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1 | /* |
2 | * ========== Copyright Header Begin ========================================== | |
3 | * | |
4 | * OpenSPARC T2 Processor File: dmu_imu_rds_intx_defines.h | |
5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
7 | * | |
8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or modify | |
11 | * it under the terms of the GNU General Public License as published by | |
12 | * the Free Software Foundation; version 2 of the License. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | * For the avoidance of doubt, and except that if any non-GPL license | |
24 | * choice is available it will apply instead, Sun elects to use only | |
25 | * the General Public License version 2 (GPLv2) at this time for any | |
26 | * software where a choice of GPL license versions is made | |
27 | * available with the language indicating that GPLv2 or any later version | |
28 | * may be used, or where a choice of which version of the GPL is applied is | |
29 | * otherwise unspecified. | |
30 | * | |
31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
33 | * have any questions. | |
34 | * | |
35 | * | |
36 | * ========== Copyright Header End ============================================ | |
37 | */ | |
38 | `ifdef FIRE_DLC_IMU_RDS_INTX_DEFINES | |
39 | `else | |
40 | `define FIRE_DLC_IMU_RDS_INTX_DEFINES | |
41 | ||
42 | `define FIRE_DLC_IMU_RDS_INTX_INSTANCE_ID_VALUE_A 1'h0 | |
43 | `define FIRE_DLC_IMU_RDS_INTX_INSTANCE_ID_VALUE_B 1'h1 | |
44 | ||
45 | //------------------------------------------------------- | |
46 | //----- Variable definitions for register fire_dlc_imu_rds_intx_csr_intx_status_reg | |
47 | //------------------------------------------------------- | |
48 | ||
49 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_HW_ADDR 27'b000000011000001011000000000 | |
50 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR 30'b000000011000001011000000000000 | |
51 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INTX_STATUS_REG_HW_ADDR 27'b000000011100001011000000000 | |
52 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INTX_STATUS_REG_ADDR 30'b000000011100001011000000000000 | |
53 | ||
54 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_WIDTH 64 | |
55 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_DEPTH 1 | |
56 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_SLC 63:0 | |
57 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_SLC 63:0 | |
58 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_POSITION 0 | |
59 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_LOW_ADDR_WIDTH 0 | |
60 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_ADDR_RANGE 26:0 | |
61 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111 | |
62 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000001111 | |
63 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
64 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
65 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
66 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
67 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
68 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000001111 | |
69 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111110000 | |
70 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
71 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
72 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INTERNAL_REG 0 | |
73 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_EXTERNAL_DECODE_REG 1 | |
74 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_ZERO_TIME_OMNI 0 | |
75 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_NUM_FIELDS 4 | |
76 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_FID 0 | |
77 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_SLC 3:3 | |
78 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_WIDTH 1 | |
79 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_INT_SLC 0:0 | |
80 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_POSITION 3 | |
81 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_FMASK 64'b0000000000000000000000000000000000000000000000000000000000001000 | |
82 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
83 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_POR_VALUE 1'b0 | |
84 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_FID 1 | |
85 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_SLC 2:2 | |
86 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_WIDTH 1 | |
87 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_INT_SLC 0:0 | |
88 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_POSITION 2 | |
89 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000100 | |
90 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
91 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_POR_VALUE 1'b0 | |
92 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_FID 2 | |
93 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_SLC 1:1 | |
94 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_WIDTH 1 | |
95 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_INT_SLC 0:0 | |
96 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_POSITION 1 | |
97 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000010 | |
98 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
99 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_POR_VALUE 1'b0 | |
100 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_FID 3 | |
101 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_SLC 0:0 | |
102 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_WIDTH 1 | |
103 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_INT_SLC 0:0 | |
104 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_POSITION 0 | |
105 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
106 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
107 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_POR_VALUE 1'b0 | |
108 | ||
109 | //------------------------------------------------------- | |
110 | //----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_a_int_clr_reg | |
111 | //------------------------------------------------------- | |
112 | ||
113 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_HW_ADDR 27'b000000011000001011000000001 | |
114 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_ADDR 30'b000000011000001011000000001000 | |
115 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_A_INT_CLR_REG_HW_ADDR 27'b000000011100001011000000001 | |
116 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_A_INT_CLR_REG_ADDR 30'b000000011100001011000000001000 | |
117 | ||
118 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH 64 | |
119 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_DEPTH 1 | |
120 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_SLC 63:0 | |
121 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_INT_SLC 63:0 | |
122 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_POSITION 0 | |
123 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_LOW_ADDR_WIDTH 0 | |
124 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_ADDR_RANGE 26:0 | |
125 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
126 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
127 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
128 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
129 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
130 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
131 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
132 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
133 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111110 | |
134 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
135 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
136 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_INTERNAL_REG 1 | |
137 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_ZERO_TIME_OMNI 1 | |
138 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_NUM_FIELDS 1 | |
139 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_FID 0 | |
140 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_SLC 0:0 | |
141 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_WIDTH 1 | |
142 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_INT_SLC 0:0 | |
143 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_POSITION 0 | |
144 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
145 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
146 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_POR_VALUE 1'b0 | |
147 | ||
148 | //------------------------------------------------------- | |
149 | //----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_b_int_clr_reg | |
150 | //------------------------------------------------------- | |
151 | ||
152 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_HW_ADDR 27'b000000011000001011000000010 | |
153 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_ADDR 30'b000000011000001011000000010000 | |
154 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_B_INT_CLR_REG_HW_ADDR 27'b000000011100001011000000010 | |
155 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_B_INT_CLR_REG_ADDR 30'b000000011100001011000000010000 | |
156 | ||
157 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WIDTH 64 | |
158 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_DEPTH 1 | |
159 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_SLC 63:0 | |
160 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_INT_SLC 63:0 | |
161 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_POSITION 0 | |
162 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_LOW_ADDR_WIDTH 0 | |
163 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_ADDR_RANGE 26:0 | |
164 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
165 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
166 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
167 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
168 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
169 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
170 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
171 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
172 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111110 | |
173 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
174 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
175 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_INTERNAL_REG 1 | |
176 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_ZERO_TIME_OMNI 1 | |
177 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_NUM_FIELDS 1 | |
178 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_FID 0 | |
179 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_SLC 0:0 | |
180 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_WIDTH 1 | |
181 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_INT_SLC 0:0 | |
182 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_POSITION 0 | |
183 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
184 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
185 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_POR_VALUE 1'b0 | |
186 | ||
187 | //------------------------------------------------------- | |
188 | //----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_c_int_clr_reg | |
189 | //------------------------------------------------------- | |
190 | ||
191 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_HW_ADDR 27'b000000011000001011000000011 | |
192 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_ADDR 30'b000000011000001011000000011000 | |
193 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_C_INT_CLR_REG_HW_ADDR 27'b000000011100001011000000011 | |
194 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_C_INT_CLR_REG_ADDR 30'b000000011100001011000000011000 | |
195 | ||
196 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH 64 | |
197 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_DEPTH 1 | |
198 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_SLC 63:0 | |
199 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_INT_SLC 63:0 | |
200 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_POSITION 0 | |
201 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_LOW_ADDR_WIDTH 0 | |
202 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_ADDR_RANGE 26:0 | |
203 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
204 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
205 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
206 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
207 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
208 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
209 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
210 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
211 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111110 | |
212 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
213 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
214 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_INTERNAL_REG 1 | |
215 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_ZERO_TIME_OMNI 1 | |
216 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_NUM_FIELDS 1 | |
217 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_FID 0 | |
218 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_SLC 0:0 | |
219 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_WIDTH 1 | |
220 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_INT_SLC 0:0 | |
221 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_POSITION 0 | |
222 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
223 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
224 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_POR_VALUE 1'b0 | |
225 | ||
226 | //------------------------------------------------------- | |
227 | //----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_d_int_clr_reg | |
228 | //------------------------------------------------------- | |
229 | ||
230 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_HW_ADDR 27'b000000011000001011000000100 | |
231 | `define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_ADDR 30'b000000011000001011000000100000 | |
232 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_D_INT_CLR_REG_HW_ADDR 27'b000000011100001011000000100 | |
233 | `define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_D_INT_CLR_REG_ADDR 30'b000000011100001011000000100000 | |
234 | ||
235 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WIDTH 64 | |
236 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_DEPTH 1 | |
237 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_SLC 63:0 | |
238 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_INT_SLC 63:0 | |
239 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_POSITION 0 | |
240 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_LOW_ADDR_WIDTH 0 | |
241 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_ADDR_RANGE 26:0 | |
242 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
243 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
244 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
245 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
246 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
247 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
248 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
249 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
250 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111111111110 | |
251 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
252 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 | |
253 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_INTERNAL_REG 1 | |
254 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_ZERO_TIME_OMNI 1 | |
255 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_NUM_FIELDS 1 | |
256 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_FID 0 | |
257 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_SLC 0:0 | |
258 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_WIDTH 1 | |
259 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_INT_SLC 0:0 | |
260 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_POSITION 0 | |
261 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
262 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 | |
263 | `define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_POR_VALUE 1'b0 | |
264 | ||
265 | ||
266 | `endif |