design/sys/iop/dmu/rtl/dmu_imu_rds_intx_defines.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_imu_rds_intx_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`ifdef FIRE_DLC_IMU_RDS_INTX_DEFINES
`else
`define FIRE_DLC_IMU_RDS_INTX_DEFINES

`define FIRE_DLC_IMU_RDS_INTX_INSTANCE_ID_VALUE_A 1'h0
`define FIRE_DLC_IMU_RDS_INTX_INSTANCE_ID_VALUE_B 1'h1

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_intx_csr_intx_status_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_HW_ADDR     27'b000000011000001011000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INTX_STATUS_REG_ADDR        30'b000000011000001011000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INTX_STATUS_REG_HW_ADDR     27'b000000011100001011000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INTX_STATUS_REG_ADDR        30'b000000011100001011000000000000

`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_WIDTH 64
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_DEPTH 1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_SLC   63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_SLC       63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_POSITION      0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_LOW_ADDR_WIDTH        0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_ADDR_RANGE    26:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_READ_MASK     64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_READ_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_WRITE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_WRITE_ONLY_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_SET_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_CLEAR_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_TOGGLE_MASK   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_RMASK 64'b0000000000000000000000000000000000000000000000000000000000001111
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_RESERVED_BIT_MASK     64'b1111111111111111111111111111111111111111111111111111111111110000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_HW_LD_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_POR_VALUE     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INTERNAL_REG  0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_EXTERNAL_DECODE_REG   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_ZERO_TIME_OMNI        0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_NUM_FIELDS    4
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_FID     0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_SLC     3:3
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_POSITION        3
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_FMASK   64'b0000000000000000000000000000000000000000000000000000000000001000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_A_POR_VALUE       1'b0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_FID     1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_SLC     2:2
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_POSITION        2
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000100
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_B_POR_VALUE       1'b0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_FID     2
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_SLC     1:1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_POSITION        1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000010
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_C_POR_VALUE       1'b0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_FID     3
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_SLC     0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_POSITION        0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INTX_STATUS_REG_INT_D_POR_VALUE       1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_a_int_clr_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_HW_ADDR   27'b000000011000001011000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_A_INT_CLR_REG_ADDR      30'b000000011000001011000000001000
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_A_INT_CLR_REG_HW_ADDR   27'b000000011100001011000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_A_INT_CLR_REG_ADDR      30'b000000011100001011000000001000

`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WIDTH       64
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_DEPTH       1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_SLC 63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_INT_SLC     63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_POSITION    0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_READ_MASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_RMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111111111111111111110
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_INTERNAL_REG        1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_NUM_FIELDS  1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_FID     0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_SLC     0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_POSITION        0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_A_INT_CLR_REG_CLR_POR_VALUE       1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_b_int_clr_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_HW_ADDR   27'b000000011000001011000000010
`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_B_INT_CLR_REG_ADDR      30'b000000011000001011000000010000
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_B_INT_CLR_REG_HW_ADDR   27'b000000011100001011000000010
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_B_INT_CLR_REG_ADDR      30'b000000011100001011000000010000

`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WIDTH       64
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_DEPTH       1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_SLC 63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_INT_SLC     63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_POSITION    0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_READ_MASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_RMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111111111111111111110
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_INTERNAL_REG        1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_NUM_FIELDS  1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_FID     0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_SLC     0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_POSITION        0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_B_INT_CLR_REG_CLR_POR_VALUE       1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_c_int_clr_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_HW_ADDR   27'b000000011000001011000000011
`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_C_INT_CLR_REG_ADDR      30'b000000011000001011000000011000
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_C_INT_CLR_REG_HW_ADDR   27'b000000011100001011000000011
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_C_INT_CLR_REG_ADDR      30'b000000011100001011000000011000

`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WIDTH       64
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_DEPTH       1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_SLC 63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_INT_SLC     63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_POSITION    0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_READ_MASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_RMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111111111111111111110
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_INTERNAL_REG        1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_NUM_FIELDS  1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_FID     0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_SLC     0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_POSITION        0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_C_INT_CLR_REG_CLR_POR_VALUE       1'b0

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_rds_intx_csr_int_d_int_clr_reg
//-------------------------------------------------------

`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_HW_ADDR   27'b000000011000001011000000100
`define FIRE_DLC_IMU_RDS_INTX_CSR_A_INT_D_INT_CLR_REG_ADDR      30'b000000011000001011000000100000
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_D_INT_CLR_REG_HW_ADDR   27'b000000011100001011000000100
`define FIRE_DLC_IMU_RDS_INTX_CSR_B_INT_D_INT_CLR_REG_ADDR      30'b000000011100001011000000100000

`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WIDTH       64
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_DEPTH       1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_SLC 63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_INT_SLC     63:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_POSITION    0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_LOW_ADDR_WIDTH      0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_ADDR_RANGE  26:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_READ_MASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_READ_ONLY_MASK      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WRITE_MASK  64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_WRITE_ONLY_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_SET_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLEAR_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_RMASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_RESERVED_BIT_MASK   64'b1111111111111111111111111111111111111111111111111111111111111110
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_HW_LD_MASK  64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_POR_VALUE   64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_INTERNAL_REG        1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_ZERO_TIME_OMNI      1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_NUM_FIELDS  1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_FID     0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_SLC     0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_WIDTH   1
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_INT_SLC 0:0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_POSITION        0
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_FMASK   64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_HW_LD_MASK      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_RDS_INTX_CSR_INT_D_INT_CLR_REG_CLR_POR_VALUE       1'b0


`endif