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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / mcu / rtl / mcu_lndskw_dp.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: mcu_lndskw_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module mcu_lndskw_dp (
36 lndskw_data,
37 lndskw_ts0_hdr_match,
38 lndskw_status_parity,
39 lndskw_idle_match,
40 lndskw_alert_match,
41 lndskw_alert_asserted,
42 lndskw_nbde,
43 lndskw_thermal_trip,
44 fbd_data,
45 fbdic_clr_ptrs,
46 fbdic_inc_wptr,
47 fbdic_inc_rptr,
48 fbdic_failover_mask,
49 fbdic_failover_mask_l,
50 fdout_idle_lfsr,
51 fdout_idle_lfsr_l_0,
52 fdout_idle_lfsr_0,
53 drl2clk,
54 scan_in,
55 scan_out,
56 tcu_pce_ov,
57 tcu_aclk,
58 tcu_bclk,
59 tcu_scan_en,
60 wmr_scan_in,
61 wmr_scan_out,
62 aclk_wmr);
63wire [167:0] mux_fbd_data;
64wire algnbf0_wmr_scanin;
65wire algnbf0_wmr_scanout;
66wire algnbf0_scanin;
67wire algnbf0_scanout;
68wire algnbf1_wmr_scanin;
69wire algnbf1_wmr_scanout;
70wire algnbf1_scanin;
71wire algnbf1_scanout;
72wire algnbf2_wmr_scanin;
73wire algnbf2_wmr_scanout;
74wire algnbf2_scanin;
75wire algnbf2_scanout;
76wire algnbf3_wmr_scanin;
77wire algnbf3_wmr_scanout;
78wire algnbf3_scanin;
79wire algnbf3_scanout;
80wire algnbf4_wmr_scanin;
81wire algnbf4_wmr_scanout;
82wire algnbf4_scanin;
83wire algnbf4_scanout;
84wire algnbf5_wmr_scanin;
85wire algnbf5_wmr_scanout;
86wire algnbf5_scanin;
87wire algnbf5_scanout;
88wire algnbf6_wmr_scanin;
89wire algnbf6_wmr_scanout;
90wire algnbf6_scanin;
91wire algnbf6_scanout;
92wire algnbf7_wmr_scanin;
93wire algnbf7_wmr_scanout;
94wire algnbf7_scanin;
95wire algnbf7_scanout;
96wire algnbf8_wmr_scanin;
97wire algnbf8_wmr_scanout;
98wire algnbf8_scanin;
99wire algnbf8_scanout;
100wire algnbf9_wmr_scanin;
101wire algnbf9_wmr_scanout;
102wire algnbf9_scanin;
103wire algnbf9_scanout;
104wire algnbf10_wmr_scanin;
105wire algnbf10_wmr_scanout;
106wire algnbf10_scanin;
107wire algnbf10_scanout;
108wire algnbf11_wmr_scanin;
109wire algnbf11_wmr_scanout;
110wire algnbf11_scanin;
111wire algnbf11_scanout;
112wire [1:0] lndskw_status_parity_unused;
113wire [1:0] lndskw_alert_asserted_unused;
114wire [1:0] lndskw_nbde_unused;
115wire [3:0] lndskw_thermal_trip_unused;
116wire algnbf12_wmr_scanin;
117wire algnbf12_wmr_scanout;
118wire algnbf12_scanin;
119wire algnbf12_scanout;
120wire algnbf13_wmr_scanin;
121wire algnbf13_wmr_scanout;
122wire algnbf13_scanin;
123wire algnbf13_scanout;
124
125
126output [167:0] lndskw_data;
127
128output [13:0] lndskw_ts0_hdr_match;
129output [11:0] lndskw_status_parity;
130output [13:0] lndskw_idle_match;
131output [13:0] lndskw_alert_match;
132output [11:0] lndskw_alert_asserted;
133output [11:0] lndskw_nbde;
134output [23:0] lndskw_thermal_trip;
135
136input [167:0] fbd_data;
137input fbdic_clr_ptrs;
138input fbdic_inc_wptr;
139input [13:0] fbdic_inc_rptr;
140input [12:0] fbdic_failover_mask;
141input [12:0] fbdic_failover_mask_l;
142input [11:0] fdout_idle_lfsr;
143input fdout_idle_lfsr_l_0;
144input [1:0] fdout_idle_lfsr_0;
145
146input drl2clk;
147input scan_in;
148output scan_out;
149input tcu_pce_ov;
150input tcu_aclk;
151input tcu_bclk;
152input tcu_scan_en;
153
154input wmr_scan_in;
155output wmr_scan_out;
156input aclk_wmr;
157
158mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_11_0 (
159 .din0(fbd_data[11:0]),
160 .din1(fbd_data[23:12]),
161 .sel0(fbdic_failover_mask_l[0]),
162 .sel1(fbdic_failover_mask[0]),
163 .dout(mux_fbd_data[11:0]));
164
165mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_23_12 (
166 .din0(fbd_data[23:12]),
167 .din1(fbd_data[35:24]),
168 .sel0(fbdic_failover_mask_l[1]),
169 .sel1(fbdic_failover_mask[1]),
170 .dout(mux_fbd_data[23:12]));
171
172mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_35_24 (
173 .din0(fbd_data[35:24]),
174 .din1(fbd_data[47:36]),
175 .sel0(fbdic_failover_mask_l[2]),
176 .sel1(fbdic_failover_mask[2]),
177 .dout(mux_fbd_data[35:24]));
178
179mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_47_36 (
180 .din0(fbd_data[47:36]),
181 .din1(fbd_data[59:48]),
182 .sel0(fbdic_failover_mask_l[3]),
183 .sel1(fbdic_failover_mask[3]),
184 .dout(mux_fbd_data[47:36]));
185
186mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_59_48 (
187 .din0(fbd_data[59:48]),
188 .din1(fbd_data[71:60]),
189 .sel0(fbdic_failover_mask_l[4]),
190 .sel1(fbdic_failover_mask[4]),
191 .dout(mux_fbd_data[59:48]));
192
193mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_71_60 (
194 .din0(fbd_data[71:60]),
195 .din1(fbd_data[83:72]),
196 .sel0(fbdic_failover_mask_l[5]),
197 .sel1(fbdic_failover_mask[5]),
198 .dout(mux_fbd_data[71:60]));
199
200mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_83_72 (
201 .din0(fbd_data[83:72]),
202 .din1(fbd_data[95:84]),
203 .sel0(fbdic_failover_mask_l[6]),
204 .sel1(fbdic_failover_mask[6]),
205 .dout(mux_fbd_data[83:72]));
206
207mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_95_84 (
208 .din0(fbd_data[95:84]),
209 .din1(fbd_data[107:96]),
210 .sel0(fbdic_failover_mask_l[7]),
211 .sel1(fbdic_failover_mask[7]),
212 .dout(mux_fbd_data[95:84]));
213
214mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_107_96 (
215 .din0(fbd_data[107:96]),
216 .din1(fbd_data[119:108]),
217 .sel0(fbdic_failover_mask_l[8]),
218 .sel1(fbdic_failover_mask[8]),
219 .dout(mux_fbd_data[107:96]));
220
221mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_119_108 (
222 .din0(fbd_data[119:108]),
223 .din1(fbd_data[131:120]),
224 .sel0(fbdic_failover_mask_l[9]),
225 .sel1(fbdic_failover_mask[9]),
226 .dout(mux_fbd_data[119:108]));
227
228mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_131_120 (
229 .din0(fbd_data[131:120]),
230 .din1(fbd_data[143:132]),
231 .sel0(fbdic_failover_mask_l[10]),
232 .sel1(fbdic_failover_mask[10]),
233 .dout(mux_fbd_data[131:120]));
234
235mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_143_132 (
236 .din0(fbd_data[143:132]),
237 .din1(fbd_data[155:144]),
238 .sel0(fbdic_failover_mask_l[11]),
239 .sel1(fbdic_failover_mask[11]),
240 .dout(mux_fbd_data[143:132]));
241
242mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 m_mux_failover_155_144 (
243 .din0(fbd_data[155:144]),
244 .din1(fbd_data[167:156]),
245 .sel0(fbdic_failover_mask_l[12]),
246 .sel1(fbdic_failover_mask[12]),
247 .dout(mux_fbd_data[155:144]));
248
249assign mux_fbd_data[167:156] = fbd_data[167:156];
250
251mcu_algnbf_dp algnbf0 ( // FS:wmr_protect
252 .din(mux_fbd_data[11:0]),
253 .dout(lndskw_data[11:0]),
254 .ts0_hdr_match(lndskw_ts0_hdr_match[0]),
255 .status_parity(lndskw_status_parity[0]),
256 .idle_match(lndskw_idle_match[0]),
257 .alert_match(lndskw_alert_match[0]),
258 .alert_asserted(lndskw_alert_asserted[0]),
259 .nbde(lndskw_nbde[0]),
260 .thermal_trip(lndskw_thermal_trip[1:0]),
261 .inc_rptr(fbdic_inc_rptr[0]),
262 .inc_wptr(fbdic_inc_wptr),
263 .clr_ptrs(fbdic_clr_ptrs),
264 .lfsr_bit({2{fdout_idle_lfsr_0[0]}}),
265 .wmr_scan_in(algnbf0_wmr_scanin),
266 .wmr_scan_out(algnbf0_wmr_scanout),
267 .scan_in(algnbf0_scanin),
268 .scan_out(algnbf0_scanout),
269 .drl2clk(drl2clk),
270 .tcu_pce_ov(tcu_pce_ov),
271 .tcu_aclk(tcu_aclk),
272 .tcu_bclk(tcu_bclk),
273 .tcu_scan_en(tcu_scan_en),
274 .aclk_wmr(aclk_wmr)
275);
276
277mcu_algnbf_dp algnbf1 ( // FS:wmr_protect
278 .din(mux_fbd_data[23:12]),
279 .dout(lndskw_data[23:12]),
280 .ts0_hdr_match(lndskw_ts0_hdr_match[1]),
281 .status_parity(lndskw_status_parity[1]),
282 .idle_match(lndskw_idle_match[1]),
283 .alert_match(lndskw_alert_match[1]),
284 .alert_asserted(lndskw_alert_asserted[1]),
285 .nbde(lndskw_nbde[1]),
286 .thermal_trip(lndskw_thermal_trip[3:2]),
287 .inc_rptr(fbdic_inc_rptr[1]),
288 .inc_wptr(fbdic_inc_wptr),
289 .clr_ptrs(fbdic_clr_ptrs),
290 .lfsr_bit({2{fdout_idle_lfsr[1]}}),
291 .wmr_scan_in(algnbf1_wmr_scanin),
292 .wmr_scan_out(algnbf1_wmr_scanout),
293 .scan_in(algnbf1_scanin),
294 .scan_out(algnbf1_scanout),
295 .drl2clk(drl2clk),
296 .tcu_pce_ov(tcu_pce_ov),
297 .tcu_aclk(tcu_aclk),
298 .tcu_bclk(tcu_bclk),
299 .tcu_scan_en(tcu_scan_en),
300 .aclk_wmr(aclk_wmr)
301);
302
303mcu_algnbf_dp algnbf2 ( // FS:wmr_protect
304 .din(mux_fbd_data[35:24]),
305 .dout(lndskw_data[35:24]),
306 .ts0_hdr_match(lndskw_ts0_hdr_match[2]),
307 .status_parity(lndskw_status_parity[2]),
308 .idle_match(lndskw_idle_match[2]),
309 .alert_match(lndskw_alert_match[2]),
310 .alert_asserted(lndskw_alert_asserted[2]),
311 .nbde(lndskw_nbde[2]),
312 .thermal_trip(lndskw_thermal_trip[5:4]),
313 .inc_rptr(fbdic_inc_rptr[2]),
314 .inc_wptr(fbdic_inc_wptr),
315 .clr_ptrs(fbdic_clr_ptrs),
316 .lfsr_bit({2{fdout_idle_lfsr[2]}}),
317 .wmr_scan_in(algnbf2_wmr_scanin),
318 .wmr_scan_out(algnbf2_wmr_scanout),
319 .scan_in(algnbf2_scanin),
320 .scan_out(algnbf2_scanout),
321 .drl2clk(drl2clk),
322 .tcu_pce_ov(tcu_pce_ov),
323 .tcu_aclk(tcu_aclk),
324 .tcu_bclk(tcu_bclk),
325 .tcu_scan_en(tcu_scan_en),
326 .aclk_wmr(aclk_wmr)
327);
328
329mcu_algnbf_dp algnbf3 ( // FS:wmr_protect
330 .din(mux_fbd_data[47:36]),
331 .dout(lndskw_data[47:36]),
332 .ts0_hdr_match(lndskw_ts0_hdr_match[3]),
333 .status_parity(lndskw_status_parity[3]),
334 .idle_match(lndskw_idle_match[3]),
335 .alert_match(lndskw_alert_match[3]),
336 .alert_asserted(lndskw_alert_asserted[3]),
337 .nbde(lndskw_nbde[3]),
338 .thermal_trip(lndskw_thermal_trip[7:6]),
339 .inc_rptr(fbdic_inc_rptr[3]),
340 .inc_wptr(fbdic_inc_wptr),
341 .clr_ptrs(fbdic_clr_ptrs),
342 .lfsr_bit({2{fdout_idle_lfsr[3]}}),
343 .wmr_scan_in(algnbf3_wmr_scanin),
344 .wmr_scan_out(algnbf3_wmr_scanout),
345 .scan_in(algnbf3_scanin),
346 .scan_out(algnbf3_scanout),
347 .drl2clk(drl2clk),
348 .tcu_pce_ov(tcu_pce_ov),
349 .tcu_aclk(tcu_aclk),
350 .tcu_bclk(tcu_bclk),
351 .tcu_scan_en(tcu_scan_en),
352 .aclk_wmr(aclk_wmr)
353);
354
355mcu_algnbf_dp algnbf4 ( // FS:wmr_protect
356 .din(mux_fbd_data[59:48]),
357 .dout(lndskw_data[59:48]),
358 .ts0_hdr_match(lndskw_ts0_hdr_match[4]),
359 .status_parity(lndskw_status_parity[4]),
360 .idle_match(lndskw_idle_match[4]),
361 .alert_match(lndskw_alert_match[4]),
362 .alert_asserted(lndskw_alert_asserted[4]),
363 .nbde(lndskw_nbde[4]),
364 .thermal_trip(lndskw_thermal_trip[9:8]),
365 .inc_rptr(fbdic_inc_rptr[4]),
366 .inc_wptr(fbdic_inc_wptr),
367 .clr_ptrs(fbdic_clr_ptrs),
368 .lfsr_bit({2{fdout_idle_lfsr[4]}}),
369 .wmr_scan_in(algnbf4_wmr_scanin),
370 .wmr_scan_out(algnbf4_wmr_scanout),
371 .scan_in(algnbf4_scanin),
372 .scan_out(algnbf4_scanout),
373 .drl2clk(drl2clk),
374 .tcu_pce_ov(tcu_pce_ov),
375 .tcu_aclk(tcu_aclk),
376 .tcu_bclk(tcu_bclk),
377 .tcu_scan_en(tcu_scan_en),
378 .aclk_wmr(aclk_wmr)
379);
380
381mcu_algnbf_dp algnbf5 ( // FS:wmr_protect
382 .din(mux_fbd_data[71:60]),
383 .dout(lndskw_data[71:60]),
384 .ts0_hdr_match(lndskw_ts0_hdr_match[5]),
385 .status_parity(lndskw_status_parity[5]),
386 .idle_match(lndskw_idle_match[5]),
387 .alert_match(lndskw_alert_match[5]),
388 .alert_asserted(lndskw_alert_asserted[5]),
389 .nbde(lndskw_nbde[5]),
390 .thermal_trip(lndskw_thermal_trip[11:10]),
391 .inc_rptr(fbdic_inc_rptr[5]),
392 .inc_wptr(fbdic_inc_wptr),
393 .clr_ptrs(fbdic_clr_ptrs),
394 .lfsr_bit({2{fdout_idle_lfsr[5]}}),
395 .wmr_scan_in(algnbf5_wmr_scanin),
396 .wmr_scan_out(algnbf5_wmr_scanout),
397 .scan_in(algnbf5_scanin),
398 .scan_out(algnbf5_scanout),
399 .drl2clk(drl2clk),
400 .tcu_pce_ov(tcu_pce_ov),
401 .tcu_aclk(tcu_aclk),
402 .tcu_bclk(tcu_bclk),
403 .tcu_scan_en(tcu_scan_en),
404 .aclk_wmr(aclk_wmr)
405);
406
407mcu_algnbf_dp algnbf6 ( // FS:wmr_protect
408 .din(mux_fbd_data[83:72]),
409 .dout(lndskw_data[83:72]),
410 .ts0_hdr_match(lndskw_ts0_hdr_match[6]),
411 .status_parity(lndskw_status_parity[6]),
412 .idle_match(lndskw_idle_match[6]),
413 .alert_match(lndskw_alert_match[6]),
414 .alert_asserted(lndskw_alert_asserted[6]),
415 .nbde(lndskw_nbde[6]),
416 .thermal_trip(lndskw_thermal_trip[13:12]),
417 .inc_rptr(fbdic_inc_rptr[6]),
418 .inc_wptr(fbdic_inc_wptr),
419 .clr_ptrs(fbdic_clr_ptrs),
420 .lfsr_bit({2{fdout_idle_lfsr[6]}}),
421 .wmr_scan_in(algnbf6_wmr_scanin),
422 .wmr_scan_out(algnbf6_wmr_scanout),
423 .scan_in(algnbf6_scanin),
424 .scan_out(algnbf6_scanout),
425 .drl2clk(drl2clk),
426 .tcu_pce_ov(tcu_pce_ov),
427 .tcu_aclk(tcu_aclk),
428 .tcu_bclk(tcu_bclk),
429 .tcu_scan_en(tcu_scan_en),
430 .aclk_wmr(aclk_wmr)
431);
432
433mcu_algnbf_dp algnbf7 ( // FS:wmr_protect
434 .din(mux_fbd_data[95:84]),
435 .dout(lndskw_data[95:84]),
436 .ts0_hdr_match(lndskw_ts0_hdr_match[7]),
437 .status_parity(lndskw_status_parity[7]),
438 .idle_match(lndskw_idle_match[7]),
439 .alert_match(lndskw_alert_match[7]),
440 .alert_asserted(lndskw_alert_asserted[7]),
441 .nbde(lndskw_nbde[7]),
442 .thermal_trip(lndskw_thermal_trip[15:14]),
443 .inc_rptr(fbdic_inc_rptr[7]),
444 .inc_wptr(fbdic_inc_wptr),
445 .clr_ptrs(fbdic_clr_ptrs),
446 .lfsr_bit({2{fdout_idle_lfsr[7]}}),
447 .wmr_scan_in(algnbf7_wmr_scanin),
448 .wmr_scan_out(algnbf7_wmr_scanout),
449 .scan_in(algnbf7_scanin),
450 .scan_out(algnbf7_scanout),
451 .drl2clk(drl2clk),
452 .tcu_pce_ov(tcu_pce_ov),
453 .tcu_aclk(tcu_aclk),
454 .tcu_bclk(tcu_bclk),
455 .tcu_scan_en(tcu_scan_en),
456 .aclk_wmr(aclk_wmr)
457);
458
459mcu_algnbf_dp algnbf8 ( // FS:wmr_protect
460 .din(mux_fbd_data[107:96]),
461 .dout(lndskw_data[107:96]),
462 .ts0_hdr_match(lndskw_ts0_hdr_match[8]),
463 .status_parity(lndskw_status_parity[8]),
464 .idle_match(lndskw_idle_match[8]),
465 .alert_match(lndskw_alert_match[8]),
466 .alert_asserted(lndskw_alert_asserted[8]),
467 .nbde(lndskw_nbde[8]),
468 .thermal_trip(lndskw_thermal_trip[17:16]),
469 .inc_rptr(fbdic_inc_rptr[8]),
470 .inc_wptr(fbdic_inc_wptr),
471 .clr_ptrs(fbdic_clr_ptrs),
472 .lfsr_bit({2{fdout_idle_lfsr[8]}}),
473 .wmr_scan_in(algnbf8_wmr_scanin),
474 .wmr_scan_out(algnbf8_wmr_scanout),
475 .scan_in(algnbf8_scanin),
476 .scan_out(algnbf8_scanout),
477 .drl2clk(drl2clk),
478 .tcu_pce_ov(tcu_pce_ov),
479 .tcu_aclk(tcu_aclk),
480 .tcu_bclk(tcu_bclk),
481 .tcu_scan_en(tcu_scan_en),
482 .aclk_wmr(aclk_wmr)
483);
484
485mcu_algnbf_dp algnbf9 ( // FS:wmr_protect
486 .din(mux_fbd_data[119:108]),
487 .dout(lndskw_data[119:108]),
488 .ts0_hdr_match(lndskw_ts0_hdr_match[9]),
489 .status_parity(lndskw_status_parity[9]),
490 .idle_match(lndskw_idle_match[9]),
491 .alert_match(lndskw_alert_match[9]),
492 .alert_asserted(lndskw_alert_asserted[9]),
493 .nbde(lndskw_nbde[9]),
494 .thermal_trip(lndskw_thermal_trip[19:18]),
495 .inc_rptr(fbdic_inc_rptr[9]),
496 .inc_wptr(fbdic_inc_wptr),
497 .clr_ptrs(fbdic_clr_ptrs),
498 .lfsr_bit({2{fdout_idle_lfsr[9]}}),
499 .wmr_scan_in(algnbf9_wmr_scanin),
500 .wmr_scan_out(algnbf9_wmr_scanout),
501 .scan_in(algnbf9_scanin),
502 .scan_out(algnbf9_scanout),
503 .drl2clk(drl2clk),
504 .tcu_pce_ov(tcu_pce_ov),
505 .tcu_aclk(tcu_aclk),
506 .tcu_bclk(tcu_bclk),
507 .tcu_scan_en(tcu_scan_en),
508 .aclk_wmr(aclk_wmr)
509);
510
511mcu_algnbf_dp algnbf10 ( // FS:wmr_protect
512 .din(mux_fbd_data[131:120]),
513 .dout(lndskw_data[131:120]),
514 .ts0_hdr_match(lndskw_ts0_hdr_match[10]),
515 .status_parity(lndskw_status_parity[10]),
516 .idle_match(lndskw_idle_match[10]),
517 .alert_match(lndskw_alert_match[10]),
518 .alert_asserted(lndskw_alert_asserted[10]),
519 .nbde(lndskw_nbde[10]),
520 .thermal_trip(lndskw_thermal_trip[21:20]),
521 .inc_rptr(fbdic_inc_rptr[10]),
522 .inc_wptr(fbdic_inc_wptr),
523 .clr_ptrs(fbdic_clr_ptrs),
524 .lfsr_bit({2{fdout_idle_lfsr[10]}}),
525 .wmr_scan_in(algnbf10_wmr_scanin),
526 .wmr_scan_out(algnbf10_wmr_scanout),
527 .scan_in(algnbf10_scanin),
528 .scan_out(algnbf10_scanout),
529 .drl2clk(drl2clk),
530 .tcu_pce_ov(tcu_pce_ov),
531 .tcu_aclk(tcu_aclk),
532 .tcu_bclk(tcu_bclk),
533 .tcu_scan_en(tcu_scan_en),
534 .aclk_wmr(aclk_wmr)
535);
536
537mcu_algnbf_dp algnbf11 ( // FS:wmr_protect
538 .din(mux_fbd_data[143:132]),
539 .dout(lndskw_data[143:132]),
540 .ts0_hdr_match(lndskw_ts0_hdr_match[11]),
541 .status_parity(lndskw_status_parity[11]),
542 .idle_match(lndskw_idle_match[11]),
543 .alert_match(lndskw_alert_match[11]),
544 .alert_asserted(lndskw_alert_asserted[11]),
545 .nbde(lndskw_nbde[11]),
546 .thermal_trip(lndskw_thermal_trip[23:22]),
547 .inc_rptr(fbdic_inc_rptr[11]),
548 .inc_wptr(fbdic_inc_wptr),
549 .clr_ptrs(fbdic_clr_ptrs),
550 .lfsr_bit({2{fdout_idle_lfsr[11]}}),
551 .wmr_scan_in(algnbf11_wmr_scanin),
552 .wmr_scan_out(algnbf11_wmr_scanout),
553 .scan_in(algnbf11_scanin),
554 .scan_out(algnbf11_scanout),
555 .drl2clk(drl2clk),
556 .tcu_pce_ov(tcu_pce_ov),
557 .tcu_aclk(tcu_aclk),
558 .tcu_bclk(tcu_bclk),
559 .tcu_scan_en(tcu_scan_en),
560 .aclk_wmr(aclk_wmr)
561);
562
563mcu_algnbf_dp algnbf12 ( // FS:wmr_protect
564 .din(mux_fbd_data[155:144]),
565 .dout(lndskw_data[155:144]),
566 .ts0_hdr_match(lndskw_ts0_hdr_match[12]),
567 .status_parity(lndskw_status_parity_unused[0]),
568 .idle_match(lndskw_idle_match[12]),
569 .alert_match(lndskw_alert_match[12]),
570 .alert_asserted(lndskw_alert_asserted_unused[0]),
571 .nbde(lndskw_nbde_unused[0]),
572 .thermal_trip(lndskw_thermal_trip_unused[1:0]),
573 .inc_rptr(fbdic_inc_rptr[12]),
574 .inc_wptr(fbdic_inc_wptr),
575 .clr_ptrs(fbdic_clr_ptrs),
576 .lfsr_bit({fdout_idle_lfsr_l_0,fdout_idle_lfsr[0]}),
577 .wmr_scan_in(algnbf12_wmr_scanin),
578 .wmr_scan_out(algnbf12_wmr_scanout),
579 .scan_in(algnbf12_scanin),
580 .scan_out(algnbf12_scanout),
581 .drl2clk(drl2clk),
582 .tcu_pce_ov(tcu_pce_ov),
583 .tcu_aclk(tcu_aclk),
584 .tcu_bclk(tcu_bclk),
585 .tcu_scan_en(tcu_scan_en),
586 .aclk_wmr(aclk_wmr)
587);
588
589mcu_algnbf_dp algnbf13 ( // FS:wmr_protect
590 .din(mux_fbd_data[167:156]),
591 .dout(lndskw_data[167:156]),
592 .ts0_hdr_match(lndskw_ts0_hdr_match[13]),
593 .status_parity(lndskw_status_parity_unused[1]),
594 .idle_match(lndskw_idle_match[13]),
595 .alert_match(lndskw_alert_match[13]),
596 .alert_asserted(lndskw_alert_asserted_unused[1]),
597 .nbde(lndskw_nbde_unused[1]),
598 .thermal_trip(lndskw_thermal_trip_unused[3:2]),
599 .inc_rptr(fbdic_inc_rptr[13]),
600 .inc_wptr(fbdic_inc_wptr),
601 .clr_ptrs(fbdic_clr_ptrs),
602 .lfsr_bit({2{fdout_idle_lfsr_0[1]}}),
603 .wmr_scan_in(algnbf13_wmr_scanin),
604 .wmr_scan_out(algnbf13_wmr_scanout),
605 .scan_in(algnbf13_scanin),
606 .scan_out(algnbf13_scanout),
607 .drl2clk(drl2clk),
608 .tcu_pce_ov(tcu_pce_ov),
609 .tcu_aclk(tcu_aclk),
610 .tcu_bclk(tcu_bclk),
611 .tcu_scan_en(tcu_scan_en),
612 .aclk_wmr(aclk_wmr)
613);
614
615// fixscan start:
616assign algnbf0_scanin = scan_in ;
617assign algnbf1_scanin = algnbf0_scanout ;
618assign algnbf2_scanin = algnbf1_scanout ;
619assign algnbf3_scanin = algnbf2_scanout ;
620assign algnbf4_scanin = algnbf3_scanout ;
621assign algnbf5_scanin = algnbf4_scanout ;
622assign algnbf6_scanin = algnbf5_scanout ;
623assign algnbf7_scanin = algnbf6_scanout ;
624assign algnbf8_scanin = algnbf7_scanout ;
625assign algnbf9_scanin = algnbf8_scanout ;
626assign algnbf10_scanin = algnbf9_scanout ;
627assign algnbf11_scanin = algnbf10_scanout ;
628assign algnbf12_scanin = algnbf11_scanout ;
629assign algnbf13_scanin = algnbf12_scanout ;
630assign scan_out = algnbf13_scanout ;
631
632assign algnbf0_wmr_scanin = wmr_scan_in ;
633assign algnbf1_wmr_scanin = algnbf0_wmr_scanout ;
634assign algnbf2_wmr_scanin = algnbf1_wmr_scanout ;
635assign algnbf3_wmr_scanin = algnbf2_wmr_scanout ;
636assign algnbf4_wmr_scanin = algnbf3_wmr_scanout ;
637assign algnbf5_wmr_scanin = algnbf4_wmr_scanout ;
638assign algnbf6_wmr_scanin = algnbf5_wmr_scanout ;
639assign algnbf7_wmr_scanin = algnbf6_wmr_scanout ;
640assign algnbf8_wmr_scanin = algnbf7_wmr_scanout ;
641assign algnbf9_wmr_scanin = algnbf8_wmr_scanout ;
642assign algnbf10_wmr_scanin = algnbf9_wmr_scanout ;
643assign algnbf11_wmr_scanin = algnbf10_wmr_scanout ;
644assign algnbf12_wmr_scanin = algnbf11_wmr_scanout ;
645assign algnbf13_wmr_scanin = algnbf12_wmr_scanout ;
646assign wmr_scan_out = algnbf13_wmr_scanout ;
647// fixscan end:
648endmodule
649
650
651// general mux macro for pass-gate and and-or muxes with/wout priority encoders
652// also for pass-gate with decoder
653
654
655
656
657
658// any PARAMS parms go into naming of macro
659
660module mcu_lndskw_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 (
661 din0,
662 sel0,
663 din1,
664 sel1,
665 dout);
666 input [11:0] din0;
667 input sel0;
668 input [11:0] din1;
669 input sel1;
670 output [11:0] dout;
671
672
673
674
675
676mux2s #(12) d0_0 (
677 .sel0(sel0),
678 .sel1(sel1),
679 .in0(din0[11:0]),
680 .in1(din1[11:0]),
681.dout(dout[11:0])
682);
683
684endmodule
685
686
687//
688// comparator macro (output is 1 if both inputs are equal; 0 otherwise)
689//
690//
691
692
693
694
695
696module mcu_lndskw_dp_cmp_macro__width_12 (
697 din0,
698 din1,
699 dout);
700 input [11:0] din0;
701 input [11:0] din1;
702 output dout;
703
704
705
706
707
708
709cmp #(12) m0_0 (
710.in0(din0[11:0]),
711.in1(din1[11:0]),
712.out(dout)
713);
714
715
716
717
718
719
720
721
722
723
724endmodule
725
726
727
728
729
730//
731// xor macro for ports = 2,3
732//
733//
734
735
736
737
738
739module mcu_lndskw_dp_xor_macro__ports_3 (
740 din0,
741 din1,
742 din2,
743 dout);
744 input [0:0] din0;
745 input [0:0] din1;
746 input [0:0] din2;
747 output [0:0] dout;
748
749
750
751
752
753xor3 #(1) d0_0 (
754.in0(din0[0:0]),
755.in1(din1[0:0]),
756.in2(din2[0:0]),
757.out(dout[0:0])
758);
759
760
761
762
763
764
765
766
767endmodule
768
769
770
771
772
773//
774// invert macro
775//
776//
777
778
779
780
781
782module mcu_lndskw_dp_inv_macro__width_2 (
783 din,
784 dout);
785 input [1:0] din;
786 output [1:0] dout;
787
788
789
790
791
792
793inv #(2) d0_0 (
794.in(din[1:0]),
795.out(dout[1:0])
796);
797
798
799
800
801
802
803
804
805
806endmodule
807
808
809
810
811
812//
813// and macro for ports = 2,3,4
814//
815//
816
817
818
819
820
821module mcu_lndskw_dp_and_macro__width_1 (
822 din0,
823 din1,
824 dout);
825 input [0:0] din0;
826 input [0:0] din1;
827 output [0:0] dout;
828
829
830
831
832
833
834and2 #(1) d0_0 (
835.in0(din0[0:0]),
836.in1(din1[0:0]),
837.out(dout[0:0])
838);
839
840
841
842
843
844
845
846
847
848endmodule
849
850
851
852
853
854//
855// and macro for ports = 2,3,4
856//
857//
858
859
860
861
862
863module mcu_lndskw_dp_and_macro__width_2 (
864 din0,
865 din1,
866 dout);
867 input [1:0] din0;
868 input [1:0] din1;
869 output [1:0] dout;
870
871
872
873
874
875
876and2 #(2) d0_0 (
877.in0(din0[1:0]),
878.in1(din1[1:0]),
879.out(dout[1:0])
880);
881
882
883
884
885
886
887
888
889
890endmodule
891
892
893
894
895
896//
897// or macro for ports = 2,3
898//
899//
900
901
902
903
904
905module mcu_lndskw_dp_or_macro__width_2 (
906 din0,
907 din1,
908 dout);
909 input [1:0] din0;
910 input [1:0] din1;
911 output [1:0] dout;
912
913
914
915
916
917
918or2 #(2) d0_0 (
919.in0(din0[1:0]),
920.in1(din1[1:0]),
921.out(dout[1:0])
922);
923
924
925
926
927
928
929
930
931
932endmodule
933
934
935
936
937
938//
939// increment macro
940//
941//
942
943
944
945
946
947module mcu_lndskw_dp_increment_macro__width_4 (
948 din,
949 cin,
950 dout,
951 cout);
952 input [3:0] din;
953 input cin;
954 output [3:0] dout;
955 output cout;
956
957
958
959
960
961
962incr #(4) m0_0 (
963.cin(cin),
964.in(din[3:0]),
965.out(dout[3:0]),
966.cout(cout)
967);
968
969
970
971
972
973
974
975
976
977
978
979endmodule
980
981
982
983
984
985//
986// invert macro
987//
988//
989
990
991
992
993
994module mcu_lndskw_dp_inv_macro__width_3 (
995 din,
996 dout);
997 input [2:0] din;
998 output [2:0] dout;
999
1000
1001
1002
1003
1004
1005inv #(3) d0_0 (
1006.in(din[2:0]),
1007.out(dout[2:0])
1008);
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018endmodule
1019
1020
1021
1022
1023
1024//
1025// and macro for ports = 2,3,4
1026//
1027//
1028
1029
1030
1031
1032
1033module mcu_lndskw_dp_and_macro__ports_2__width_3 (
1034 din0,
1035 din1,
1036 dout);
1037 input [2:0] din0;
1038 input [2:0] din1;
1039 output [2:0] dout;
1040
1041
1042
1043
1044
1045
1046and2 #(3) d0_0 (
1047.in0(din0[2:0]),
1048.in1(din1[2:0]),
1049.out(dout[2:0])
1050);
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060endmodule
1061
1062
1063
1064
1065
1066//
1067// or macro for ports = 2,3
1068//
1069//
1070
1071
1072
1073
1074
1075module mcu_lndskw_dp_or_macro__ports_2__width_1 (
1076 din0,
1077 din1,
1078 dout);
1079 input [0:0] din0;
1080 input [0:0] din1;
1081 output [0:0] dout;
1082
1083
1084
1085
1086
1087
1088or2 #(1) d0_0 (
1089.in0(din0[0:0]),
1090.in1(din1[0:0]),
1091.out(dout[0:0])
1092);
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102endmodule
1103
1104
1105
1106
1107
1108//
1109// nor macro for ports = 2,3
1110//
1111//
1112
1113
1114
1115
1116
1117module mcu_lndskw_dp_nor_macro__ports_3 (
1118 din0,
1119 din1,
1120 din2,
1121 dout);
1122 input [0:0] din0;
1123 input [0:0] din1;
1124 input [0:0] din2;
1125 output [0:0] dout;
1126
1127
1128
1129
1130
1131
1132nor3 #(1) d0_0 (
1133.in0(din0[0:0]),
1134.in1(din1[0:0]),
1135.in2(din2[0:0]),
1136.out(dout[0:0])
1137);
1138
1139
1140
1141
1142
1143
1144
1145endmodule
1146
1147
1148
1149
1150
1151// general mux macro for pass-gate and and-or muxes with/wout priority encoders
1152// also for pass-gate with decoder
1153
1154
1155
1156
1157
1158// any PARAMS parms go into naming of macro
1159
1160module mcu_lndskw_dp_mux_macro__mux_aonpe__ports_6__stack_12r__width_12 (
1161 din0,
1162 sel0,
1163 din1,
1164 sel1,
1165 din2,
1166 sel2,
1167 din3,
1168 sel3,
1169 din4,
1170 sel4,
1171 din5,
1172 sel5,
1173 dout);
1174wire buffout0;
1175wire buffout1;
1176wire buffout2;
1177wire buffout3;
1178wire buffout4;
1179wire buffout5;
1180
1181 input [11:0] din0;
1182 input sel0;
1183 input [11:0] din1;
1184 input sel1;
1185 input [11:0] din2;
1186 input sel2;
1187 input [11:0] din3;
1188 input sel3;
1189 input [11:0] din4;
1190 input sel4;
1191 input [11:0] din5;
1192 input sel5;
1193 output [11:0] dout;
1194
1195
1196
1197
1198
1199cl_dp1_muxbuff6_8x c0_0 (
1200 .in0(sel0),
1201 .in1(sel1),
1202 .in2(sel2),
1203 .in3(sel3),
1204 .in4(sel4),
1205 .in5(sel5),
1206 .out0(buffout0),
1207 .out1(buffout1),
1208 .out2(buffout2),
1209 .out3(buffout3),
1210 .out4(buffout4),
1211 .out5(buffout5)
1212);
1213mux6s #(12) d0_0 (
1214 .sel0(buffout0),
1215 .sel1(buffout1),
1216 .sel2(buffout2),
1217 .sel3(buffout3),
1218 .sel4(buffout4),
1219 .sel5(buffout5),
1220 .in0(din0[11:0]),
1221 .in1(din1[11:0]),
1222 .in2(din2[11:0]),
1223 .in3(din3[11:0]),
1224 .in4(din4[11:0]),
1225 .in5(din5[11:0]),
1226.dout(dout[11:0])
1227);
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241endmodule
1242
1243
1244//
1245// and macro for ports = 2,3,4
1246//
1247//
1248
1249
1250
1251
1252
1253module mcu_lndskw_dp_and_macro__ports_2__width_12 (
1254 din0,
1255 din1,
1256 dout);
1257 input [11:0] din0;
1258 input [11:0] din1;
1259 output [11:0] dout;
1260
1261
1262
1263
1264
1265
1266and2 #(12) d0_0 (
1267.in0(din0[11:0]),
1268.in1(din1[11:0]),
1269.out(dout[11:0])
1270);
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280endmodule
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290// any PARAMS parms go into naming of macro
1291
1292module mcu_lndskw_dp_msff_macro__stack_12r__width_12 (
1293 din,
1294 clk,
1295 en,
1296 se,
1297 scan_in,
1298 siclk,
1299 soclk,
1300 pce_ov,
1301 stop,
1302 dout,
1303 scan_out);
1304wire l1clk;
1305wire siclk_out;
1306wire soclk_out;
1307wire [10:0] so;
1308
1309 input [11:0] din;
1310
1311
1312 input clk;
1313 input en;
1314 input se;
1315 input scan_in;
1316 input siclk;
1317 input soclk;
1318 input pce_ov;
1319 input stop;
1320
1321
1322
1323 output [11:0] dout;
1324
1325
1326 output scan_out;
1327
1328
1329
1330
1331cl_dp1_l1hdr_8x c0_0 (
1332.l2clk(clk),
1333.pce(en),
1334.aclk(siclk),
1335.bclk(soclk),
1336.l1clk(l1clk),
1337 .se(se),
1338 .pce_ov(pce_ov),
1339 .stop(stop),
1340 .siclk_out(siclk_out),
1341 .soclk_out(soclk_out)
1342);
1343dff #(12) d0_0 (
1344.l1clk(l1clk),
1345.siclk(siclk_out),
1346.soclk(soclk_out),
1347.d(din[11:0]),
1348.si({scan_in,so[10:0]}),
1349.so({so[10:0],scan_out}),
1350.q(dout[11:0])
1351);
1352
1353
1354
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365
1366
1367
1368
1369
1370
1371
1372endmodule
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386// any PARAMS parms go into naming of macro
1387
1388module mcu_lndskw_dp_msff_macro__stack_12r__width_6 (
1389 din,
1390 clk,
1391 en,
1392 se,
1393 scan_in,
1394 siclk,
1395 soclk,
1396 pce_ov,
1397 stop,
1398 dout,
1399 scan_out);
1400wire l1clk;
1401wire siclk_out;
1402wire soclk_out;
1403wire [4:0] so;
1404
1405 input [5:0] din;
1406
1407
1408 input clk;
1409 input en;
1410 input se;
1411 input scan_in;
1412 input siclk;
1413 input soclk;
1414 input pce_ov;
1415 input stop;
1416
1417
1418
1419 output [5:0] dout;
1420
1421
1422 output scan_out;
1423
1424
1425
1426
1427cl_dp1_l1hdr_8x c0_0 (
1428.l2clk(clk),
1429.pce(en),
1430.aclk(siclk),
1431.bclk(soclk),
1432.l1clk(l1clk),
1433 .se(se),
1434 .pce_ov(pce_ov),
1435 .stop(stop),
1436 .siclk_out(siclk_out),
1437 .soclk_out(soclk_out)
1438);
1439dff #(6) d0_0 (
1440.l1clk(l1clk),
1441.siclk(siclk_out),
1442.soclk(soclk_out),
1443.d(din[5:0]),
1444.si({scan_in,so[4:0]}),
1445.so({so[4:0],scan_out}),
1446.q(dout[5:0])
1447);
1448
1449
1450
1451
1452
1453
1454
1455
1456
1457
1458
1459
1460
1461
1462
1463
1464
1465
1466
1467
1468endmodule
1469
1470
1471
1472
1473
1474
1475
1476
Full OpenSPARC design & verification tarball including full HDL.