projects / OpenSPARC-T2-DV / blame
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|---|---|---|
| 86530b38 AT |
1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== | |
| 3 | * | |
| 4 | * OpenSPARC T2 Processor File: NcuRegRw.s | |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 7 | * | |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License as published by | |
| 12 | * the Free Software Foundation; version 2 of the License. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 22 | * | |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license | |
| 24 | * choice is available it will apply instead, Sun elects to use only | |
| 25 | * the General Public License version 2 (GPLv2) at this time for any | |
| 26 | * software where a choice of GPL license versions is made | |
| 27 | * available with the language indicating that GPLv2 or any later version | |
| 28 | * may be used, or where a choice of which version of the GPL is applied is | |
| 29 | * otherwise unspecified. | |
| 30 | * | |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or | |
| 33 | * have any questions. | |
| 34 | * | |
| 35 | * | |
| 36 | * ========== Copyright Header End ============================================ | |
| 37 | */ | |
| 38 | #define MAIN_PAGE_HV_ALSO | |
| 39 | ||
| 40 | #include "hboot.s" | |
| 41 | #include "peu_defines.h" | |
| 42 | ||
| 43 | #define ALL_FS 0xffffffffffffffff | |
| 44 | #define IOMMU_INVALIDATE_REG_ADDR 0x0000008000002030 | |
| 45 | ||
| 46 | /************************************************************************ | |
| 47 | Test case code start | |
| 48 | ************************************************************************/ | |
| 49 | .text | |
| 50 | .global main | |
| 51 | main: | |
| 52 | ta T_CHANGE_HPRIV | |
| 53 | nop | |
| 54 | ||
| 55 | setx ALL_FS, %g1, %g5 | |
| 56 | ||
| 57 | setx MEM32_OFFSET_BASE_REG_ADDR, %g1, %g2 ! 0x8000002000 | |
| 58 | setx MEM32_OFFSET_BASE_REG_DATA, %g1, %g3 | |
| 59 | ldx [%g2], %g4 ! read POR value | |
| 60 | ||
| 61 | stx %g5, [%g2] ! store all Fs | |
| 62 | ldx [%g2], %g4 ! read back | |
| 63 | ||
| 64 | stx %g3, [%g2] ! store default value | |
| 65 | ldx [%g2], %g4 ! read back | |
| 66 | ||
| 67 | setx MEM32_OFFSET_MASK_REG_ADDR, %g1, %g2 ! 0x8000002008 | |
| 68 | setx MEM32_OFFSET_MASK_REG_DATA, %g1, %g3 | |
| 69 | ldx [%g2], %g4 ! read POR value | |
| 70 | ||
| 71 | stx %g5, [%g2] ! store all Fs | |
| 72 | ldx [%g2], %g4 ! read back | |
| 73 | ||
| 74 | stx %g3, [%g2] ! store default value | |
| 75 | ldx [%g2], %g4 ! read back | |
| 76 | ||
| 77 | setx MEM64_OFFSET_BASE_REG_ADDR, %g1, %g2 ! 0x8000002010 | |
| 78 | setx MEM64_OFFSET_BASE_REG_DATA, %g1, %g3 | |
| 79 | ldx [%g2], %g4 ! read POR value | |
| 80 | ||
| 81 | stx %g5, [%g2] ! store all Fs | |
| 82 | ldx [%g2], %g4 ! read back | |
| 83 | ||
| 84 | stx %g3, [%g2] ! store default value | |
| 85 | ldx [%g2], %g4 ! read back | |
| 86 | ||
| 87 | setx MEM64_OFFSET_MASK_REG_ADDR, %g1, %g2 ! 0x8000002018 | |
| 88 | setx MEM64_OFFSET_MASK_REG_DATA, %g1, %g3 | |
| 89 | ldx [%g2], %g4 ! read POR value | |
| 90 | ||
| 91 | stx %g5, [%g2] ! store all Fs | |
| 92 | ldx [%g2], %g4 ! read back | |
| 93 | ||
| 94 | stx %g3, [%g2] ! store default value | |
| 95 | ldx [%g2], %g4 ! read back | |
| 96 | ||
| 97 | setx IOCFG_OFFSET_BASE_REG_ADDR, %g1, %g2 ! 0x8000002020 | |
| 98 | setx IOCFG_OFFSET_BASE_REG_DATA, %g1, %g3 | |
| 99 | ldx [%g2], %g4 ! read POR value | |
| 100 | ||
| 101 | stx %g5, [%g2] ! store all Fs | |
| 102 | ldx [%g2], %g4 ! read back | |
| 103 | ||
| 104 | stx %g3, [%g2] ! store default value | |
| 105 | ldx [%g2], %g4 ! read back | |
| 106 | ||
| 107 | setx IOCFG_OFFSET_MASK_REG_ADDR, %g1, %g2 ! 0x8000002028 | |
| 108 | setx IOCFG_OFFSET_MASK_REG_DATA, %g1, %g3 | |
| 109 | ldx [%g2], %g4 ! read POR value | |
| 110 | ||
| 111 | stx %g5, [%g2] ! store all Fs | |
| 112 | ldx [%g2], %g4 ! read back | |
| 113 | ||
| 114 | stx %g3, [%g2] ! store default value | |
| 115 | ldx [%g2], %g4 ! read back | |
| 116 | ||
| 117 | ! not used in PCIe link training, but as long as we're here ... | |
| 118 | ||
| 119 | setx IOMMU_INVALIDATE_REG_ADDR, %g1, %g2 ! 0x8000002030 | |
| 120 | setx 0xa0a0a0a0a0a0a0a0, %g1, %g3 | |
| 121 | ldx [%g2], %g4 ! read POR value | |
| 122 | ||
| 123 | stx %g5, [%g2] ! store all Fs | |
| 124 | ldx [%g2], %g4 ! read back | |
| 125 | ||
| 126 | stx %g3, [%g2] ! store a0a0... | |
| 127 | ldx [%g2], %g4 ! read back | |
| 128 | ||
| 129 | nop | |
| 130 | nop | |
| 131 | ||
| 132 | test_passed: | |
| 133 | EXIT_GOOD | |
| 134 | ||
| 135 | test_failed: | |
| 136 | EXIT_BAD | |
| 137 |