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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tcu.port.vri | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #ifndef INC_TCU_PORT_VRI | |
36 | #define INC_TCU_PORT_VRI | |
37 | ||
38 | #include "tcu_top_defines.vri" | |
39 | ||
40 | // WHAT: clock port | |
41 | port TCU_clk_port { | |
42 | l2clk; | |
43 | iol2clk; | |
44 | gclk; | |
45 | } | |
46 | ||
47 | // now in common | |
48 | // port tap__port { | |
49 | // tck; | |
50 | // trst_n; | |
51 | // test_mode; | |
52 | // tms; | |
53 | // tdi; | |
54 | // tdo; | |
55 | // } | |
56 | ||
57 | port bscan__port { | |
58 | tck; | |
59 | scan_en; | |
60 | clk; | |
61 | aclk; | |
62 | bclk; | |
63 | uclk; | |
64 | } | |
65 | ||
66 | port mbist__port { | |
67 | ||
68 | clk; | |
69 | mbist_user; | |
70 | mbist_start; | |
71 | mbist_done; | |
72 | mbist_fail; | |
73 | mb_scan_en; | |
74 | tcu_aclk; | |
75 | tcu_bclk; | |
76 | tcu_clk_stop; | |
77 | tcu_scan_in; | |
78 | tcu_scan_out; | |
79 | tcu_spc_mbist_start; | |
80 | tcu_mbist_bisi_en; | |
81 | tcu_soc_scan_in; | |
82 | tcu_soc_scan_out; | |
83 | ||
84 | tcu_niu_clk_stop; | |
85 | tcu_peu_io_clk_stop; | |
86 | tcu_dmu_io_clk_stop; | |
87 | tcu_l2t7_clk_stop; | |
88 | tcu_l2t6_clk_stop; | |
89 | tcu_l2t5_clk_stop; | |
90 | tcu_l2t4_clk_stop; | |
91 | tcu_l2t3_clk_stop; | |
92 | tcu_l2t2_clk_stop; | |
93 | tcu_l2t1_clk_stop; | |
94 | tcu_l2t0_clk_stop; | |
95 | tcu_l2b7_clk_stop; | |
96 | tcu_l2b6_clk_stop; | |
97 | tcu_l2b5_clk_stop; | |
98 | tcu_l2b4_clk_stop; | |
99 | tcu_l2b3_clk_stop; | |
100 | tcu_l2b2_clk_stop; | |
101 | tcu_l2b1_clk_stop; | |
102 | tcu_l2b0_clk_stop; | |
103 | tcu_mcu3_clk_stop; | |
104 | tcu_mcu2_clk_stop; | |
105 | tcu_mcu1_clk_stop; | |
106 | tcu_mcu0_clk_stop; | |
107 | tcu_soc_clk_stop; | |
108 | ||
109 | tcu_soc_aclk; | |
110 | tcu_soc_bclk; | |
111 | tcu_soc_scan_en; | |
112 | ||
113 | tcu_peu_pc_clk_stop; | |
114 | tcu_mcu0_dr_clk_stop; | |
115 | tcu_mcu0_io_clk_stop; | |
116 | tcu_mcu0_fbd_clk_stop; | |
117 | tcu_mcu1_dr_clk_stop; | |
118 | tcu_mcu1_io_clk_stop; | |
119 | tcu_mcu1_fbd_clk_stop; | |
120 | tcu_mcu2_dr_clk_stop; | |
121 | tcu_mcu2_io_clk_stop; | |
122 | tcu_mcu2_fbd_clk_stop; | |
123 | tcu_mcu3_dr_clk_stop; | |
124 | tcu_mcu3_io_clk_stop; | |
125 | tcu_mcu3_fbd_clk_stop; | |
126 | tcu_ncu_io_clk_stop; | |
127 | tcu_sio_io_clk_stop; | |
128 | tcu_sii_io_clk_stop; | |
129 | tcu_mio_mbist_fail; | |
130 | tcu_mio_mbist_done; | |
131 | pin_mbist_fail; | |
132 | pin_mbist_done; | |
133 | #ifdef FC_SCAN_BENCH | |
134 | mbist_l2tag_read_l2t0; | |
135 | #endif //FC_SCAN_BENCH | |
136 | bisx_counter; | |
137 | } | |
138 | ||
139 | port lbist__port { | |
140 | clk; | |
141 | lbist_start; | |
142 | lbist_scan_in; | |
143 | lbist_pgm; | |
144 | test_mode; | |
145 | lbist_done; | |
146 | lbist_scan_out; | |
147 | } | |
148 | ||
149 | port scan__port { | |
150 | tck; | |
151 | ac_test_mode; | |
152 | //srdes_scancfg; | |
153 | //tcu_srdes_scancfg; | |
154 | //tcu_pllbypass; | |
155 | scan_en; | |
156 | tcu_scan_en; | |
157 | tcu_se_scancollar_in; | |
158 | tcu_se_scancollar_out; | |
159 | tcu_array_wr_inhibit; | |
160 | tcu_array_bypass; | |
161 | tcu_dectest; | |
162 | tcu_muxtest; | |
163 | tcu_aclk; | |
164 | tcu_bclk; | |
165 | pscan_si; // PIN interface | |
166 | pscan_so; // PIN interface | |
167 | jtag_si; // TCU mux port | |
168 | jtag_so; // TCU mux port | |
169 | } | |
170 | ||
171 | port efuse__port { | |
172 | tck; | |
173 | efuse_rowaddr; | |
174 | efuse_coladdr; | |
175 | efuse_read_en; | |
176 | efuse_read_mode; | |
177 | efuse_read_start; | |
178 | efuse_fuse_bypass; | |
179 | efuse_dest_sample; | |
180 | efuse_updatedr; | |
181 | efuse_shiftdr; | |
182 | efuse_capturedr; | |
183 | efuse_sbc_efa_bit_addr; | |
184 | efuse_sbc_efa_word_addr; | |
185 | efuse_sbc_efa_margin0_rd; | |
186 | efuse_sbc_efa_margin1_rd; | |
187 | efuse_sbc_efa_power_down; | |
188 | efuse_pwr_ok; | |
189 | efuse_por_l; | |
190 | efuse_pi_efa_prog_en; | |
191 | efuse_vpp; | |
192 | efuse_sbc_efa_read_en; | |
193 | efuse_efa_read_data; | |
194 | efuse_efa_out_data; | |
195 | efuse_read_data_ff; | |
196 | efuse_tck_shft_data_ff; | |
197 | efuse_io_vpp; | |
198 | efuse_io_pgrm_en; | |
199 | efu_ncu_bankavl_xfer_en; | |
200 | efu_ncu_coreavl_xfer_en; | |
201 | efu_l2b1_fuse_xfer_en; | |
202 | efu_l2t1_fuse_xfer_en; | |
203 | efu_ncu_srlnum1_xfer_en; | |
204 | efu_niu_4k_xfer_en; | |
205 | efu_spc1_fuse_dxfer_en; | |
206 | efu_spc1_fuse_ixfer_en; | |
207 | efu_dmu_xfer_en; | |
208 | efuse_por_n; | |
209 | efuse_efuse_row; | |
210 | efuse_xfer_en; | |
211 | efu_rv_clr; | |
212 | VPP; | |
213 | PGRM_EN; | |
214 | coreavail; | |
215 | bankavail; | |
216 | sernum0; | |
217 | sernum1; | |
218 | sernum2; | |
219 | fusestat; | |
220 | efcnt_dout; | |
221 | efu_done_int; | |
222 | dest_efu_xfer_en; | |
223 | } | |
224 | ||
225 | // #ifndef FC_SCAN_BENCH | |
226 | port cmp__port { | |
227 | clk; | |
228 | core_available_array; | |
229 | core_enable_status_array; | |
230 | core_running_array; | |
231 | core_running_status_array; | |
232 | tb_fusedata_init; | |
233 | } | |
234 | ||
235 | port spc_debug__port { | |
236 | clk; | |
237 | tcu_ss_mode; | |
238 | tcu_do_mode; | |
239 | tcu_ss_request; | |
240 | ss_complete; | |
241 | core_running; | |
242 | core_running_status; | |
243 | } | |
244 | ||
245 | port ncu_sck__port { | |
246 | sck_cnt; | |
247 | } | |
248 | ||
249 | port tcu_siu__port { | |
250 | clk; | |
251 | tcu_sii_data; | |
252 | tcu_sii_vld; | |
253 | sio_tcu_data; | |
254 | sio_tcu_vld; | |
255 | sio_tcu_data__in; // __in: input to vera | |
256 | sio_tcu_vld__in; // __in: input to vera | |
257 | } | |
258 | // #endif //FC_SCAN_BENCH | |
259 | ||
260 | port jt_scan_clk__port { | |
261 | jt_scan_aclk; | |
262 | jt_scan_bclk; | |
263 | io_test_mode; | |
264 | mtaccess; | |
265 | #ifndef TCU_GATE | |
266 | instr_ser_scan; | |
267 | #endif | |
268 | jt_scan_en; | |
269 | tcu_asic_array_wr_inhibit; | |
270 | tcu_spc0_array_wr_inhibit; | |
271 | tcu_spc1_array_wr_inhibit; | |
272 | tcu_spc2_array_wr_inhibit; | |
273 | tcu_spc3_array_wr_inhibit; | |
274 | tcu_spc4_array_wr_inhibit; | |
275 | tcu_spc5_array_wr_inhibit; | |
276 | tcu_spc6_array_wr_inhibit; | |
277 | tcu_spc7_array_wr_inhibit; | |
278 | } | |
279 | ||
280 | port shscan__port { | |
281 | tck; | |
282 | shscan_spc_aclk; | |
283 | shscan_spc_bclk; | |
284 | shscan_spc_se; | |
285 | shscan_spc_pce_ov; | |
286 | shscan_spc_clk_stop; | |
287 | shscan_spc_shscanid; | |
288 | shscan_l2t_aclk; | |
289 | shscan_l2t_bclk; | |
290 | shscan_l2t_se; | |
291 | shscan_l2t_pce_ov; | |
292 | shscan_l2t_clk_stop; | |
293 | spc_tcu_shscan_scan_in; | |
294 | tcu_spc_shscan_scan_out; | |
295 | } | |
296 | ||
297 | // WHAT: tcu-rst interface signals and reseting-related signals | |
298 | ||
299 | port TCU_rst_port { | |
300 | l2clk; | |
301 | PWRON_RST_L; | |
302 | tcu_por_reset; | |
303 | rst_tcu_asicflush_stop_req; | |
304 | tcu_rst_asicflush_stop_ack; | |
305 | rst_tcu_flush_init_req; | |
306 | tcu_rst_flush_init_ack; | |
307 | rst_tcu_flush_stop_req; | |
308 | tcu_rst_flush_stop_ack; | |
309 | tcu_efu_read_start; | |
310 | tcu_rst_efu_done; | |
311 | rst_ncu_unpark_thread; | |
312 | } | |
313 | ||
314 | // WHAT: core/bank available/enable | |
315 | ||
316 | port TCU_corebank_port { | |
317 | l2clk; | |
318 | core_available; | |
319 | core_enable; | |
320 | bank_available; | |
321 | bank_enable; | |
322 | } | |
323 | ||
324 | // WHAT: port for tcu_*_clk_stop signals | |
325 | ||
326 | port TCU_clkstop_port { | |
327 | clk; | |
328 | spc_clkstop; | |
329 | spc_shscan_clkstop; | |
330 | l2b_clkstop; | |
331 | l2d_clkstop; | |
332 | l2t_clkstop; | |
333 | l2t_shscan_clkstop; | |
334 | mcu_clkstop; | |
335 | mcu_dr_clkstop; | |
336 | mcu_io_clkstop; | |
337 | mcu_fbd_clkstop; | |
338 | soc0_clkstop; // SOC0: ccx, efu, ncu, sii, sio | |
339 | soc0_io_clkstop; // SOC0: db0, db1, efu, mio, ncu, sii, sio | |
340 | soc1_io_clkstop; // SOC1: mac, rdp, rtx, tds | |
341 | soc2_io_clkstop; // SOC2: dmu_io | |
342 | soc3_io_clkstop; // SOC3: peu_io | |
343 | soc3_clkstop; // SOC3: peu_pc | |
344 | ccu_clkstop; // special case: ccu | |
345 | ccu_io_clkstop; // special case: ccu | |
346 | rst_clkstop; // special case: rst | |
347 | rst_io_clkstop; // special case: rst | |
348 | //--- all TCU's tcu_*_clk_stop signals --- | |
349 | all_clk_stop_sigs; | |
350 | } | |
351 | ||
352 | // WHAT: debug event signals from core and SOC to TCU | |
353 | ||
354 | port TCU_dbg_event_port { | |
355 | l2clk; | |
356 | hardstop_request; | |
357 | softstop_request; | |
358 | trigger_pulse; | |
359 | soc_hard_stop; | |
360 | soc_trigout; | |
361 | ||
362 | tcu_mio_trigout; | |
363 | mio_tcu_trigin; | |
364 | } | |
365 | ||
366 | port stci__port { | |
367 | tck; | |
368 | tcu_stciclk; | |
369 | tcu_stcicfg; | |
370 | tcu_stcid; | |
371 | STCIQ; | |
372 | io_tdi; | |
373 | stciq_tcu; | |
374 | update_dr_state; | |
375 | capture_dr_state; | |
376 | shift_dr_state; | |
377 | #ifndef TCU_GATE | |
378 | clockdr; | |
379 | #endif | |
380 | STCICLK; | |
381 | STCICFG; | |
382 | STCID; | |
383 | stci_acc_mode; | |
384 | tap_state; | |
385 | signal_to_disable_checker; | |
386 | } | |
387 | ||
388 | #endif |