verif/env/tcu/vera/include/tcu.port.vri

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: tcu.port.vri
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
// may be used, or where a choice of which version of the GPL is applied is
// otherwise unspecified.
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// CA 95054 USA or visit www.sun.com if you need additional information or
// have any questions.
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// ========== Copyright Header End ============================================
#ifndef INC_TCU_PORT_VRI
#define INC_TCU_PORT_VRI

#include "tcu_top_defines.vri"

// WHAT: clock port
port TCU_clk_port {
  l2clk;
  iol2clk;
  gclk;
}

// now in common
// port tap__port {
//   tck;
//   trst_n;
//   test_mode;
//   tms;
//   tdi;
//   tdo;
// }

port bscan__port {
  tck;
  scan_en;
  clk;
  aclk;
  bclk;
  uclk;
}

port mbist__port {

  clk;
  mbist_user;
  mbist_start;
  mbist_done;
  mbist_fail;
  mb_scan_en;
  tcu_aclk;
  tcu_bclk;
  tcu_clk_stop;
  tcu_scan_in;
  tcu_scan_out;
  tcu_spc_mbist_start;
  tcu_mbist_bisi_en;
  tcu_soc_scan_in;
  tcu_soc_scan_out;

  tcu_niu_clk_stop;
  tcu_peu_io_clk_stop;
  tcu_dmu_io_clk_stop;
  tcu_l2t7_clk_stop;
  tcu_l2t6_clk_stop;
  tcu_l2t5_clk_stop;
  tcu_l2t4_clk_stop;
  tcu_l2t3_clk_stop;
  tcu_l2t2_clk_stop;
  tcu_l2t1_clk_stop;
  tcu_l2t0_clk_stop;
  tcu_l2b7_clk_stop;
  tcu_l2b6_clk_stop;
  tcu_l2b5_clk_stop;
  tcu_l2b4_clk_stop;
  tcu_l2b3_clk_stop;
  tcu_l2b2_clk_stop;
  tcu_l2b1_clk_stop;
  tcu_l2b0_clk_stop;
  tcu_mcu3_clk_stop;
  tcu_mcu2_clk_stop;
  tcu_mcu1_clk_stop;
  tcu_mcu0_clk_stop;
  tcu_soc_clk_stop;

  tcu_soc_aclk;
  tcu_soc_bclk;
  tcu_soc_scan_en;

  tcu_peu_pc_clk_stop;
  tcu_mcu0_dr_clk_stop;
  tcu_mcu0_io_clk_stop;
  tcu_mcu0_fbd_clk_stop;
  tcu_mcu1_dr_clk_stop;
  tcu_mcu1_io_clk_stop;
  tcu_mcu1_fbd_clk_stop;
  tcu_mcu2_dr_clk_stop;
  tcu_mcu2_io_clk_stop;
  tcu_mcu2_fbd_clk_stop;
  tcu_mcu3_dr_clk_stop;
  tcu_mcu3_io_clk_stop;
  tcu_mcu3_fbd_clk_stop;
  tcu_ncu_io_clk_stop;
  tcu_sio_io_clk_stop;
  tcu_sii_io_clk_stop;
  tcu_mio_mbist_fail;
  tcu_mio_mbist_done;
  pin_mbist_fail;
  pin_mbist_done;
#ifdef FC_SCAN_BENCH
  mbist_l2tag_read_l2t0;
#endif //FC_SCAN_BENCH
  bisx_counter;
}

port lbist__port {
  clk;
  lbist_start;
  lbist_scan_in;
  lbist_pgm;
  test_mode;
  lbist_done;
  lbist_scan_out;
}

port scan__port {
  tck;
  ac_test_mode;
  //srdes_scancfg;
  //tcu_srdes_scancfg;
  //tcu_pllbypass;
  scan_en;
  tcu_scan_en;
  tcu_se_scancollar_in;
  tcu_se_scancollar_out;
  tcu_array_wr_inhibit;
  tcu_array_bypass;
  tcu_dectest;
  tcu_muxtest;
  tcu_aclk;
  tcu_bclk;
  pscan_si; // PIN interface
  pscan_so; // PIN interface
  jtag_si;  // TCU mux port
  jtag_so;  // TCU mux port
}

port efuse__port {
  tck;
  efuse_rowaddr;
  efuse_coladdr;
  efuse_read_en;
  efuse_read_mode;
  efuse_read_start;
  efuse_fuse_bypass;
  efuse_dest_sample;
  efuse_updatedr;
  efuse_shiftdr;
  efuse_capturedr;
  efuse_sbc_efa_bit_addr;
  efuse_sbc_efa_word_addr;
  efuse_sbc_efa_margin0_rd;
  efuse_sbc_efa_margin1_rd;
  efuse_sbc_efa_power_down;
  efuse_pwr_ok;
  efuse_por_l;
  efuse_pi_efa_prog_en;
  efuse_vpp;
  efuse_sbc_efa_read_en;
  efuse_efa_read_data;
  efuse_efa_out_data;
  efuse_read_data_ff;
  efuse_tck_shft_data_ff;
  efuse_io_vpp;
  efuse_io_pgrm_en;
  efu_ncu_bankavl_xfer_en;
  efu_ncu_coreavl_xfer_en;
  efu_l2b1_fuse_xfer_en;
  efu_l2t1_fuse_xfer_en;
  efu_ncu_srlnum1_xfer_en;
  efu_niu_4k_xfer_en;
  efu_spc1_fuse_dxfer_en;
  efu_spc1_fuse_ixfer_en;
  efu_dmu_xfer_en;
  efuse_por_n;
  efuse_efuse_row;
  efuse_xfer_en;
  efu_rv_clr;
  VPP;
  PGRM_EN;
  coreavail;
  bankavail;
  sernum0;
  sernum1;
  sernum2;
  fusestat;
  efcnt_dout;
  efu_done_int;
  dest_efu_xfer_en;
 }

// #ifndef FC_SCAN_BENCH
port cmp__port {
  clk;
  core_available_array;
  core_enable_status_array;
  core_running_array;
  core_running_status_array;
  tb_fusedata_init;
}

port spc_debug__port {
  clk;
  tcu_ss_mode;
  tcu_do_mode;
  tcu_ss_request;
  ss_complete;
  core_running;
  core_running_status;
}

port ncu_sck__port {
  sck_cnt;
}

port tcu_siu__port {
  clk;
  tcu_sii_data;
  tcu_sii_vld;
  sio_tcu_data;
  sio_tcu_vld;
  sio_tcu_data__in; // __in: input to vera
  sio_tcu_vld__in;  // __in: input to vera
}
// #endif //FC_SCAN_BENCH

port jt_scan_clk__port {
   jt_scan_aclk;
   jt_scan_bclk;
   io_test_mode;
   mtaccess;
#ifndef TCU_GATE
   instr_ser_scan;
#endif
   jt_scan_en;
   tcu_asic_array_wr_inhibit;
   tcu_spc0_array_wr_inhibit;
   tcu_spc1_array_wr_inhibit;
   tcu_spc2_array_wr_inhibit;
   tcu_spc3_array_wr_inhibit;
   tcu_spc4_array_wr_inhibit;
   tcu_spc5_array_wr_inhibit;
   tcu_spc6_array_wr_inhibit;
   tcu_spc7_array_wr_inhibit;
}

port shscan__port {
  tck;
  shscan_spc_aclk;
  shscan_spc_bclk;
  shscan_spc_se;
  shscan_spc_pce_ov;
  shscan_spc_clk_stop;
  shscan_spc_shscanid;
  shscan_l2t_aclk;
  shscan_l2t_bclk;
  shscan_l2t_se;
  shscan_l2t_pce_ov;
  shscan_l2t_clk_stop;
  spc_tcu_shscan_scan_in;
  tcu_spc_shscan_scan_out;
}

// WHAT: tcu-rst interface signals and reseting-related signals

port TCU_rst_port {
   l2clk;
   PWRON_RST_L;
   tcu_por_reset;
   rst_tcu_asicflush_stop_req;
   tcu_rst_asicflush_stop_ack;
   rst_tcu_flush_init_req;
   tcu_rst_flush_init_ack;
   rst_tcu_flush_stop_req;
   tcu_rst_flush_stop_ack;
   tcu_efu_read_start;
   tcu_rst_efu_done;
   rst_ncu_unpark_thread;
}

// WHAT: core/bank available/enable

port TCU_corebank_port {
  l2clk;
  core_available;
  core_enable;
  bank_available;
  bank_enable;
}

// WHAT: port for tcu_*_clk_stop signals

port TCU_clkstop_port {
  clk;
  spc_clkstop;
  spc_shscan_clkstop;
  l2b_clkstop;
  l2d_clkstop;
  l2t_clkstop;
  l2t_shscan_clkstop;
  mcu_clkstop;
  mcu_dr_clkstop;
  mcu_io_clkstop;
  mcu_fbd_clkstop;
  soc0_clkstop;     // SOC0: ccx, efu, ncu, sii, sio
  soc0_io_clkstop;  // SOC0: db0, db1, efu, mio, ncu, sii, sio
  soc1_io_clkstop;  // SOC1: mac, rdp, rtx, tds
  soc2_io_clkstop;  // SOC2: dmu_io
  soc3_io_clkstop;  // SOC3: peu_io
  soc3_clkstop;     // SOC3: peu_pc
  ccu_clkstop;      // special case: ccu
  ccu_io_clkstop;   // special case: ccu
  rst_clkstop;      // special case: rst
  rst_io_clkstop;   // special case: rst
  //--- all TCU's tcu_*_clk_stop signals ---
  all_clk_stop_sigs;
}

// WHAT: debug event signals from core and SOC to TCU

port TCU_dbg_event_port {
  l2clk;
  hardstop_request;
  softstop_request;
  trigger_pulse;
  soc_hard_stop;
  soc_trigout;

  tcu_mio_trigout;
  mio_tcu_trigin;
}

port stci__port {
  tck;
  tcu_stciclk;
  tcu_stcicfg;
  tcu_stcid;
  STCIQ;
  io_tdi;
  stciq_tcu;
  update_dr_state;
  capture_dr_state;
  shift_dr_state;
#ifndef TCU_GATE
  clockdr;
#endif
  STCICLK;
  STCICFG;
  STCID;
  stci_acc_mode;
  tap_state;
  signal_to_disable_checker;
}

#endif