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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: siumon.if.vrhpal | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | #inc "siu_inc.pal" | |
36 | ||
37 | #ifndef INC_SIUMON_IF_VRH | |
38 | #define INC_SIUMON_IF_VRH | |
39 | ||
40 | #include "top_defines.vrh" | |
41 | ||
42 | interface ncu_mon { | |
43 | input iol2clk CLOCK verilog_node "`SII.iol2clk"; | |
44 | input syn_vld INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_syn_vld"; | |
45 | input [3:0] syn_data INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_syn_data"; | |
46 | input niu_a_pei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_niua_pei"; | |
47 | input niu_a_pe INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_niua_pe"; | |
48 | input niu_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_niud_pei"; | |
49 | input niu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_niud_pe"; | |
50 | input niu_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_niuctag_uei"; | |
51 | input niu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_niuctag_ue"; | |
52 | input niu_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_niuctag_cei"; | |
53 | input niu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_niuctag_ce"; | |
54 | input dmu_a_pei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_dmua_pei"; | |
55 | input dmu_a_pe INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_dmua_pe"; | |
56 | input dmu_d_pei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_dmud_pei"; | |
57 | input dmu_d_pe INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_dmud_pe"; | |
58 | input dmu_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_dmuctag_uei"; | |
59 | input dmu_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_dmuctag_ue"; | |
60 | input dmu_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`SII.ncu_sii_dmuctag_cei"; | |
61 | input dmu_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_ncu_dmuctag_ce"; | |
62 | input sio_ctag_uei INPUT_EDGE INPUT_SKEW verilog_node "`SIO.ncu_sio_ctag_uei"; | |
63 | input sio_ctag_ue INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_ncu_ctag_ue"; | |
64 | input sio_ctag_cei INPUT_EDGE INPUT_SKEW verilog_node "`SIO.ncu_sio_ctag_cei"; | |
65 | input sio_ctag_ce INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_ncu_ctag_ce"; | |
66 | } | |
67 | ||
68 | interface cmd_mon { | |
69 | input l2clk CLOCK verilog_node "`SII.l2clk"; | |
70 | #ifdef GATESIM | |
71 | input cmd_parity_err INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc__n2852"; | |
72 | input cur_source INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc__n2857"; | |
73 | #else | |
74 | input cmd_parity_err INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.cmd_parity_err"; | |
75 | input cur_source INPUT_EDGE INPUT_SKEW verilog_node "`SII.ipcc.cur_source"; | |
76 | #endif | |
77 | } | |
78 | ||
79 | interface niu_mon { | |
80 | input clk CLOCK verilog_node "`SII.iol2clk"; | |
81 | input sreq INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_hdr_vld"; | |
82 | input bypass INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_reqbypass"; | |
83 | input sdatareq INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_datareq"; | |
84 | input [127:0] sdata INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_data"; | |
85 | input [1:0] sparity INPUT_EDGE INPUT_SKEW verilog_node "`SII.niu_sii_parity"; | |
86 | input oqdq INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_niu_oqdq"; | |
87 | input bqdq INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_niu_bqdq"; | |
88 | input rreq INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_niu_hdr_vld"; | |
89 | input rdatareq INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_niu_datareq"; | |
90 | input [127:0] rdata INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_niu_data"; | |
91 | input [1:0] rparity INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_niu_parity"; | |
92 | input niu_dq INPUT_EDGE INPUT_SKEW verilog_node "`SIO.niu_sio_dq"; | |
93 | } | |
94 | ||
95 | interface dmu_mon { | |
96 | input clk CLOCK verilog_node "`SII.iol2clk"; | |
97 | input sreq INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_hdr_vld"; | |
98 | input bypass INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_reqbypass"; | |
99 | input sdatareq INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_datareq"; | |
100 | input datareq16 INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_datareq16"; | |
101 | input [127:0] sdata INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_data"; | |
102 | input [1:0] sparity INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_parity"; | |
103 | input [15:0] be INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_be"; | |
104 | input beparity INPUT_EDGE INPUT_SKEW verilog_node "`SII.dmu_sii_be_parity"; | |
105 | input wrack_vld INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_dmu_wrack_vld"; | |
106 | input [3:0] wrack_tag INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_dmu_wrack_tag"; | |
107 | input rreq INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_dmu_hdr_vld"; | |
108 | //input rdatareq INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_dmu_datareq"; | |
109 | input [127:0] rdata INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_dmu_data"; | |
110 | input [1:0] rparity INPUT_EDGE INPUT_SKEW verilog_node "`SIO.sio_dmu_parity"; | |
111 | } | |
112 | ||
113 | .for($b=0; $b<$BANKS; $b++) { | |
114 | interface l2_${b}_mon { | |
115 | input clk CLOCK verilog_node "`SII.l2clk"; | |
116 | input req_vld INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2t${b}_req_vld"; | |
117 | input [31:0] req INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2t${b}_req"; | |
118 | input [6:0] ecc INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_l2b${b}_ecc"; | |
119 | input ctag_vld INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_ctag_vld"; | |
120 | input [31:0] data INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_data"; | |
121 | input [1:0] parity INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_parity"; | |
122 | input ue_err INPUT_EDGE INPUT_SKEW verilog_node "`SIO.l2b${b}_sio_ue_err"; | |
123 | input iq_dequeue INPUT_EDGE INPUT_SKEW verilog_node "`SII.l2t${b}_sii_iq_dequeue"; | |
124 | input wib_dequeue INPUT_EDGE INPUT_SKEW verilog_node "`SII.l2t${b}_sii_wib_dequeue"; | |
125 | input [1:0] dbg_req INPUT_EDGE INPUT_SKEW verilog_node "`SII.sii_dbg1_l2t${b}_req"; | |
126 | } | |
127 | ||
128 | .} | |
129 | ||
130 | #endif |