| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_cmu_ctx_clstreg_array.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_cmu_ctx_clstreg_array ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | addr, |
| 39 | data_in, |
| 40 | rw, |
| 41 | data_out |
| 42 | ); |
| 43 | |
| 44 | //************************************************ |
| 45 | // PARAMETERS |
| 46 | //************************************************ |
| 47 | |
| 48 | parameter WIDTH = 8, |
| 49 | DEPTH = 8, |
| 50 | ADDR_WDTH = 3; |
| 51 | |
| 52 | //************************************************ |
| 53 | // PORTS |
| 54 | //************************************************ |
| 55 | |
| 56 | input clk; // input clock |
| 57 | input rst_l; // synopsys sync_set_reset "rst_l" |
| 58 | |
| 59 | input [ADDR_WDTH -1 :0] addr; |
| 60 | input [WIDTH -1 :0] data_in; // input data |
| 61 | input rw; // syncronous write strobe |
| 62 | output [WIDTH - 1:0] data_out; // output data |
| 63 | |
| 64 | |
| 65 | // Flop Array |
| 66 | |
| 67 | reg [WIDTH -1 :0] reg_array[0 :DEPTH -1]; // The fifo storge arrary |
| 68 | |
| 69 | integer i; |
| 70 | |
| 71 | |
| 72 | //************************************************ |
| 73 | // SIGNALS |
| 74 | //************************************************ |
| 75 | |
| 76 | |
| 77 | //************************************************ |
| 78 | // Zero In checkers |
| 79 | //************************************************ |
| 80 | |
| 81 | // *************** Procedures *************************************/ |
| 82 | // Write access, put the data on the input bus into |
| 83 | // the location referenced by the write pointer. |
| 84 | // Write contention is guaranteed not to happen |
| 85 | // because accessing agents never access same address |
| 86 | |
| 87 | always @(posedge clk) begin |
| 88 | if(~rst_l) begin : reg_reset |
| 89 | integer j; |
| 90 | for(j=0; j < DEPTH; j=j+1) |
| 91 | begin |
| 92 | reg_array[j] <= {WIDTH{1'b0}}; |
| 93 | end |
| 94 | end |
| 95 | else begin |
| 96 | if (rw) begin //rw = 1 to write |
| 97 | reg_array[addr] <= data_in; |
| 98 | end |
| 99 | else begin |
| 100 | for(i=0; i < DEPTH; i=i+1) |
| 101 | reg_array[i] <= reg_array[i]; |
| 102 | end |
| 103 | end |
| 104 | end // always @ (posedge clk) |
| 105 | |
| 106 | // ***********************Assignments *****************************/ |
| 107 | |
| 108 | |
| 109 | //*********************************************** |
| 110 | // A read returns data referenced by the read pointer |
| 111 | //************************************************ |
| 112 | |
| 113 | assign data_out = reg_array[addr]; |
| 114 | |
| 115 | endmodule // dmu_cmu_ctx_clstreg_array |
| 116 | |
| 117 | |
| 118 | |