| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_ilu_iil_xfrfsm.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_ilu_iil_xfrfsm ( |
| 36 | clk, |
| 37 | rst_l, |
| 38 | |
| 39 | p2d_cto_req, |
| 40 | p2d_cto_tag, |
| 41 | d2p_cto_ack, |
| 42 | n_cto_req_reg, |
| 43 | |
| 44 | cib2iil_ihb_pe_drain, // caused by iil2cib_ihb_pe |
| 45 | cib2iil_pec_drain, // caused by p2d_drain |
| 46 | // cib2iil_drain, |
| 47 | iil2cib_ihb_pe, |
| 48 | |
| 49 | y2k_rcd_enq, |
| 50 | k2y_rcd_deq, |
| 51 | |
| 52 | ihb_rcd_is_cpl, |
| 53 | |
| 54 | iil2isb_clr, |
| 55 | isb2iil_vld, |
| 56 | |
| 57 | is_ihb_rcd, |
| 58 | is_cto_rcd, |
| 59 | pio_tag_gen, |
| 60 | |
| 61 | ihb_empty, |
| 62 | ihb_rptr_inc, |
| 63 | |
| 64 | // idle check |
| 65 | iil_is_idle, |
| 66 | |
| 67 | // debug |
| 68 | state, |
| 69 | is_fifo_space, |
| 70 | drop_inserted_rcd ); |
| 71 | |
| 72 | //synopsys sync_set_reset "rst_l" |
| 73 | |
| 74 | // >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 75 | |
| 76 | // states |
| 77 | parameter // summit enum xfr_enum |
| 78 | IDLE = 0, |
| 79 | IHB = 1, |
| 80 | CTO_WAIT = 2, |
| 81 | CTO_SERV = 3, |
| 82 | DRAIN = 4; |
| 83 | |
| 84 | // num of states |
| 85 | parameter STATE_NUM = 5; |
| 86 | |
| 87 | // >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 88 | |
| 89 | //--------------------------------------------------------------------- |
| 90 | // Clock and Reset Signals |
| 91 | //--------------------------------------------------------------------- |
| 92 | input clk; // input clock |
| 93 | input rst_l; // input reset |
| 94 | |
| 95 | |
| 96 | //--------------------------------------------------------------------- |
| 97 | // cto interface - PIO completion time out |
| 98 | //--------------------------------------------------------------------- |
| 99 | input p2d_cto_req; // cto request from TLU |
| 100 | input [4:0] p2d_cto_tag; |
| 101 | output d2p_cto_ack; // cto ack back |
| 102 | output n_cto_req_reg; // p2d_cto_req synchronized to iol2clk for dbg |
| 103 | |
| 104 | //--------------------------------------------------------------------- |
| 105 | // drain interface |
| 106 | //--------------------------------------------------------------------- |
| 107 | // input cib2iil_drain; // drain signal |
| 108 | input cib2iil_ihb_pe_drain; // caused by iil2cib_ihb_pe |
| 109 | input cib2iil_pec_drain; // caused by p2d_drain |
| 110 | |
| 111 | |
| 112 | //--------------------------------------------------------------------- |
| 113 | // record interface to TMU |
| 114 | //--------------------------------------------------------------------- |
| 115 | input k2y_rcd_deq; // record fifo dequeue |
| 116 | output y2k_rcd_enq; // ingress PEC record enqueue |
| 117 | |
| 118 | //--------------------------------------------------------------------- |
| 119 | // sub-block to sub-block interface |
| 120 | //--------------------------------------------------------------------- |
| 121 | output iil2isb_clr; |
| 122 | input isb2iil_vld; |
| 123 | |
| 124 | input iil2cib_ihb_pe; // ingress header parity error, from *_parchk.v |
| 125 | |
| 126 | //--------------------------------------------------------------------- |
| 127 | // IHB rcd status |
| 128 | //--------------------------------------------------------------------- |
| 129 | input ihb_rcd_is_cpl; // to determine iil2isb_clr, from *_rcdbldr.v |
| 130 | |
| 131 | //--------------------------------------------------------------------- |
| 132 | // IHB management |
| 133 | //--------------------------------------------------------------------- |
| 134 | input ihb_empty; // from *_bufmgr.v |
| 135 | output ihb_rptr_inc; // advance ihb rptr, to *_bufmgr.v |
| 136 | |
| 137 | //--------------------------------------------------------------------- |
| 138 | // states releated info |
| 139 | //--------------------------------------------------------------------- |
| 140 | output is_ihb_rcd; // in-process rcd is ihb rcd, to *_rcdbldr.v & *_crdtcnt.v |
| 141 | output is_cto_rcd; // in-process rcd is CTO rcd, to *_rcdbldr.v |
| 142 | output [4:0] pio_tag_gen; // pio_tag to gen cpl header, to *_rcdbldr.v |
| 143 | |
| 144 | //--------------------------------------------------------------------- |
| 145 | // debug signals |
| 146 | //--------------------------------------------------------------------- |
| 147 | output [STATE_NUM-1:0] state; |
| 148 | output is_fifo_space; |
| 149 | output drop_inserted_rcd; |
| 150 | |
| 151 | //--------------------------------------------------------------------- |
| 152 | // idle check |
| 153 | //--------------------------------------------------------------------- |
| 154 | output iil_is_idle; |
| 155 | |
| 156 | // >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<< |
| 157 | |
| 158 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 159 | reg cto_req_reg; |
| 160 | reg d2p_cto_ack; |
| 161 | |
| 162 | reg [STATE_NUM-1:0] state; |
| 163 | |
| 164 | reg [4:0] pio_tag_drain; // loop through in drain state |
| 165 | |
| 166 | reg [2:0] fifo_credit; // TMU rcd fifo credit |
| 167 | |
| 168 | reg is_ihb_rcd_ps2; |
| 169 | reg is_cto_rcd_ps2; |
| 170 | reg is_drain_rcd_ps2; |
| 171 | |
| 172 | reg [4:0] pio_tag_ps1; |
| 173 | reg [4:0] pio_tag_ps2; |
| 174 | |
| 175 | reg y2k_rcd_enq; |
| 176 | |
| 177 | reg ihb_ihb_pe_detected; |
| 178 | |
| 179 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~ |
| 180 | reg [STATE_NUM-1:0] n_state; |
| 181 | |
| 182 | reg [2:0] n_fifo_credit; // TMU rcd next fifo credit value |
| 183 | |
| 184 | // ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 185 | wire n_cto_req_reg; |
| 186 | wire cto_req; |
| 187 | wire n_cto_ack; |
| 188 | |
| 189 | wire n_y2k_rcd_enq; |
| 190 | |
| 191 | wire [4:0] pio_tag_ne0; // muxed out from pio_tag_drain and p2d_cto_tag |
| 192 | |
| 193 | wire is_ihb_rcd_ps1; |
| 194 | wire is_cto_rcd_ps1; |
| 195 | wire is_drain_rcd_ps1; |
| 196 | |
| 197 | wire crdt_back; // fifo credit when rcd need be dropped |
| 198 | wire cnsm_crdt; // consume fifo credit when inject rcd in pipeline |
| 199 | |
| 200 | // >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 201 | |
| 202 | // 0in one_hot -var state |
| 203 | // 0in max -var fifo_credit -val 6 |
| 204 | |
| 205 | // 0in known_driven -var cib2iil_ihb_pe_drain |
| 206 | |
| 207 | // 0in known_driven -var cib2iil_pec_drain |
| 208 | |
| 209 | /* 0in assert -var isb2iil_vld |
| 210 | -active ((is_ihb_rcd_ps2 & ihb_rcd_is_cpl) | |
| 211 | is_cto_rcd_ps2 ) */ |
| 212 | |
| 213 | /* 0in state -var state -val (5'b1 << IDLE) -next |
| 214 | (5'b1 << IDLE) |
| 215 | (5'b1 << IHB) |
| 216 | (5'b1 << CTO_WAIT) |
| 217 | (5'b1 << CTO_SERV) |
| 218 | (5'b1 << DRAIN) */ |
| 219 | |
| 220 | /* 0in state -var state -val (5'b1 << IHB) -next |
| 221 | (5'b1 << IDLE) |
| 222 | (5'b1 << IHB) |
| 223 | (5'b1 << CTO_WAIT) |
| 224 | (5'b1 << CTO_SERV) |
| 225 | (5'b1 << DRAIN) */ |
| 226 | |
| 227 | |
| 228 | /* 0in state -var state -val (5'b1 << CTO_WAIT) -next |
| 229 | (5'b1 << CTO_WAIT) |
| 230 | (5'b1 << CTO_SERV) */ |
| 231 | |
| 232 | /* 0in state -var state -val (5'b1 << CTO_SERV) -next |
| 233 | (5'b1 << IDLE) */ |
| 234 | |
| 235 | /* 0in state -var state -val (5'b1 << DRAIN) -next |
| 236 | (5'b1 << IDLE) |
| 237 | (5'b1 << DRAIN) */ |
| 238 | |
| 239 | // >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 240 | |
| 241 | //--------------------------------------------------------------------- |
| 242 | // PIO completion timeout request (cto) handling in stage 0 |
| 243 | //--------------------------------------------------------------------- |
| 244 | assign cto_req = n_cto_req_reg ^ cto_req_reg; |
| 245 | assign n_cto_ack = d2p_cto_ack ^ is_cto_rcd_ps1; |
| 246 | |
| 247 | always @ (posedge clk) |
| 248 | if (!rst_l) begin |
| 249 | d2p_cto_ack <= 1'b0; |
| 250 | end |
| 251 | else begin |
| 252 | d2p_cto_ack <= n_cto_ack; |
| 253 | end |
| 254 | |
| 255 | always @ (posedge clk) |
| 256 | if (!rst_l) begin |
| 257 | cto_req_reg <= {{1'b0}}; |
| 258 | end |
| 259 | else begin |
| 260 | cto_req_reg <= n_cto_req_reg; |
| 261 | end |
| 262 | |
| 263 | //--------------------------------------------------------------------- |
| 264 | // propagation through pipeline |
| 265 | //--------------------------------------------------------------------- |
| 266 | // assign pio_tag_ne0 = cib2iil_drain ? pio_tag_drain : p2d_cto_tag; |
| 267 | |
| 268 | assign pio_tag_ne0 = n_state[DRAIN] ? pio_tag_drain : p2d_cto_tag; |
| 269 | |
| 270 | assign is_cto_rcd_ps1 = state[CTO_SERV]; |
| 271 | assign is_ihb_rcd_ps1 = state[IHB]; |
| 272 | assign is_drain_rcd_ps1 = state[DRAIN]; |
| 273 | |
| 274 | always @ (posedge clk) |
| 275 | if (!rst_l) begin |
| 276 | pio_tag_ps1 <= {5{1'b0}}; |
| 277 | pio_tag_ps2 <= {5{1'b0}}; |
| 278 | is_cto_rcd_ps2 <= {{1'b0}}; |
| 279 | is_ihb_rcd_ps2 <= {{1'b0}}; |
| 280 | is_drain_rcd_ps2 <= {{1'b0}}; |
| 281 | y2k_rcd_enq <= {{1'b0}}; |
| 282 | end |
| 283 | else begin |
| 284 | pio_tag_ps1 <= pio_tag_ne0; |
| 285 | pio_tag_ps2 <= pio_tag_ps1; |
| 286 | is_cto_rcd_ps2 <= is_cto_rcd_ps1; |
| 287 | is_ihb_rcd_ps2 <= is_ihb_rcd_ps1; |
| 288 | is_drain_rcd_ps2 <= is_drain_rcd_ps1; |
| 289 | y2k_rcd_enq <= n_y2k_rcd_enq; |
| 290 | end |
| 291 | |
| 292 | assign is_ihb_rcd = is_ihb_rcd_ps2; |
| 293 | assign is_cto_rcd = is_cto_rcd_ps2; |
| 294 | assign pio_tag_gen = pio_tag_ps2; |
| 295 | |
| 296 | //--------------------------------------------------------------------- |
| 297 | // fsm - stage 0 |
| 298 | //--------------------------------------------------------------------- |
| 299 | |
| 300 | // summit state_vector state enum xfr_enum |
| 301 | |
| 302 | // present state |
| 303 | always @ (posedge clk) |
| 304 | begin |
| 305 | if (!rst_l) begin |
| 306 | state <= {STATE_NUM{1'b0}}; |
| 307 | state[IDLE] <= 1'b1; |
| 308 | end |
| 309 | else |
| 310 | state <= n_state; |
| 311 | end |
| 312 | |
| 313 | |
| 314 | // next state ps 0 logic |
| 315 | always @ (state or is_fifo_space or cto_req or cib2iil_ihb_pe_drain or cib2iil_pec_drain or ihb_empty) |
| 316 | begin |
| 317 | n_state = {STATE_NUM{1'b0}}; |
| 318 | case (1'b1) // 0in < case -full // synopsys parallel_case |
| 319 | |
| 320 | state[IDLE], |
| 321 | state[IHB] : |
| 322 | casez ({is_fifo_space, cib2iil_ihb_pe_drain, cib2iil_pec_drain, cto_req, ihb_empty}) // 0in < case -parallel -full |
| 323 | 5'b0001z: n_state[CTO_WAIT] = 1'b1; |
| 324 | |
| 325 | 5'b1001z: n_state[CTO_SERV] = 1'b1; |
| 326 | |
| 327 | 5'b0000z, |
| 328 | 5'b10001, |
| 329 | 5'b01zzz, |
| 330 | 5'b001zz: n_state[IDLE] = 1'b1; |
| 331 | |
| 332 | 5'b11zzz, |
| 333 | 5'b101z1: n_state[DRAIN] = 1'b1; |
| 334 | |
| 335 | 5'b10000, |
| 336 | 5'b101z0: n_state[IHB] = 1'b1; |
| 337 | endcase // casez({is_fifo_space, cib2iil_ihb_pe_drain, cib2iil_pec_drain, cto_req, ihb_empty}) |
| 338 | |
| 339 | state[DRAIN] : |
| 340 | casez ({cib2iil_ihb_pe_drain, cib2iil_pec_drain, is_fifo_space}) // 0in < case -parallel -full |
| 341 | 3'b011, |
| 342 | 3'b1z1: n_state[DRAIN] = 1'b1; |
| 343 | |
| 344 | 3'bzz0, |
| 345 | 3'b001: n_state[IDLE] = 1'b1; |
| 346 | endcase // case({cib2iil_ihb_pe_drain, cib2iil_pec_drain, is_fifo_space}) |
| 347 | |
| 348 | state[CTO_WAIT] : |
| 349 | if (is_fifo_space) n_state[CTO_SERV] = 1'b1; |
| 350 | else n_state[CTO_WAIT] = 1'b1; |
| 351 | |
| 352 | state[CTO_SERV]: n_state[IDLE] = 1'b1; |
| 353 | |
| 354 | endcase // case(1'b1) |
| 355 | end // always @ (state, is_fifo_space, cto_req, cib2iil_ihb_pe_drain, cib2iil_pec_drain, ihb_empty) |
| 356 | |
| 357 | // outputs |
| 358 | assign ihb_rptr_inc = n_state[IHB]; |
| 359 | assign cnsm_crdt = n_state[DRAIN] | n_state[IHB] | n_state[CTO_SERV]; |
| 360 | |
| 361 | //--------------------------------------------------------------------- |
| 362 | // log iil2cib_ihb_pe to reg ihb_ihb_pe_detected as a status bit |
| 363 | //--------------------------------------------------------------------- |
| 364 | always @(posedge clk) begin |
| 365 | if (~rst_l) begin |
| 366 | ihb_ihb_pe_detected <= 1'b0; |
| 367 | end |
| 368 | else if (iil2cib_ihb_pe) begin |
| 369 | ihb_ihb_pe_detected <= 1'b1; |
| 370 | end |
| 371 | end |
| 372 | |
| 373 | //--------------------------------------------------------------------- |
| 374 | // check if inserted rcd need be dropped |
| 375 | //--------------------------------------------------------------------- |
| 376 | assign drop_inserted_rcd = (is_ihb_rcd_ps2 & iil2cib_ihb_pe) | |
| 377 | (is_ihb_rcd_ps2 & ihb_ihb_pe_detected) | |
| 378 | ((is_cto_rcd_ps2 | is_drain_rcd_ps2) & |
| 379 | ~isb2iil_vld); |
| 380 | |
| 381 | assign n_y2k_rcd_enq = (is_ihb_rcd_ps2 | is_cto_rcd_ps2 | is_drain_rcd_ps2) & |
| 382 | (~drop_inserted_rcd); |
| 383 | |
| 384 | assign crdt_back = drop_inserted_rcd; |
| 385 | |
| 386 | //--------------------------------------------------------------------- |
| 387 | // only assert iil2isb_clr when the entry is valid |
| 388 | //--------------------------------------------------------------------- |
| 389 | // assign iil2isb_clr = isb2iil_vld & ((is_ihb_rcd_ps2 & ihb_rcd_is_cpl) | |
| 390 | // is_cto_rcd_ps2 | is_drain_rcd_ps2); |
| 391 | //BP n2 4-8-05 bug 92994 rfe 2258 |
| 392 | assign iil2isb_clr = isb2iil_vld & |
| 393 | ((is_ihb_rcd_ps2 & ihb_rcd_is_cpl & ~iil2cib_ihb_pe & ~ihb_ihb_pe_detected) |
| 394 | | is_cto_rcd_ps2 |
| 395 | | is_drain_rcd_ps2); |
| 396 | |
| 397 | //--------------------------------------------------------------------- |
| 398 | // TMU rcd fifo credit management |
| 399 | //--------------------------------------------------------------------- |
| 400 | // next fifo_credit |
| 401 | always @(fifo_credit or crdt_back or k2y_rcd_deq or cnsm_crdt) |
| 402 | case ({crdt_back, k2y_rcd_deq, cnsm_crdt}) |
| 403 | 3'b000: n_fifo_credit = fifo_credit; |
| 404 | 3'b001: n_fifo_credit = fifo_credit - 1'b1; |
| 405 | 3'b010: n_fifo_credit = fifo_credit + 1'b1; |
| 406 | 3'b011: n_fifo_credit = fifo_credit; |
| 407 | 3'b100: n_fifo_credit = fifo_credit + 1'b1; |
| 408 | 3'b101: n_fifo_credit = fifo_credit; |
| 409 | 3'b110: n_fifo_credit = fifo_credit + 3'b010; |
| 410 | 3'b111: n_fifo_credit = fifo_credit + 1'b1; |
| 411 | endcase // case({crdt_back, k2y_rcd_deq, cnsm_crdt}) |
| 412 | |
| 413 | // current fifo_credit |
| 414 | always @(posedge clk) |
| 415 | if (~rst_l) |
| 416 | fifo_credit <= 3'b110; |
| 417 | else |
| 418 | fifo_credit <= n_fifo_credit; |
| 419 | |
| 420 | // is_fifo_space check |
| 421 | assign is_fifo_space = |fifo_credit; |
| 422 | |
| 423 | //--------------------------------------------------------------------- |
| 424 | // loop through scoreboad for pio_tag_drain |
| 425 | //--------------------------------------------------------------------- |
| 426 | always @(posedge clk) |
| 427 | if (~rst_l) |
| 428 | pio_tag_drain <= 5'b0; |
| 429 | else if (state[DRAIN]) |
| 430 | pio_tag_drain <= pio_tag_drain + 1'b1; |
| 431 | |
| 432 | //--------------------------------------------------------------------- |
| 433 | // idle check output |
| 434 | //--------------------------------------------------------------------- |
| 435 | |
| 436 | assign iil_is_idle = ihb_empty & state[IDLE]; |
| 437 | |
| 438 | // >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<< |
| 439 | |
| 440 | // sync-flop instantiations for p2d_cto_req |
| 441 | // pcie_common_sync_flop #(1) cto_req_sync_flop( |
| 442 | // .clk(clk), |
| 443 | // .din(p2d_cto_req), |
| 444 | // .dout(n_cto_req_reg)); |
| 445 | cl_a1_clksyncff_4x cto_req_sync_flop ( .d(p2d_cto_req), .si(1'b0), .q( n_cto_req_reg), .so(), |
| 446 | .l1clk(clk), .siclk(1'b0), .soclk(1'b0) ); |
| 447 | |
| 448 | |
| 449 | endmodule // dmu_ilu_iil_xfrfsm |
| 450 | |