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// OpenSPARC T2 Processor File: dmu_ilu_iil_xfrfsm.v
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module dmu_ilu_iil_xfrfsm (
cib2iil_ihb_pe_drain, // caused by iil2cib_ihb_pe
cib2iil_pec_drain, // caused by p2d_drain
//synopsys sync_set_reset "rst_l"
// >>>>>>>>>>>>>>>>>>>>>>>>> Parameter Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
parameter // summit enum xfr_enum
// >>>>>>>>>>>>>>>>>>>>>>>>> Port Declarations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
//---------------------------------------------------------------------
// Clock and Reset Signals
//---------------------------------------------------------------------
input clk; // input clock
input rst_l; // input reset
//---------------------------------------------------------------------
// cto interface - PIO completion time out
//---------------------------------------------------------------------
input p2d_cto_req; // cto request from TLU
output d2p_cto_ack; // cto ack back
output n_cto_req_reg; // p2d_cto_req synchronized to iol2clk for dbg
//---------------------------------------------------------------------
//---------------------------------------------------------------------
// input cib2iil_drain; // drain signal
input cib2iil_ihb_pe_drain; // caused by iil2cib_ihb_pe
input cib2iil_pec_drain; // caused by p2d_drain
//---------------------------------------------------------------------
// record interface to TMU
//---------------------------------------------------------------------
input k2y_rcd_deq; // record fifo dequeue
output y2k_rcd_enq; // ingress PEC record enqueue
//---------------------------------------------------------------------
// sub-block to sub-block interface
//---------------------------------------------------------------------
input iil2cib_ihb_pe; // ingress header parity error, from *_parchk.v
//---------------------------------------------------------------------
//---------------------------------------------------------------------
input ihb_rcd_is_cpl; // to determine iil2isb_clr, from *_rcdbldr.v
//---------------------------------------------------------------------
//---------------------------------------------------------------------
input ihb_empty; // from *_bufmgr.v
output ihb_rptr_inc; // advance ihb rptr, to *_bufmgr.v
//---------------------------------------------------------------------
//---------------------------------------------------------------------
output is_ihb_rcd; // in-process rcd is ihb rcd, to *_rcdbldr.v & *_crdtcnt.v
output is_cto_rcd; // in-process rcd is CTO rcd, to *_rcdbldr.v
output [4:0] pio_tag_gen; // pio_tag to gen cpl header, to *_rcdbldr.v
//---------------------------------------------------------------------
//---------------------------------------------------------------------
output [STATE_NUM-1:0] state;
output drop_inserted_rcd;
//---------------------------------------------------------------------
//---------------------------------------------------------------------
// >>>>>>>>>>>>>>>>>>>>>>>>> Data Type Declarations <<<<<<<<<<<<<<<<<<<<<<<<<
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
reg [STATE_NUM-1:0] state;
reg [4:0] pio_tag_drain; // loop through in drain state
reg [2:0] fifo_credit; // TMU rcd fifo credit
// ~~~~~~~~~~~~~~~~~~~~~~~~~ REGISTER - NON-FLOPS ~~~~~~~~~~~~~~~~~~~~~~~~
reg [STATE_NUM-1:0] n_state;
reg [2:0] n_fifo_credit; // TMU rcd next fifo credit value
// ~~~~~~~~~~~~~~~~~~~~~~~~~ NETS ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
wire [4:0] pio_tag_ne0; // muxed out from pio_tag_drain and p2d_cto_tag
wire crdt_back; // fifo credit when rcd need be dropped
wire cnsm_crdt; // consume fifo credit when inject rcd in pipeline
// >>>>>>>>>>>>>>>>>>>>>>>>> Zero In Checkers <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// 0in one_hot -var state
// 0in max -var fifo_credit -val 6
// 0in known_driven -var cib2iil_ihb_pe_drain
// 0in known_driven -var cib2iil_pec_drain
/* 0in assert -var isb2iil_vld
-active ((is_ihb_rcd_ps2 & ihb_rcd_is_cpl) |
/* 0in state -var state -val (5'b1 << IDLE) -next
/* 0in state -var state -val (5'b1 << IHB) -next
/* 0in state -var state -val (5'b1 << CTO_WAIT) -next
/* 0in state -var state -val (5'b1 << CTO_SERV) -next
/* 0in state -var state -val (5'b1 << DRAIN) -next
// >>>>>>>>>>>>>>>>>>>>>>>>> RTL/Behavioral Model <<<<<<<<<<<<<<<<<<<<<<<<<<<
//---------------------------------------------------------------------
// PIO completion timeout request (cto) handling in stage 0
//---------------------------------------------------------------------
assign cto_req = n_cto_req_reg ^ cto_req_reg;
assign n_cto_ack = d2p_cto_ack ^ is_cto_rcd_ps1;
d2p_cto_ack <= n_cto_ack;
cto_req_reg <= n_cto_req_reg;
//---------------------------------------------------------------------
// propagation through pipeline
//---------------------------------------------------------------------
// assign pio_tag_ne0 = cib2iil_drain ? pio_tag_drain : p2d_cto_tag;
assign pio_tag_ne0 = n_state[DRAIN] ? pio_tag_drain : p2d_cto_tag;
assign is_cto_rcd_ps1 = state[CTO_SERV];
assign is_ihb_rcd_ps1 = state[IHB];
assign is_drain_rcd_ps1 = state[DRAIN];
pio_tag_ps1 <= {5{1'b0}};
pio_tag_ps2 <= {5{1'b0}};
is_cto_rcd_ps2 <= {{1'b0}};
is_ihb_rcd_ps2 <= {{1'b0}};
is_drain_rcd_ps2 <= {{1'b0}};
pio_tag_ps1 <= pio_tag_ne0;
pio_tag_ps2 <= pio_tag_ps1;
is_cto_rcd_ps2 <= is_cto_rcd_ps1;
is_ihb_rcd_ps2 <= is_ihb_rcd_ps1;
is_drain_rcd_ps2 <= is_drain_rcd_ps1;
y2k_rcd_enq <= n_y2k_rcd_enq;
assign is_ihb_rcd = is_ihb_rcd_ps2;
assign is_cto_rcd = is_cto_rcd_ps2;
assign pio_tag_gen = pio_tag_ps2;
//---------------------------------------------------------------------
//---------------------------------------------------------------------
// summit state_vector state enum xfr_enum
state <= {STATE_NUM{1'b0}};
always @ (state or is_fifo_space or cto_req or cib2iil_ihb_pe_drain or cib2iil_pec_drain or ihb_empty)
n_state = {STATE_NUM{1'b0}};
case (1'b1) // 0in < case -full // synopsys parallel_case
casez ({is_fifo_space, cib2iil_ihb_pe_drain, cib2iil_pec_drain, cto_req, ihb_empty}) // 0in < case -parallel -full
5'b0001z: n_state[CTO_WAIT] = 1'b1;
5'b1001z: n_state[CTO_SERV] = 1'b1;
5'b001zz: n_state[IDLE] = 1'b1;
5'b101z1: n_state[DRAIN] = 1'b1;
5'b101z0: n_state[IHB] = 1'b1;
endcase // casez({is_fifo_space, cib2iil_ihb_pe_drain, cib2iil_pec_drain, cto_req, ihb_empty})
casez ({cib2iil_ihb_pe_drain, cib2iil_pec_drain, is_fifo_space}) // 0in < case -parallel -full
3'b1z1: n_state[DRAIN] = 1'b1;
3'b001: n_state[IDLE] = 1'b1;
endcase // case({cib2iil_ihb_pe_drain, cib2iil_pec_drain, is_fifo_space})
if (is_fifo_space) n_state[CTO_SERV] = 1'b1;
else n_state[CTO_WAIT] = 1'b1;
state[CTO_SERV]: n_state[IDLE] = 1'b1;
end // always @ (state, is_fifo_space, cto_req, cib2iil_ihb_pe_drain, cib2iil_pec_drain, ihb_empty)
assign ihb_rptr_inc = n_state[IHB];
assign cnsm_crdt = n_state[DRAIN] | n_state[IHB] | n_state[CTO_SERV];
//---------------------------------------------------------------------
// log iil2cib_ihb_pe to reg ihb_ihb_pe_detected as a status bit
//---------------------------------------------------------------------
always @(posedge clk) begin
ihb_ihb_pe_detected <= 1'b0;
else if (iil2cib_ihb_pe) begin
ihb_ihb_pe_detected <= 1'b1;
//---------------------------------------------------------------------
// check if inserted rcd need be dropped
//---------------------------------------------------------------------
assign drop_inserted_rcd = (is_ihb_rcd_ps2 & iil2cib_ihb_pe) |
(is_ihb_rcd_ps2 & ihb_ihb_pe_detected) |
((is_cto_rcd_ps2 | is_drain_rcd_ps2) &
assign n_y2k_rcd_enq = (is_ihb_rcd_ps2 | is_cto_rcd_ps2 | is_drain_rcd_ps2) &
assign crdt_back = drop_inserted_rcd;
//---------------------------------------------------------------------
// only assert iil2isb_clr when the entry is valid
//---------------------------------------------------------------------
// assign iil2isb_clr = isb2iil_vld & ((is_ihb_rcd_ps2 & ihb_rcd_is_cpl) |
// is_cto_rcd_ps2 | is_drain_rcd_ps2);
//BP n2 4-8-05 bug 92994 rfe 2258
assign iil2isb_clr = isb2iil_vld &
((is_ihb_rcd_ps2 & ihb_rcd_is_cpl & ~iil2cib_ihb_pe & ~ihb_ihb_pe_detected)
//---------------------------------------------------------------------
// TMU rcd fifo credit management
//---------------------------------------------------------------------
always @(fifo_credit or crdt_back or k2y_rcd_deq or cnsm_crdt)
case ({crdt_back, k2y_rcd_deq, cnsm_crdt})
3'b000: n_fifo_credit = fifo_credit;
3'b001: n_fifo_credit = fifo_credit - 1'b1;
3'b010: n_fifo_credit = fifo_credit + 1'b1;
3'b011: n_fifo_credit = fifo_credit;
3'b100: n_fifo_credit = fifo_credit + 1'b1;
3'b101: n_fifo_credit = fifo_credit;
3'b110: n_fifo_credit = fifo_credit + 3'b010;
3'b111: n_fifo_credit = fifo_credit + 1'b1;
endcase // case({crdt_back, k2y_rcd_deq, cnsm_crdt})
fifo_credit <= n_fifo_credit;
assign is_fifo_space = |fifo_credit;
//---------------------------------------------------------------------
// loop through scoreboad for pio_tag_drain
//---------------------------------------------------------------------
pio_tag_drain <= pio_tag_drain + 1'b1;
//---------------------------------------------------------------------
//---------------------------------------------------------------------
assign iil_is_idle = ihb_empty & state[IDLE];
// >>>>>>>>>>>>>>>>>>>>>>>>> Instantiations <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
// sync-flop instantiations for p2d_cto_req
// pcie_common_sync_flop #(1) cto_req_sync_flop(
// .dout(n_cto_req_reg));
cl_a1_clksyncff_4x cto_req_sync_flop ( .d(p2d_cto_req), .si(1'b0), .q( n_cto_req_reg), .so(),
.l1clk(clk), .siclk(1'b0), .soclk(1'b0) );
endmodule // dmu_ilu_iil_xfrfsm