| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_logged_error_status_reg_entry.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_imu_ics_csr_imu_logged_error_status_reg_entry |
| 36 | ( |
| 37 | // synopsys translate_off |
| 38 | omni_ld, |
| 39 | omni_data, |
| 40 | omni_rw1c_alias, |
| 41 | omni_rw1s_alias, |
| 42 | // synopsys translate_on |
| 43 | clk, |
| 44 | por_l, |
| 45 | w_ld, |
| 46 | csrbus_wr_data, |
| 47 | rw1c_alias, |
| 48 | rw1s_alias, |
| 49 | imu_logged_error_status_reg_csrbus_read_data, |
| 50 | imu_logged_error_status_reg_spare_s_hw_set, |
| 51 | imu_logged_error_status_reg_eq_over_s_hw_set, |
| 52 | imu_logged_error_status_reg_eq_not_en_s_hw_set, |
| 53 | imu_logged_error_status_reg_msi_mal_err_s_hw_set, |
| 54 | imu_logged_error_status_reg_msi_par_err_s_hw_set, |
| 55 | imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set, |
| 56 | imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set, |
| 57 | imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set, |
| 58 | imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set, |
| 59 | imu_logged_error_status_reg_cor_mes_not_en_s_hw_set, |
| 60 | imu_logged_error_status_reg_msi_not_en_s_hw_set, |
| 61 | imu_logged_error_status_reg_spare_p_hw_set, |
| 62 | imu_logged_error_status_reg_eq_over_p_hw_set, |
| 63 | imu_logged_error_status_reg_eq_not_en_p_hw_set, |
| 64 | imu_logged_error_status_reg_msi_mal_err_p_hw_set, |
| 65 | imu_logged_error_status_reg_msi_par_err_p_hw_set, |
| 66 | imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set, |
| 67 | imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set, |
| 68 | imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set, |
| 69 | imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set, |
| 70 | imu_logged_error_status_reg_cor_mes_not_en_p_hw_set, |
| 71 | imu_logged_error_status_reg_msi_not_en_p_hw_set |
| 72 | ); |
| 73 | |
| 74 | //==================================================================== |
| 75 | // Polarity declarations |
| 76 | //==================================================================== |
| 77 | // synopsys translate_off |
| 78 | input omni_ld; // Omni load |
| 79 | // vlint flag_input_port_not_connected off |
| 80 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH - 1:0] omni_data; |
| 81 | // Omni write data |
| 82 | // vlint flag_input_port_not_connected on |
| 83 | input omni_rw1c_alias; // Omni load type: write-one-to-clear |
| 84 | input omni_rw1s_alias; // Omni load type: write-one-to-set |
| 85 | // synopsys translate_on |
| 86 | input clk; // Clock signal |
| 87 | input por_l; // Reset signal |
| 88 | input w_ld; // SW load |
| 89 | // vlint flag_input_port_not_connected off |
| 90 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 91 | // vlint flag_input_port_not_connected on |
| 92 | input rw1c_alias; // SW load type: write-one-to-clear |
| 93 | input rw1s_alias; // SW load type: write-one-to-set |
| 94 | output [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH-1:0] |
| 95 | imu_logged_error_status_reg_csrbus_read_data; // SW read data |
| 96 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC] |
| 97 | imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for |
| 98 | // imu_logged_error_status_reg_spare_s. |
| 99 | // When set |
| 100 | // imu_logged_error_status_reg |
| 101 | // will be set to one. |
| 102 | input imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for |
| 103 | // imu_logged_error_status_reg_eq_over_s. |
| 104 | // When set |
| 105 | // imu_logged_error_status_reg |
| 106 | // will be set to one. |
| 107 | input imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal |
| 108 | // for |
| 109 | // imu_logged_error_status_reg_eq_not_en_s. |
| 110 | // When set |
| 111 | // imu_logged_error_status_reg |
| 112 | // will be set to one. |
| 113 | input imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal |
| 114 | // for |
| 115 | // imu_logged_error_status_reg_msi_mal_err_s. |
| 116 | // When set |
| 117 | // imu_logged_error_status_reg |
| 118 | // will be set to one. |
| 119 | input imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal |
| 120 | // for |
| 121 | // imu_logged_error_status_reg_msi_par_err_s. |
| 122 | // When set |
| 123 | // imu_logged_error_status_reg |
| 124 | // will be set to one. |
| 125 | input imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set |
| 126 | // signal for |
| 127 | // imu_logged_error_status_reg_pmeack_mes_not_en_s. |
| 128 | // When set |
| 129 | // imu_logged_error_status_reg |
| 130 | // will be set |
| 131 | // to one. |
| 132 | input imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set |
| 133 | // signal for |
| 134 | // imu_logged_error_status_reg_pmpme_mes_not_en_s. |
| 135 | // When set |
| 136 | // imu_logged_error_status_reg |
| 137 | // will be set to |
| 138 | // one. |
| 139 | input imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set |
| 140 | // signal for |
| 141 | // imu_logged_error_status_reg_fatal_mes_not_en_s. |
| 142 | // When set |
| 143 | // imu_logged_error_status_reg |
| 144 | // will be set to |
| 145 | // one. |
| 146 | input imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware |
| 147 | // set signal |
| 148 | // for |
| 149 | // imu_logged_error_status_reg_nonfatal_mes_not_en_s. |
| 150 | // When set |
| 151 | // imu_logged_error_status_reg |
| 152 | // will be set |
| 153 | // to one. |
| 154 | input imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set |
| 155 | // signal for |
| 156 | // imu_logged_error_status_reg_cor_mes_not_en_s. |
| 157 | // When set |
| 158 | // imu_logged_error_status_reg |
| 159 | // will be set to |
| 160 | // one. |
| 161 | input imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal |
| 162 | // for |
| 163 | // imu_logged_error_status_reg_msi_not_en_s. |
| 164 | // When set |
| 165 | // imu_logged_error_status_reg |
| 166 | // will be set to one. |
| 167 | input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC] |
| 168 | imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for |
| 169 | // imu_logged_error_status_reg_spare_p. |
| 170 | // When set |
| 171 | // imu_logged_error_status_reg |
| 172 | // will be set to one. |
| 173 | input imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for |
| 174 | // imu_logged_error_status_reg_eq_over_p. |
| 175 | // When set |
| 176 | // imu_logged_error_status_reg |
| 177 | // will be set to one. |
| 178 | input imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal |
| 179 | // for |
| 180 | // imu_logged_error_status_reg_eq_not_en_p. |
| 181 | // When set |
| 182 | // imu_logged_error_status_reg |
| 183 | // will be set to one. |
| 184 | input imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal |
| 185 | // for |
| 186 | // imu_logged_error_status_reg_msi_mal_err_p. |
| 187 | // When set |
| 188 | // imu_logged_error_status_reg |
| 189 | // will be set to one. |
| 190 | input imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal |
| 191 | // for |
| 192 | // imu_logged_error_status_reg_msi_par_err_p. |
| 193 | // When set |
| 194 | // imu_logged_error_status_reg |
| 195 | // will be set to one. |
| 196 | input imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set |
| 197 | // signal for |
| 198 | // imu_logged_error_status_reg_pmeack_mes_not_en_p. |
| 199 | // When set |
| 200 | // imu_logged_error_status_reg |
| 201 | // will be set |
| 202 | // to one. |
| 203 | input imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set |
| 204 | // signal for |
| 205 | // imu_logged_error_status_reg_pmpme_mes_not_en_p. |
| 206 | // When set |
| 207 | // imu_logged_error_status_reg |
| 208 | // will be set to |
| 209 | // one. |
| 210 | input imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set |
| 211 | // signal for |
| 212 | // imu_logged_error_status_reg_fatal_mes_not_en_p. |
| 213 | // When set |
| 214 | // imu_logged_error_status_reg |
| 215 | // will be set to |
| 216 | // one. |
| 217 | input imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware |
| 218 | // set signal |
| 219 | // for |
| 220 | // imu_logged_error_status_reg_nonfatal_mes_not_en_p. |
| 221 | // When set |
| 222 | // imu_logged_error_status_reg |
| 223 | // will be set |
| 224 | // to one. |
| 225 | input imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set |
| 226 | // signal for |
| 227 | // imu_logged_error_status_reg_cor_mes_not_en_p. |
| 228 | // When set |
| 229 | // imu_logged_error_status_reg |
| 230 | // will be set to |
| 231 | // one. |
| 232 | input imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal |
| 233 | // for |
| 234 | // imu_logged_error_status_reg_msi_not_en_p. |
| 235 | // When set |
| 236 | // imu_logged_error_status_reg |
| 237 | // will be set to one. |
| 238 | |
| 239 | //==================================================================== |
| 240 | // Type declarations |
| 241 | //==================================================================== |
| 242 | // synopsys translate_off |
| 243 | wire omni_ld; // Omni load |
| 244 | // vlint flag_dangling_net_within_module off |
| 245 | // vlint flag_net_has_no_load off |
| 246 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH - 1:0] omni_data; |
| 247 | // Omni write data |
| 248 | // vlint flag_dangling_net_within_module on |
| 249 | // vlint flag_net_has_no_load on |
| 250 | wire omni_rw1c_alias; // Omni load type: write-one-to-clear |
| 251 | wire omni_rw1s_alias; // Omni load type: write-one-to-set |
| 252 | // synopsys translate_on |
| 253 | wire clk; // Clock signal |
| 254 | wire por_l; // Reset signal |
| 255 | wire w_ld; // SW load |
| 256 | // vlint flag_dangling_net_within_module off |
| 257 | // vlint flag_net_has_no_load off |
| 258 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 259 | // vlint flag_dangling_net_within_module on |
| 260 | // vlint flag_net_has_no_load on |
| 261 | wire rw1c_alias; // SW load type: write-one-to-clear |
| 262 | wire rw1s_alias; // SW load type: write-one-to-set |
| 263 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH-1:0] |
| 264 | imu_logged_error_status_reg_csrbus_read_data; // SW read data |
| 265 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC] |
| 266 | imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for |
| 267 | // imu_logged_error_status_reg_spare_s. |
| 268 | // When set |
| 269 | // imu_logged_error_status_reg |
| 270 | // will be set to one. |
| 271 | wire imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for |
| 272 | // imu_logged_error_status_reg_eq_over_s. |
| 273 | // When set |
| 274 | // imu_logged_error_status_reg |
| 275 | // will be set to one. |
| 276 | wire imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal for |
| 277 | // imu_logged_error_status_reg_eq_not_en_s. |
| 278 | // When set |
| 279 | // imu_logged_error_status_reg |
| 280 | // will be set to one. |
| 281 | wire imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal |
| 282 | // for |
| 283 | // imu_logged_error_status_reg_msi_mal_err_s. |
| 284 | // When set |
| 285 | // imu_logged_error_status_reg |
| 286 | // will be set to one. |
| 287 | wire imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal |
| 288 | // for |
| 289 | // imu_logged_error_status_reg_msi_par_err_s. |
| 290 | // When set |
| 291 | // imu_logged_error_status_reg |
| 292 | // will be set to one. |
| 293 | wire imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set |
| 294 | // signal for |
| 295 | // imu_logged_error_status_reg_pmeack_mes_not_en_s. |
| 296 | // When set |
| 297 | // imu_logged_error_status_reg |
| 298 | // will be set to |
| 299 | // one. |
| 300 | wire imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set |
| 301 | // signal for |
| 302 | // imu_logged_error_status_reg_pmpme_mes_not_en_s. |
| 303 | // When set |
| 304 | // imu_logged_error_status_reg |
| 305 | // will be set to |
| 306 | // one. |
| 307 | wire imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set |
| 308 | // signal for |
| 309 | // imu_logged_error_status_reg_fatal_mes_not_en_s. |
| 310 | // When set |
| 311 | // imu_logged_error_status_reg |
| 312 | // will be set to |
| 313 | // one. |
| 314 | wire imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware set |
| 315 | // signal for |
| 316 | // imu_logged_error_status_reg_nonfatal_mes_not_en_s. |
| 317 | // When set |
| 318 | // imu_logged_error_status_reg |
| 319 | // will be set |
| 320 | // to one. |
| 321 | wire imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set |
| 322 | // signal for |
| 323 | // imu_logged_error_status_reg_cor_mes_not_en_s. |
| 324 | // When set |
| 325 | // imu_logged_error_status_reg |
| 326 | // will be set to |
| 327 | // one. |
| 328 | wire imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal |
| 329 | // for |
| 330 | // imu_logged_error_status_reg_msi_not_en_s. |
| 331 | // When set |
| 332 | // imu_logged_error_status_reg |
| 333 | // will be set to one. |
| 334 | wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC] |
| 335 | imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for |
| 336 | // imu_logged_error_status_reg_spare_p. |
| 337 | // When set |
| 338 | // imu_logged_error_status_reg |
| 339 | // will be set to one. |
| 340 | wire imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for |
| 341 | // imu_logged_error_status_reg_eq_over_p. |
| 342 | // When set |
| 343 | // imu_logged_error_status_reg |
| 344 | // will be set to one. |
| 345 | wire imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal for |
| 346 | // imu_logged_error_status_reg_eq_not_en_p. |
| 347 | // When set |
| 348 | // imu_logged_error_status_reg |
| 349 | // will be set to one. |
| 350 | wire imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal |
| 351 | // for |
| 352 | // imu_logged_error_status_reg_msi_mal_err_p. |
| 353 | // When set |
| 354 | // imu_logged_error_status_reg |
| 355 | // will be set to one. |
| 356 | wire imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal |
| 357 | // for |
| 358 | // imu_logged_error_status_reg_msi_par_err_p. |
| 359 | // When set |
| 360 | // imu_logged_error_status_reg |
| 361 | // will be set to one. |
| 362 | wire imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set |
| 363 | // signal for |
| 364 | // imu_logged_error_status_reg_pmeack_mes_not_en_p. |
| 365 | // When set |
| 366 | // imu_logged_error_status_reg |
| 367 | // will be set to |
| 368 | // one. |
| 369 | wire imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set |
| 370 | // signal for |
| 371 | // imu_logged_error_status_reg_pmpme_mes_not_en_p. |
| 372 | // When set |
| 373 | // imu_logged_error_status_reg |
| 374 | // will be set to |
| 375 | // one. |
| 376 | wire imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set |
| 377 | // signal for |
| 378 | // imu_logged_error_status_reg_fatal_mes_not_en_p. |
| 379 | // When set |
| 380 | // imu_logged_error_status_reg |
| 381 | // will be set to |
| 382 | // one. |
| 383 | wire imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware set |
| 384 | // signal for |
| 385 | // imu_logged_error_status_reg_nonfatal_mes_not_en_p. |
| 386 | // When set |
| 387 | // imu_logged_error_status_reg |
| 388 | // will be set |
| 389 | // to one. |
| 390 | wire imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set |
| 391 | // signal for |
| 392 | // imu_logged_error_status_reg_cor_mes_not_en_p. |
| 393 | // When set |
| 394 | // imu_logged_error_status_reg |
| 395 | // will be set to |
| 396 | // one. |
| 397 | wire imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal |
| 398 | // for |
| 399 | // imu_logged_error_status_reg_msi_not_en_p. |
| 400 | // When set |
| 401 | // imu_logged_error_status_reg |
| 402 | // will be set to one. |
| 403 | |
| 404 | //==================================================================== |
| 405 | // Logic |
| 406 | //==================================================================== |
| 407 | |
| 408 | //----- Reset values |
| 409 | // verilint 531 off |
| 410 | wire [4:0] reset_spare_s = 5'h0; |
| 411 | wire [0:0] reset_eq_over_s = 1'h0; |
| 412 | wire [0:0] reset_eq_not_en_s = 1'h0; |
| 413 | wire [0:0] reset_msi_mal_err_s = 1'h0; |
| 414 | wire [0:0] reset_msi_par_err_s = 1'h0; |
| 415 | wire [0:0] reset_pmeack_mes_not_en_s = 1'h0; |
| 416 | wire [0:0] reset_pmpme_mes_not_en_s = 1'h0; |
| 417 | wire [0:0] reset_fatal_mes_not_en_s = 1'h0; |
| 418 | wire [0:0] reset_nonfatal_mes_not_en_s = 1'h0; |
| 419 | wire [0:0] reset_cor_mes_not_en_s = 1'h0; |
| 420 | wire [0:0] reset_msi_not_en_s = 1'h0; |
| 421 | wire [4:0] reset_spare_p = 5'h0; |
| 422 | wire [0:0] reset_eq_over_p = 1'h0; |
| 423 | wire [0:0] reset_eq_not_en_p = 1'h0; |
| 424 | wire [0:0] reset_msi_mal_err_p = 1'h0; |
| 425 | wire [0:0] reset_msi_par_err_p = 1'h0; |
| 426 | wire [0:0] reset_pmeack_mes_not_en_p = 1'h0; |
| 427 | wire [0:0] reset_pmpme_mes_not_en_p = 1'h0; |
| 428 | wire [0:0] reset_fatal_mes_not_en_p = 1'h0; |
| 429 | wire [0:0] reset_nonfatal_mes_not_en_p = 1'h0; |
| 430 | wire [0:0] reset_cor_mes_not_en_p = 1'h0; |
| 431 | wire [0:0] reset_msi_not_en_p = 1'h0; |
| 432 | // verilint 531 on |
| 433 | |
| 434 | //----- Active high reset wires |
| 435 | wire por_l_active_high = ~por_l; |
| 436 | |
| 437 | //==================================================== |
| 438 | // Instantiation of flops |
| 439 | //==================================================== |
| 440 | |
| 441 | // bit 0 |
| 442 | csr_sw csr_sw_0 |
| 443 | ( |
| 444 | // synopsys translate_off |
| 445 | .omni_ld (omni_ld), |
| 446 | .omni_data (omni_data[0]), |
| 447 | .omni_rw_alias (1'b0), |
| 448 | .omni_rw1c_alias (omni_rw1c_alias), |
| 449 | .omni_rw1s_alias (omni_rw1s_alias), |
| 450 | // synopsys translate_on |
| 451 | .rst (por_l_active_high), |
| 452 | .rst_val (reset_msi_not_en_p[0]), |
| 453 | .csr_ld (w_ld), |
| 454 | .csr_data (csrbus_wr_data[0]), |
| 455 | .rw_alias (1'b0), |
| 456 | .rw1c_alias (rw1c_alias), |
| 457 | .rw1s_alias (rw1s_alias), |
| 458 | .hw_ld (imu_logged_error_status_reg_msi_not_en_p_hw_set), |
| 459 | .hw_data (1'b1), |
| 460 | .cp (clk), |
| 461 | .q (imu_logged_error_status_reg_csrbus_read_data[0]) |
| 462 | ); |
| 463 | |
| 464 | // bit 1 |
| 465 | csr_sw csr_sw_1 |
| 466 | ( |
| 467 | // synopsys translate_off |
| 468 | .omni_ld (omni_ld), |
| 469 | .omni_data (omni_data[1]), |
| 470 | .omni_rw_alias (1'b0), |
| 471 | .omni_rw1c_alias (omni_rw1c_alias), |
| 472 | .omni_rw1s_alias (omni_rw1s_alias), |
| 473 | // synopsys translate_on |
| 474 | .rst (por_l_active_high), |
| 475 | .rst_val (reset_cor_mes_not_en_p[0]), |
| 476 | .csr_ld (w_ld), |
| 477 | .csr_data (csrbus_wr_data[1]), |
| 478 | .rw_alias (1'b0), |
| 479 | .rw1c_alias (rw1c_alias), |
| 480 | .rw1s_alias (rw1s_alias), |
| 481 | .hw_ld (imu_logged_error_status_reg_cor_mes_not_en_p_hw_set), |
| 482 | .hw_data (1'b1), |
| 483 | .cp (clk), |
| 484 | .q (imu_logged_error_status_reg_csrbus_read_data[1]) |
| 485 | ); |
| 486 | |
| 487 | // bit 2 |
| 488 | csr_sw csr_sw_2 |
| 489 | ( |
| 490 | // synopsys translate_off |
| 491 | .omni_ld (omni_ld), |
| 492 | .omni_data (omni_data[2]), |
| 493 | .omni_rw_alias (1'b0), |
| 494 | .omni_rw1c_alias (omni_rw1c_alias), |
| 495 | .omni_rw1s_alias (omni_rw1s_alias), |
| 496 | // synopsys translate_on |
| 497 | .rst (por_l_active_high), |
| 498 | .rst_val (reset_nonfatal_mes_not_en_p[0]), |
| 499 | .csr_ld (w_ld), |
| 500 | .csr_data (csrbus_wr_data[2]), |
| 501 | .rw_alias (1'b0), |
| 502 | .rw1c_alias (rw1c_alias), |
| 503 | .rw1s_alias (rw1s_alias), |
| 504 | .hw_ld (imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set), |
| 505 | .hw_data (1'b1), |
| 506 | .cp (clk), |
| 507 | .q (imu_logged_error_status_reg_csrbus_read_data[2]) |
| 508 | ); |
| 509 | |
| 510 | // bit 3 |
| 511 | csr_sw csr_sw_3 |
| 512 | ( |
| 513 | // synopsys translate_off |
| 514 | .omni_ld (omni_ld), |
| 515 | .omni_data (omni_data[3]), |
| 516 | .omni_rw_alias (1'b0), |
| 517 | .omni_rw1c_alias (omni_rw1c_alias), |
| 518 | .omni_rw1s_alias (omni_rw1s_alias), |
| 519 | // synopsys translate_on |
| 520 | .rst (por_l_active_high), |
| 521 | .rst_val (reset_fatal_mes_not_en_p[0]), |
| 522 | .csr_ld (w_ld), |
| 523 | .csr_data (csrbus_wr_data[3]), |
| 524 | .rw_alias (1'b0), |
| 525 | .rw1c_alias (rw1c_alias), |
| 526 | .rw1s_alias (rw1s_alias), |
| 527 | .hw_ld (imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set), |
| 528 | .hw_data (1'b1), |
| 529 | .cp (clk), |
| 530 | .q (imu_logged_error_status_reg_csrbus_read_data[3]) |
| 531 | ); |
| 532 | |
| 533 | // bit 4 |
| 534 | csr_sw csr_sw_4 |
| 535 | ( |
| 536 | // synopsys translate_off |
| 537 | .omni_ld (omni_ld), |
| 538 | .omni_data (omni_data[4]), |
| 539 | .omni_rw_alias (1'b0), |
| 540 | .omni_rw1c_alias (omni_rw1c_alias), |
| 541 | .omni_rw1s_alias (omni_rw1s_alias), |
| 542 | // synopsys translate_on |
| 543 | .rst (por_l_active_high), |
| 544 | .rst_val (reset_pmpme_mes_not_en_p[0]), |
| 545 | .csr_ld (w_ld), |
| 546 | .csr_data (csrbus_wr_data[4]), |
| 547 | .rw_alias (1'b0), |
| 548 | .rw1c_alias (rw1c_alias), |
| 549 | .rw1s_alias (rw1s_alias), |
| 550 | .hw_ld (imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set), |
| 551 | .hw_data (1'b1), |
| 552 | .cp (clk), |
| 553 | .q (imu_logged_error_status_reg_csrbus_read_data[4]) |
| 554 | ); |
| 555 | |
| 556 | // bit 5 |
| 557 | csr_sw csr_sw_5 |
| 558 | ( |
| 559 | // synopsys translate_off |
| 560 | .omni_ld (omni_ld), |
| 561 | .omni_data (omni_data[5]), |
| 562 | .omni_rw_alias (1'b0), |
| 563 | .omni_rw1c_alias (omni_rw1c_alias), |
| 564 | .omni_rw1s_alias (omni_rw1s_alias), |
| 565 | // synopsys translate_on |
| 566 | .rst (por_l_active_high), |
| 567 | .rst_val (reset_pmeack_mes_not_en_p[0]), |
| 568 | .csr_ld (w_ld), |
| 569 | .csr_data (csrbus_wr_data[5]), |
| 570 | .rw_alias (1'b0), |
| 571 | .rw1c_alias (rw1c_alias), |
| 572 | .rw1s_alias (rw1s_alias), |
| 573 | .hw_ld (imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set), |
| 574 | .hw_data (1'b1), |
| 575 | .cp (clk), |
| 576 | .q (imu_logged_error_status_reg_csrbus_read_data[5]) |
| 577 | ); |
| 578 | |
| 579 | // bit 6 |
| 580 | csr_sw csr_sw_6 |
| 581 | ( |
| 582 | // synopsys translate_off |
| 583 | .omni_ld (omni_ld), |
| 584 | .omni_data (omni_data[6]), |
| 585 | .omni_rw_alias (1'b0), |
| 586 | .omni_rw1c_alias (omni_rw1c_alias), |
| 587 | .omni_rw1s_alias (omni_rw1s_alias), |
| 588 | // synopsys translate_on |
| 589 | .rst (por_l_active_high), |
| 590 | .rst_val (reset_msi_par_err_p[0]), |
| 591 | .csr_ld (w_ld), |
| 592 | .csr_data (csrbus_wr_data[6]), |
| 593 | .rw_alias (1'b0), |
| 594 | .rw1c_alias (rw1c_alias), |
| 595 | .rw1s_alias (rw1s_alias), |
| 596 | .hw_ld (imu_logged_error_status_reg_msi_par_err_p_hw_set), |
| 597 | .hw_data (1'b1), |
| 598 | .cp (clk), |
| 599 | .q (imu_logged_error_status_reg_csrbus_read_data[6]) |
| 600 | ); |
| 601 | |
| 602 | // bit 7 |
| 603 | csr_sw csr_sw_7 |
| 604 | ( |
| 605 | // synopsys translate_off |
| 606 | .omni_ld (omni_ld), |
| 607 | .omni_data (omni_data[7]), |
| 608 | .omni_rw_alias (1'b0), |
| 609 | .omni_rw1c_alias (omni_rw1c_alias), |
| 610 | .omni_rw1s_alias (omni_rw1s_alias), |
| 611 | // synopsys translate_on |
| 612 | .rst (por_l_active_high), |
| 613 | .rst_val (reset_msi_mal_err_p[0]), |
| 614 | .csr_ld (w_ld), |
| 615 | .csr_data (csrbus_wr_data[7]), |
| 616 | .rw_alias (1'b0), |
| 617 | .rw1c_alias (rw1c_alias), |
| 618 | .rw1s_alias (rw1s_alias), |
| 619 | .hw_ld (imu_logged_error_status_reg_msi_mal_err_p_hw_set), |
| 620 | .hw_data (1'b1), |
| 621 | .cp (clk), |
| 622 | .q (imu_logged_error_status_reg_csrbus_read_data[7]) |
| 623 | ); |
| 624 | |
| 625 | // bit 8 |
| 626 | csr_sw csr_sw_8 |
| 627 | ( |
| 628 | // synopsys translate_off |
| 629 | .omni_ld (omni_ld), |
| 630 | .omni_data (omni_data[8]), |
| 631 | .omni_rw_alias (1'b0), |
| 632 | .omni_rw1c_alias (omni_rw1c_alias), |
| 633 | .omni_rw1s_alias (omni_rw1s_alias), |
| 634 | // synopsys translate_on |
| 635 | .rst (por_l_active_high), |
| 636 | .rst_val (reset_eq_not_en_p[0]), |
| 637 | .csr_ld (w_ld), |
| 638 | .csr_data (csrbus_wr_data[8]), |
| 639 | .rw_alias (1'b0), |
| 640 | .rw1c_alias (rw1c_alias), |
| 641 | .rw1s_alias (rw1s_alias), |
| 642 | .hw_ld (imu_logged_error_status_reg_eq_not_en_p_hw_set), |
| 643 | .hw_data (1'b1), |
| 644 | .cp (clk), |
| 645 | .q (imu_logged_error_status_reg_csrbus_read_data[8]) |
| 646 | ); |
| 647 | |
| 648 | // bit 9 |
| 649 | csr_sw csr_sw_9 |
| 650 | ( |
| 651 | // synopsys translate_off |
| 652 | .omni_ld (omni_ld), |
| 653 | .omni_data (omni_data[9]), |
| 654 | .omni_rw_alias (1'b0), |
| 655 | .omni_rw1c_alias (omni_rw1c_alias), |
| 656 | .omni_rw1s_alias (omni_rw1s_alias), |
| 657 | // synopsys translate_on |
| 658 | .rst (por_l_active_high), |
| 659 | .rst_val (reset_eq_over_p[0]), |
| 660 | .csr_ld (w_ld), |
| 661 | .csr_data (csrbus_wr_data[9]), |
| 662 | .rw_alias (1'b0), |
| 663 | .rw1c_alias (rw1c_alias), |
| 664 | .rw1s_alias (rw1s_alias), |
| 665 | .hw_ld (imu_logged_error_status_reg_eq_over_p_hw_set), |
| 666 | .hw_data (1'b1), |
| 667 | .cp (clk), |
| 668 | .q (imu_logged_error_status_reg_csrbus_read_data[9]) |
| 669 | ); |
| 670 | |
| 671 | // bit 10 |
| 672 | csr_sw csr_sw_10 |
| 673 | ( |
| 674 | // synopsys translate_off |
| 675 | .omni_ld (omni_ld), |
| 676 | .omni_data (omni_data[10]), |
| 677 | .omni_rw_alias (1'b0), |
| 678 | .omni_rw1c_alias (omni_rw1c_alias), |
| 679 | .omni_rw1s_alias (omni_rw1s_alias), |
| 680 | // synopsys translate_on |
| 681 | .rst (por_l_active_high), |
| 682 | .rst_val (reset_spare_p[0]), |
| 683 | .csr_ld (w_ld), |
| 684 | .csr_data (csrbus_wr_data[10]), |
| 685 | .rw_alias (1'b0), |
| 686 | .rw1c_alias (rw1c_alias), |
| 687 | .rw1s_alias (rw1s_alias), |
| 688 | .hw_ld (imu_logged_error_status_reg_spare_p_hw_set[0]), |
| 689 | .hw_data (1'b1), |
| 690 | .cp (clk), |
| 691 | .q (imu_logged_error_status_reg_csrbus_read_data[10]) |
| 692 | ); |
| 693 | |
| 694 | // bit 11 |
| 695 | csr_sw csr_sw_11 |
| 696 | ( |
| 697 | // synopsys translate_off |
| 698 | .omni_ld (omni_ld), |
| 699 | .omni_data (omni_data[11]), |
| 700 | .omni_rw_alias (1'b0), |
| 701 | .omni_rw1c_alias (omni_rw1c_alias), |
| 702 | .omni_rw1s_alias (omni_rw1s_alias), |
| 703 | // synopsys translate_on |
| 704 | .rst (por_l_active_high), |
| 705 | .rst_val (reset_spare_p[1]), |
| 706 | .csr_ld (w_ld), |
| 707 | .csr_data (csrbus_wr_data[11]), |
| 708 | .rw_alias (1'b0), |
| 709 | .rw1c_alias (rw1c_alias), |
| 710 | .rw1s_alias (rw1s_alias), |
| 711 | .hw_ld (imu_logged_error_status_reg_spare_p_hw_set[1]), |
| 712 | .hw_data (1'b1), |
| 713 | .cp (clk), |
| 714 | .q (imu_logged_error_status_reg_csrbus_read_data[11]) |
| 715 | ); |
| 716 | |
| 717 | // bit 12 |
| 718 | csr_sw csr_sw_12 |
| 719 | ( |
| 720 | // synopsys translate_off |
| 721 | .omni_ld (omni_ld), |
| 722 | .omni_data (omni_data[12]), |
| 723 | .omni_rw_alias (1'b0), |
| 724 | .omni_rw1c_alias (omni_rw1c_alias), |
| 725 | .omni_rw1s_alias (omni_rw1s_alias), |
| 726 | // synopsys translate_on |
| 727 | .rst (por_l_active_high), |
| 728 | .rst_val (reset_spare_p[2]), |
| 729 | .csr_ld (w_ld), |
| 730 | .csr_data (csrbus_wr_data[12]), |
| 731 | .rw_alias (1'b0), |
| 732 | .rw1c_alias (rw1c_alias), |
| 733 | .rw1s_alias (rw1s_alias), |
| 734 | .hw_ld (imu_logged_error_status_reg_spare_p_hw_set[2]), |
| 735 | .hw_data (1'b1), |
| 736 | .cp (clk), |
| 737 | .q (imu_logged_error_status_reg_csrbus_read_data[12]) |
| 738 | ); |
| 739 | |
| 740 | // bit 13 |
| 741 | csr_sw csr_sw_13 |
| 742 | ( |
| 743 | // synopsys translate_off |
| 744 | .omni_ld (omni_ld), |
| 745 | .omni_data (omni_data[13]), |
| 746 | .omni_rw_alias (1'b0), |
| 747 | .omni_rw1c_alias (omni_rw1c_alias), |
| 748 | .omni_rw1s_alias (omni_rw1s_alias), |
| 749 | // synopsys translate_on |
| 750 | .rst (por_l_active_high), |
| 751 | .rst_val (reset_spare_p[3]), |
| 752 | .csr_ld (w_ld), |
| 753 | .csr_data (csrbus_wr_data[13]), |
| 754 | .rw_alias (1'b0), |
| 755 | .rw1c_alias (rw1c_alias), |
| 756 | .rw1s_alias (rw1s_alias), |
| 757 | .hw_ld (imu_logged_error_status_reg_spare_p_hw_set[3]), |
| 758 | .hw_data (1'b1), |
| 759 | .cp (clk), |
| 760 | .q (imu_logged_error_status_reg_csrbus_read_data[13]) |
| 761 | ); |
| 762 | |
| 763 | // bit 14 |
| 764 | csr_sw csr_sw_14 |
| 765 | ( |
| 766 | // synopsys translate_off |
| 767 | .omni_ld (omni_ld), |
| 768 | .omni_data (omni_data[14]), |
| 769 | .omni_rw_alias (1'b0), |
| 770 | .omni_rw1c_alias (omni_rw1c_alias), |
| 771 | .omni_rw1s_alias (omni_rw1s_alias), |
| 772 | // synopsys translate_on |
| 773 | .rst (por_l_active_high), |
| 774 | .rst_val (reset_spare_p[4]), |
| 775 | .csr_ld (w_ld), |
| 776 | .csr_data (csrbus_wr_data[14]), |
| 777 | .rw_alias (1'b0), |
| 778 | .rw1c_alias (rw1c_alias), |
| 779 | .rw1s_alias (rw1s_alias), |
| 780 | .hw_ld (imu_logged_error_status_reg_spare_p_hw_set[4]), |
| 781 | .hw_data (1'b1), |
| 782 | .cp (clk), |
| 783 | .q (imu_logged_error_status_reg_csrbus_read_data[14]) |
| 784 | ); |
| 785 | |
| 786 | assign imu_logged_error_status_reg_csrbus_read_data[15] = 1'b0; // bit 15 |
| 787 | assign imu_logged_error_status_reg_csrbus_read_data[16] = 1'b0; // bit 16 |
| 788 | assign imu_logged_error_status_reg_csrbus_read_data[17] = 1'b0; // bit 17 |
| 789 | assign imu_logged_error_status_reg_csrbus_read_data[18] = 1'b0; // bit 18 |
| 790 | assign imu_logged_error_status_reg_csrbus_read_data[19] = 1'b0; // bit 19 |
| 791 | assign imu_logged_error_status_reg_csrbus_read_data[20] = 1'b0; // bit 20 |
| 792 | assign imu_logged_error_status_reg_csrbus_read_data[21] = 1'b0; // bit 21 |
| 793 | assign imu_logged_error_status_reg_csrbus_read_data[22] = 1'b0; // bit 22 |
| 794 | assign imu_logged_error_status_reg_csrbus_read_data[23] = 1'b0; // bit 23 |
| 795 | assign imu_logged_error_status_reg_csrbus_read_data[24] = 1'b0; // bit 24 |
| 796 | assign imu_logged_error_status_reg_csrbus_read_data[25] = 1'b0; // bit 25 |
| 797 | assign imu_logged_error_status_reg_csrbus_read_data[26] = 1'b0; // bit 26 |
| 798 | assign imu_logged_error_status_reg_csrbus_read_data[27] = 1'b0; // bit 27 |
| 799 | assign imu_logged_error_status_reg_csrbus_read_data[28] = 1'b0; // bit 28 |
| 800 | assign imu_logged_error_status_reg_csrbus_read_data[29] = 1'b0; // bit 29 |
| 801 | assign imu_logged_error_status_reg_csrbus_read_data[30] = 1'b0; // bit 30 |
| 802 | assign imu_logged_error_status_reg_csrbus_read_data[31] = 1'b0; // bit 31 |
| 803 | // bit 32 |
| 804 | csr_sw csr_sw_32 |
| 805 | ( |
| 806 | // synopsys translate_off |
| 807 | .omni_ld (omni_ld), |
| 808 | .omni_data (omni_data[32]), |
| 809 | .omni_rw_alias (1'b0), |
| 810 | .omni_rw1c_alias (omni_rw1c_alias), |
| 811 | .omni_rw1s_alias (omni_rw1s_alias), |
| 812 | // synopsys translate_on |
| 813 | .rst (por_l_active_high), |
| 814 | .rst_val (reset_msi_not_en_s[0]), |
| 815 | .csr_ld (w_ld), |
| 816 | .csr_data (csrbus_wr_data[32]), |
| 817 | .rw_alias (1'b0), |
| 818 | .rw1c_alias (rw1c_alias), |
| 819 | .rw1s_alias (rw1s_alias), |
| 820 | .hw_ld (imu_logged_error_status_reg_msi_not_en_s_hw_set), |
| 821 | .hw_data (1'b1), |
| 822 | .cp (clk), |
| 823 | .q (imu_logged_error_status_reg_csrbus_read_data[32]) |
| 824 | ); |
| 825 | |
| 826 | // bit 33 |
| 827 | csr_sw csr_sw_33 |
| 828 | ( |
| 829 | // synopsys translate_off |
| 830 | .omni_ld (omni_ld), |
| 831 | .omni_data (omni_data[33]), |
| 832 | .omni_rw_alias (1'b0), |
| 833 | .omni_rw1c_alias (omni_rw1c_alias), |
| 834 | .omni_rw1s_alias (omni_rw1s_alias), |
| 835 | // synopsys translate_on |
| 836 | .rst (por_l_active_high), |
| 837 | .rst_val (reset_cor_mes_not_en_s[0]), |
| 838 | .csr_ld (w_ld), |
| 839 | .csr_data (csrbus_wr_data[33]), |
| 840 | .rw_alias (1'b0), |
| 841 | .rw1c_alias (rw1c_alias), |
| 842 | .rw1s_alias (rw1s_alias), |
| 843 | .hw_ld (imu_logged_error_status_reg_cor_mes_not_en_s_hw_set), |
| 844 | .hw_data (1'b1), |
| 845 | .cp (clk), |
| 846 | .q (imu_logged_error_status_reg_csrbus_read_data[33]) |
| 847 | ); |
| 848 | |
| 849 | // bit 34 |
| 850 | csr_sw csr_sw_34 |
| 851 | ( |
| 852 | // synopsys translate_off |
| 853 | .omni_ld (omni_ld), |
| 854 | .omni_data (omni_data[34]), |
| 855 | .omni_rw_alias (1'b0), |
| 856 | .omni_rw1c_alias (omni_rw1c_alias), |
| 857 | .omni_rw1s_alias (omni_rw1s_alias), |
| 858 | // synopsys translate_on |
| 859 | .rst (por_l_active_high), |
| 860 | .rst_val (reset_nonfatal_mes_not_en_s[0]), |
| 861 | .csr_ld (w_ld), |
| 862 | .csr_data (csrbus_wr_data[34]), |
| 863 | .rw_alias (1'b0), |
| 864 | .rw1c_alias (rw1c_alias), |
| 865 | .rw1s_alias (rw1s_alias), |
| 866 | .hw_ld (imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set), |
| 867 | .hw_data (1'b1), |
| 868 | .cp (clk), |
| 869 | .q (imu_logged_error_status_reg_csrbus_read_data[34]) |
| 870 | ); |
| 871 | |
| 872 | // bit 35 |
| 873 | csr_sw csr_sw_35 |
| 874 | ( |
| 875 | // synopsys translate_off |
| 876 | .omni_ld (omni_ld), |
| 877 | .omni_data (omni_data[35]), |
| 878 | .omni_rw_alias (1'b0), |
| 879 | .omni_rw1c_alias (omni_rw1c_alias), |
| 880 | .omni_rw1s_alias (omni_rw1s_alias), |
| 881 | // synopsys translate_on |
| 882 | .rst (por_l_active_high), |
| 883 | .rst_val (reset_fatal_mes_not_en_s[0]), |
| 884 | .csr_ld (w_ld), |
| 885 | .csr_data (csrbus_wr_data[35]), |
| 886 | .rw_alias (1'b0), |
| 887 | .rw1c_alias (rw1c_alias), |
| 888 | .rw1s_alias (rw1s_alias), |
| 889 | .hw_ld (imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set), |
| 890 | .hw_data (1'b1), |
| 891 | .cp (clk), |
| 892 | .q (imu_logged_error_status_reg_csrbus_read_data[35]) |
| 893 | ); |
| 894 | |
| 895 | // bit 36 |
| 896 | csr_sw csr_sw_36 |
| 897 | ( |
| 898 | // synopsys translate_off |
| 899 | .omni_ld (omni_ld), |
| 900 | .omni_data (omni_data[36]), |
| 901 | .omni_rw_alias (1'b0), |
| 902 | .omni_rw1c_alias (omni_rw1c_alias), |
| 903 | .omni_rw1s_alias (omni_rw1s_alias), |
| 904 | // synopsys translate_on |
| 905 | .rst (por_l_active_high), |
| 906 | .rst_val (reset_pmpme_mes_not_en_s[0]), |
| 907 | .csr_ld (w_ld), |
| 908 | .csr_data (csrbus_wr_data[36]), |
| 909 | .rw_alias (1'b0), |
| 910 | .rw1c_alias (rw1c_alias), |
| 911 | .rw1s_alias (rw1s_alias), |
| 912 | .hw_ld (imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set), |
| 913 | .hw_data (1'b1), |
| 914 | .cp (clk), |
| 915 | .q (imu_logged_error_status_reg_csrbus_read_data[36]) |
| 916 | ); |
| 917 | |
| 918 | // bit 37 |
| 919 | csr_sw csr_sw_37 |
| 920 | ( |
| 921 | // synopsys translate_off |
| 922 | .omni_ld (omni_ld), |
| 923 | .omni_data (omni_data[37]), |
| 924 | .omni_rw_alias (1'b0), |
| 925 | .omni_rw1c_alias (omni_rw1c_alias), |
| 926 | .omni_rw1s_alias (omni_rw1s_alias), |
| 927 | // synopsys translate_on |
| 928 | .rst (por_l_active_high), |
| 929 | .rst_val (reset_pmeack_mes_not_en_s[0]), |
| 930 | .csr_ld (w_ld), |
| 931 | .csr_data (csrbus_wr_data[37]), |
| 932 | .rw_alias (1'b0), |
| 933 | .rw1c_alias (rw1c_alias), |
| 934 | .rw1s_alias (rw1s_alias), |
| 935 | .hw_ld (imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set), |
| 936 | .hw_data (1'b1), |
| 937 | .cp (clk), |
| 938 | .q (imu_logged_error_status_reg_csrbus_read_data[37]) |
| 939 | ); |
| 940 | |
| 941 | // bit 38 |
| 942 | csr_sw csr_sw_38 |
| 943 | ( |
| 944 | // synopsys translate_off |
| 945 | .omni_ld (omni_ld), |
| 946 | .omni_data (omni_data[38]), |
| 947 | .omni_rw_alias (1'b0), |
| 948 | .omni_rw1c_alias (omni_rw1c_alias), |
| 949 | .omni_rw1s_alias (omni_rw1s_alias), |
| 950 | // synopsys translate_on |
| 951 | .rst (por_l_active_high), |
| 952 | .rst_val (reset_msi_par_err_s[0]), |
| 953 | .csr_ld (w_ld), |
| 954 | .csr_data (csrbus_wr_data[38]), |
| 955 | .rw_alias (1'b0), |
| 956 | .rw1c_alias (rw1c_alias), |
| 957 | .rw1s_alias (rw1s_alias), |
| 958 | .hw_ld (imu_logged_error_status_reg_msi_par_err_s_hw_set), |
| 959 | .hw_data (1'b1), |
| 960 | .cp (clk), |
| 961 | .q (imu_logged_error_status_reg_csrbus_read_data[38]) |
| 962 | ); |
| 963 | |
| 964 | // bit 39 |
| 965 | csr_sw csr_sw_39 |
| 966 | ( |
| 967 | // synopsys translate_off |
| 968 | .omni_ld (omni_ld), |
| 969 | .omni_data (omni_data[39]), |
| 970 | .omni_rw_alias (1'b0), |
| 971 | .omni_rw1c_alias (omni_rw1c_alias), |
| 972 | .omni_rw1s_alias (omni_rw1s_alias), |
| 973 | // synopsys translate_on |
| 974 | .rst (por_l_active_high), |
| 975 | .rst_val (reset_msi_mal_err_s[0]), |
| 976 | .csr_ld (w_ld), |
| 977 | .csr_data (csrbus_wr_data[39]), |
| 978 | .rw_alias (1'b0), |
| 979 | .rw1c_alias (rw1c_alias), |
| 980 | .rw1s_alias (rw1s_alias), |
| 981 | .hw_ld (imu_logged_error_status_reg_msi_mal_err_s_hw_set), |
| 982 | .hw_data (1'b1), |
| 983 | .cp (clk), |
| 984 | .q (imu_logged_error_status_reg_csrbus_read_data[39]) |
| 985 | ); |
| 986 | |
| 987 | // bit 40 |
| 988 | csr_sw csr_sw_40 |
| 989 | ( |
| 990 | // synopsys translate_off |
| 991 | .omni_ld (omni_ld), |
| 992 | .omni_data (omni_data[40]), |
| 993 | .omni_rw_alias (1'b0), |
| 994 | .omni_rw1c_alias (omni_rw1c_alias), |
| 995 | .omni_rw1s_alias (omni_rw1s_alias), |
| 996 | // synopsys translate_on |
| 997 | .rst (por_l_active_high), |
| 998 | .rst_val (reset_eq_not_en_s[0]), |
| 999 | .csr_ld (w_ld), |
| 1000 | .csr_data (csrbus_wr_data[40]), |
| 1001 | .rw_alias (1'b0), |
| 1002 | .rw1c_alias (rw1c_alias), |
| 1003 | .rw1s_alias (rw1s_alias), |
| 1004 | .hw_ld (imu_logged_error_status_reg_eq_not_en_s_hw_set), |
| 1005 | .hw_data (1'b1), |
| 1006 | .cp (clk), |
| 1007 | .q (imu_logged_error_status_reg_csrbus_read_data[40]) |
| 1008 | ); |
| 1009 | |
| 1010 | // bit 41 |
| 1011 | csr_sw csr_sw_41 |
| 1012 | ( |
| 1013 | // synopsys translate_off |
| 1014 | .omni_ld (omni_ld), |
| 1015 | .omni_data (omni_data[41]), |
| 1016 | .omni_rw_alias (1'b0), |
| 1017 | .omni_rw1c_alias (omni_rw1c_alias), |
| 1018 | .omni_rw1s_alias (omni_rw1s_alias), |
| 1019 | // synopsys translate_on |
| 1020 | .rst (por_l_active_high), |
| 1021 | .rst_val (reset_eq_over_s[0]), |
| 1022 | .csr_ld (w_ld), |
| 1023 | .csr_data (csrbus_wr_data[41]), |
| 1024 | .rw_alias (1'b0), |
| 1025 | .rw1c_alias (rw1c_alias), |
| 1026 | .rw1s_alias (rw1s_alias), |
| 1027 | .hw_ld (imu_logged_error_status_reg_eq_over_s_hw_set), |
| 1028 | .hw_data (1'b1), |
| 1029 | .cp (clk), |
| 1030 | .q (imu_logged_error_status_reg_csrbus_read_data[41]) |
| 1031 | ); |
| 1032 | |
| 1033 | // bit 42 |
| 1034 | csr_sw csr_sw_42 |
| 1035 | ( |
| 1036 | // synopsys translate_off |
| 1037 | .omni_ld (omni_ld), |
| 1038 | .omni_data (omni_data[42]), |
| 1039 | .omni_rw_alias (1'b0), |
| 1040 | .omni_rw1c_alias (omni_rw1c_alias), |
| 1041 | .omni_rw1s_alias (omni_rw1s_alias), |
| 1042 | // synopsys translate_on |
| 1043 | .rst (por_l_active_high), |
| 1044 | .rst_val (reset_spare_s[0]), |
| 1045 | .csr_ld (w_ld), |
| 1046 | .csr_data (csrbus_wr_data[42]), |
| 1047 | .rw_alias (1'b0), |
| 1048 | .rw1c_alias (rw1c_alias), |
| 1049 | .rw1s_alias (rw1s_alias), |
| 1050 | .hw_ld (imu_logged_error_status_reg_spare_s_hw_set[0]), |
| 1051 | .hw_data (1'b1), |
| 1052 | .cp (clk), |
| 1053 | .q (imu_logged_error_status_reg_csrbus_read_data[42]) |
| 1054 | ); |
| 1055 | |
| 1056 | // bit 43 |
| 1057 | csr_sw csr_sw_43 |
| 1058 | ( |
| 1059 | // synopsys translate_off |
| 1060 | .omni_ld (omni_ld), |
| 1061 | .omni_data (omni_data[43]), |
| 1062 | .omni_rw_alias (1'b0), |
| 1063 | .omni_rw1c_alias (omni_rw1c_alias), |
| 1064 | .omni_rw1s_alias (omni_rw1s_alias), |
| 1065 | // synopsys translate_on |
| 1066 | .rst (por_l_active_high), |
| 1067 | .rst_val (reset_spare_s[1]), |
| 1068 | .csr_ld (w_ld), |
| 1069 | .csr_data (csrbus_wr_data[43]), |
| 1070 | .rw_alias (1'b0), |
| 1071 | .rw1c_alias (rw1c_alias), |
| 1072 | .rw1s_alias (rw1s_alias), |
| 1073 | .hw_ld (imu_logged_error_status_reg_spare_s_hw_set[1]), |
| 1074 | .hw_data (1'b1), |
| 1075 | .cp (clk), |
| 1076 | .q (imu_logged_error_status_reg_csrbus_read_data[43]) |
| 1077 | ); |
| 1078 | |
| 1079 | // bit 44 |
| 1080 | csr_sw csr_sw_44 |
| 1081 | ( |
| 1082 | // synopsys translate_off |
| 1083 | .omni_ld (omni_ld), |
| 1084 | .omni_data (omni_data[44]), |
| 1085 | .omni_rw_alias (1'b0), |
| 1086 | .omni_rw1c_alias (omni_rw1c_alias), |
| 1087 | .omni_rw1s_alias (omni_rw1s_alias), |
| 1088 | // synopsys translate_on |
| 1089 | .rst (por_l_active_high), |
| 1090 | .rst_val (reset_spare_s[2]), |
| 1091 | .csr_ld (w_ld), |
| 1092 | .csr_data (csrbus_wr_data[44]), |
| 1093 | .rw_alias (1'b0), |
| 1094 | .rw1c_alias (rw1c_alias), |
| 1095 | .rw1s_alias (rw1s_alias), |
| 1096 | .hw_ld (imu_logged_error_status_reg_spare_s_hw_set[2]), |
| 1097 | .hw_data (1'b1), |
| 1098 | .cp (clk), |
| 1099 | .q (imu_logged_error_status_reg_csrbus_read_data[44]) |
| 1100 | ); |
| 1101 | |
| 1102 | // bit 45 |
| 1103 | csr_sw csr_sw_45 |
| 1104 | ( |
| 1105 | // synopsys translate_off |
| 1106 | .omni_ld (omni_ld), |
| 1107 | .omni_data (omni_data[45]), |
| 1108 | .omni_rw_alias (1'b0), |
| 1109 | .omni_rw1c_alias (omni_rw1c_alias), |
| 1110 | .omni_rw1s_alias (omni_rw1s_alias), |
| 1111 | // synopsys translate_on |
| 1112 | .rst (por_l_active_high), |
| 1113 | .rst_val (reset_spare_s[3]), |
| 1114 | .csr_ld (w_ld), |
| 1115 | .csr_data (csrbus_wr_data[45]), |
| 1116 | .rw_alias (1'b0), |
| 1117 | .rw1c_alias (rw1c_alias), |
| 1118 | .rw1s_alias (rw1s_alias), |
| 1119 | .hw_ld (imu_logged_error_status_reg_spare_s_hw_set[3]), |
| 1120 | .hw_data (1'b1), |
| 1121 | .cp (clk), |
| 1122 | .q (imu_logged_error_status_reg_csrbus_read_data[45]) |
| 1123 | ); |
| 1124 | |
| 1125 | // bit 46 |
| 1126 | csr_sw csr_sw_46 |
| 1127 | ( |
| 1128 | // synopsys translate_off |
| 1129 | .omni_ld (omni_ld), |
| 1130 | .omni_data (omni_data[46]), |
| 1131 | .omni_rw_alias (1'b0), |
| 1132 | .omni_rw1c_alias (omni_rw1c_alias), |
| 1133 | .omni_rw1s_alias (omni_rw1s_alias), |
| 1134 | // synopsys translate_on |
| 1135 | .rst (por_l_active_high), |
| 1136 | .rst_val (reset_spare_s[4]), |
| 1137 | .csr_ld (w_ld), |
| 1138 | .csr_data (csrbus_wr_data[46]), |
| 1139 | .rw_alias (1'b0), |
| 1140 | .rw1c_alias (rw1c_alias), |
| 1141 | .rw1s_alias (rw1s_alias), |
| 1142 | .hw_ld (imu_logged_error_status_reg_spare_s_hw_set[4]), |
| 1143 | .hw_data (1'b1), |
| 1144 | .cp (clk), |
| 1145 | .q (imu_logged_error_status_reg_csrbus_read_data[46]) |
| 1146 | ); |
| 1147 | |
| 1148 | assign imu_logged_error_status_reg_csrbus_read_data[47] = 1'b0; // bit 47 |
| 1149 | assign imu_logged_error_status_reg_csrbus_read_data[48] = 1'b0; // bit 48 |
| 1150 | assign imu_logged_error_status_reg_csrbus_read_data[49] = 1'b0; // bit 49 |
| 1151 | assign imu_logged_error_status_reg_csrbus_read_data[50] = 1'b0; // bit 50 |
| 1152 | assign imu_logged_error_status_reg_csrbus_read_data[51] = 1'b0; // bit 51 |
| 1153 | assign imu_logged_error_status_reg_csrbus_read_data[52] = 1'b0; // bit 52 |
| 1154 | assign imu_logged_error_status_reg_csrbus_read_data[53] = 1'b0; // bit 53 |
| 1155 | assign imu_logged_error_status_reg_csrbus_read_data[54] = 1'b0; // bit 54 |
| 1156 | assign imu_logged_error_status_reg_csrbus_read_data[55] = 1'b0; // bit 55 |
| 1157 | assign imu_logged_error_status_reg_csrbus_read_data[56] = 1'b0; // bit 56 |
| 1158 | assign imu_logged_error_status_reg_csrbus_read_data[57] = 1'b0; // bit 57 |
| 1159 | assign imu_logged_error_status_reg_csrbus_read_data[58] = 1'b0; // bit 58 |
| 1160 | assign imu_logged_error_status_reg_csrbus_read_data[59] = 1'b0; // bit 59 |
| 1161 | assign imu_logged_error_status_reg_csrbus_read_data[60] = 1'b0; // bit 60 |
| 1162 | assign imu_logged_error_status_reg_csrbus_read_data[61] = 1'b0; // bit 61 |
| 1163 | assign imu_logged_error_status_reg_csrbus_read_data[62] = 1'b0; // bit 62 |
| 1164 | assign imu_logged_error_status_reg_csrbus_read_data[63] = 1'b0; // bit 63 |
| 1165 | |
| 1166 | endmodule // dmu_imu_ics_csr_imu_logged_error_status_reg_entry |