// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_imu_ics_csr_imu_logged_error_status_reg_entry.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
// available with the language indicating that GPLv2 or any later version
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// otherwise unspecified.
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// CA 95054 USA or visit www.sun.com if you need additional information or
// ========== Copyright Header End ============================================
module dmu_imu_ics_csr_imu_logged_error_status_reg_entry
// synopsys translate_off
imu_logged_error_status_reg_csrbus_read_data,
imu_logged_error_status_reg_spare_s_hw_set,
imu_logged_error_status_reg_eq_over_s_hw_set,
imu_logged_error_status_reg_eq_not_en_s_hw_set,
imu_logged_error_status_reg_msi_mal_err_s_hw_set,
imu_logged_error_status_reg_msi_par_err_s_hw_set,
imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set,
imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set,
imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set,
imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set,
imu_logged_error_status_reg_cor_mes_not_en_s_hw_set,
imu_logged_error_status_reg_msi_not_en_s_hw_set,
imu_logged_error_status_reg_spare_p_hw_set,
imu_logged_error_status_reg_eq_over_p_hw_set,
imu_logged_error_status_reg_eq_not_en_p_hw_set,
imu_logged_error_status_reg_msi_mal_err_p_hw_set,
imu_logged_error_status_reg_msi_par_err_p_hw_set,
imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set,
imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set,
imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set,
imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set,
imu_logged_error_status_reg_cor_mes_not_en_p_hw_set,
imu_logged_error_status_reg_msi_not_en_p_hw_set
//====================================================================
//====================================================================
// synopsys translate_off
input omni_ld; // Omni load
// vlint flag_input_port_not_connected off
input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH - 1:0] omni_data;
// vlint flag_input_port_not_connected on
input omni_rw1c_alias; // Omni load type: write-one-to-clear
input omni_rw1s_alias; // Omni load type: write-one-to-set
input clk; // Clock signal
input por_l; // Reset signal
// vlint flag_input_port_not_connected off
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_input_port_not_connected on
input rw1c_alias; // SW load type: write-one-to-clear
input rw1s_alias; // SW load type: write-one-to-set
output [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH-1:0]
imu_logged_error_status_reg_csrbus_read_data; // SW read data
input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC]
imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_spare_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_eq_over_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal
// imu_logged_error_status_reg_eq_not_en_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_mal_err_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_par_err_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_pmeack_mes_not_en_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_pmpme_mes_not_en_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_fatal_mes_not_en_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware
// imu_logged_error_status_reg_nonfatal_mes_not_en_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_cor_mes_not_en_s.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_not_en_s.
// imu_logged_error_status_reg
input [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC]
imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_spare_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_eq_over_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal
// imu_logged_error_status_reg_eq_not_en_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_mal_err_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_par_err_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_pmeack_mes_not_en_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_pmpme_mes_not_en_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_fatal_mes_not_en_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware
// imu_logged_error_status_reg_nonfatal_mes_not_en_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_cor_mes_not_en_p.
// imu_logged_error_status_reg
input imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_not_en_p.
// imu_logged_error_status_reg
//====================================================================
//====================================================================
// synopsys translate_off
wire omni_ld; // Omni load
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH - 1:0] omni_data;
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire omni_rw1c_alias; // Omni load type: write-one-to-clear
wire omni_rw1s_alias; // Omni load type: write-one-to-set
wire clk; // Clock signal
wire por_l; // Reset signal
// vlint flag_dangling_net_within_module off
// vlint flag_net_has_no_load off
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
// vlint flag_dangling_net_within_module on
// vlint flag_net_has_no_load on
wire rw1c_alias; // SW load type: write-one-to-clear
wire rw1s_alias; // SW load type: write-one-to-set
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_WIDTH-1:0]
imu_logged_error_status_reg_csrbus_read_data; // SW read data
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_S_INT_SLC]
imu_logged_error_status_reg_spare_s_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_spare_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_eq_over_s_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_eq_over_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_eq_not_en_s_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_eq_not_en_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_msi_mal_err_s_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_mal_err_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_msi_par_err_s_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_par_err_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_pmeack_mes_not_en_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_pmpme_mes_not_en_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_fatal_mes_not_en_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_nonfatal_mes_not_en_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_cor_mes_not_en_s_hw_set; // Hardware set
// imu_logged_error_status_reg_cor_mes_not_en_s.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_msi_not_en_s_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_not_en_s.
// imu_logged_error_status_reg
wire [`FIRE_DLC_IMU_ICS_CSR_IMU_LOGGED_ERROR_STATUS_REG_RW1C_ALIAS_SPARE_P_INT_SLC]
imu_logged_error_status_reg_spare_p_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_spare_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_eq_over_p_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_eq_over_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_eq_not_en_p_hw_set; // Hardware set signal for
// imu_logged_error_status_reg_eq_not_en_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_msi_mal_err_p_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_mal_err_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_msi_par_err_p_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_par_err_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_pmeack_mes_not_en_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_pmpme_mes_not_en_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_fatal_mes_not_en_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_nonfatal_mes_not_en_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_cor_mes_not_en_p_hw_set; // Hardware set
// imu_logged_error_status_reg_cor_mes_not_en_p.
// imu_logged_error_status_reg
wire imu_logged_error_status_reg_msi_not_en_p_hw_set; // Hardware set signal
// imu_logged_error_status_reg_msi_not_en_p.
// imu_logged_error_status_reg
//====================================================================
//====================================================================
wire [4:0] reset_spare_s = 5'h0;
wire [0:0] reset_eq_over_s = 1'h0;
wire [0:0] reset_eq_not_en_s = 1'h0;
wire [0:0] reset_msi_mal_err_s = 1'h0;
wire [0:0] reset_msi_par_err_s = 1'h0;
wire [0:0] reset_pmeack_mes_not_en_s = 1'h0;
wire [0:0] reset_pmpme_mes_not_en_s = 1'h0;
wire [0:0] reset_fatal_mes_not_en_s = 1'h0;
wire [0:0] reset_nonfatal_mes_not_en_s = 1'h0;
wire [0:0] reset_cor_mes_not_en_s = 1'h0;
wire [0:0] reset_msi_not_en_s = 1'h0;
wire [4:0] reset_spare_p = 5'h0;
wire [0:0] reset_eq_over_p = 1'h0;
wire [0:0] reset_eq_not_en_p = 1'h0;
wire [0:0] reset_msi_mal_err_p = 1'h0;
wire [0:0] reset_msi_par_err_p = 1'h0;
wire [0:0] reset_pmeack_mes_not_en_p = 1'h0;
wire [0:0] reset_pmpme_mes_not_en_p = 1'h0;
wire [0:0] reset_fatal_mes_not_en_p = 1'h0;
wire [0:0] reset_nonfatal_mes_not_en_p = 1'h0;
wire [0:0] reset_cor_mes_not_en_p = 1'h0;
wire [0:0] reset_msi_not_en_p = 1'h0;
//----- Active high reset wires
wire por_l_active_high = ~por_l;
//====================================================
// Instantiation of flops
//====================================================
// synopsys translate_off
.omni_data (omni_data[0]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_msi_not_en_p[0]),
.csr_data (csrbus_wr_data[0]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_msi_not_en_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[0])
// synopsys translate_off
.omni_data (omni_data[1]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_cor_mes_not_en_p[0]),
.csr_data (csrbus_wr_data[1]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_cor_mes_not_en_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[1])
// synopsys translate_off
.omni_data (omni_data[2]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_nonfatal_mes_not_en_p[0]),
.csr_data (csrbus_wr_data[2]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_nonfatal_mes_not_en_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[2])
// synopsys translate_off
.omni_data (omni_data[3]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_fatal_mes_not_en_p[0]),
.csr_data (csrbus_wr_data[3]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_fatal_mes_not_en_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[3])
// synopsys translate_off
.omni_data (omni_data[4]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_pmpme_mes_not_en_p[0]),
.csr_data (csrbus_wr_data[4]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_pmpme_mes_not_en_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[4])
// synopsys translate_off
.omni_data (omni_data[5]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_pmeack_mes_not_en_p[0]),
.csr_data (csrbus_wr_data[5]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_pmeack_mes_not_en_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[5])
// synopsys translate_off
.omni_data (omni_data[6]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_msi_par_err_p[0]),
.csr_data (csrbus_wr_data[6]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_msi_par_err_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[6])
// synopsys translate_off
.omni_data (omni_data[7]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_msi_mal_err_p[0]),
.csr_data (csrbus_wr_data[7]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_msi_mal_err_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[7])
// synopsys translate_off
.omni_data (omni_data[8]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_eq_not_en_p[0]),
.csr_data (csrbus_wr_data[8]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_eq_not_en_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[8])
// synopsys translate_off
.omni_data (omni_data[9]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_eq_over_p[0]),
.csr_data (csrbus_wr_data[9]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_eq_over_p_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[9])
// synopsys translate_off
.omni_data (omni_data[10]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_p[0]),
.csr_data (csrbus_wr_data[10]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_p_hw_set[0]),
.q (imu_logged_error_status_reg_csrbus_read_data[10])
// synopsys translate_off
.omni_data (omni_data[11]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_p[1]),
.csr_data (csrbus_wr_data[11]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_p_hw_set[1]),
.q (imu_logged_error_status_reg_csrbus_read_data[11])
// synopsys translate_off
.omni_data (omni_data[12]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_p[2]),
.csr_data (csrbus_wr_data[12]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_p_hw_set[2]),
.q (imu_logged_error_status_reg_csrbus_read_data[12])
// synopsys translate_off
.omni_data (omni_data[13]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_p[3]),
.csr_data (csrbus_wr_data[13]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_p_hw_set[3]),
.q (imu_logged_error_status_reg_csrbus_read_data[13])
// synopsys translate_off
.omni_data (omni_data[14]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_p[4]),
.csr_data (csrbus_wr_data[14]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_p_hw_set[4]),
.q (imu_logged_error_status_reg_csrbus_read_data[14])
assign imu_logged_error_status_reg_csrbus_read_data[15] = 1'b0; // bit 15
assign imu_logged_error_status_reg_csrbus_read_data[16] = 1'b0; // bit 16
assign imu_logged_error_status_reg_csrbus_read_data[17] = 1'b0; // bit 17
assign imu_logged_error_status_reg_csrbus_read_data[18] = 1'b0; // bit 18
assign imu_logged_error_status_reg_csrbus_read_data[19] = 1'b0; // bit 19
assign imu_logged_error_status_reg_csrbus_read_data[20] = 1'b0; // bit 20
assign imu_logged_error_status_reg_csrbus_read_data[21] = 1'b0; // bit 21
assign imu_logged_error_status_reg_csrbus_read_data[22] = 1'b0; // bit 22
assign imu_logged_error_status_reg_csrbus_read_data[23] = 1'b0; // bit 23
assign imu_logged_error_status_reg_csrbus_read_data[24] = 1'b0; // bit 24
assign imu_logged_error_status_reg_csrbus_read_data[25] = 1'b0; // bit 25
assign imu_logged_error_status_reg_csrbus_read_data[26] = 1'b0; // bit 26
assign imu_logged_error_status_reg_csrbus_read_data[27] = 1'b0; // bit 27
assign imu_logged_error_status_reg_csrbus_read_data[28] = 1'b0; // bit 28
assign imu_logged_error_status_reg_csrbus_read_data[29] = 1'b0; // bit 29
assign imu_logged_error_status_reg_csrbus_read_data[30] = 1'b0; // bit 30
assign imu_logged_error_status_reg_csrbus_read_data[31] = 1'b0; // bit 31
// synopsys translate_off
.omni_data (omni_data[32]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_msi_not_en_s[0]),
.csr_data (csrbus_wr_data[32]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_msi_not_en_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[32])
// synopsys translate_off
.omni_data (omni_data[33]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_cor_mes_not_en_s[0]),
.csr_data (csrbus_wr_data[33]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_cor_mes_not_en_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[33])
// synopsys translate_off
.omni_data (omni_data[34]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_nonfatal_mes_not_en_s[0]),
.csr_data (csrbus_wr_data[34]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_nonfatal_mes_not_en_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[34])
// synopsys translate_off
.omni_data (omni_data[35]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_fatal_mes_not_en_s[0]),
.csr_data (csrbus_wr_data[35]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_fatal_mes_not_en_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[35])
// synopsys translate_off
.omni_data (omni_data[36]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_pmpme_mes_not_en_s[0]),
.csr_data (csrbus_wr_data[36]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_pmpme_mes_not_en_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[36])
// synopsys translate_off
.omni_data (omni_data[37]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_pmeack_mes_not_en_s[0]),
.csr_data (csrbus_wr_data[37]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_pmeack_mes_not_en_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[37])
// synopsys translate_off
.omni_data (omni_data[38]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_msi_par_err_s[0]),
.csr_data (csrbus_wr_data[38]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_msi_par_err_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[38])
// synopsys translate_off
.omni_data (omni_data[39]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_msi_mal_err_s[0]),
.csr_data (csrbus_wr_data[39]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_msi_mal_err_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[39])
// synopsys translate_off
.omni_data (omni_data[40]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_eq_not_en_s[0]),
.csr_data (csrbus_wr_data[40]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_eq_not_en_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[40])
// synopsys translate_off
.omni_data (omni_data[41]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_eq_over_s[0]),
.csr_data (csrbus_wr_data[41]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_eq_over_s_hw_set),
.q (imu_logged_error_status_reg_csrbus_read_data[41])
// synopsys translate_off
.omni_data (omni_data[42]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_s[0]),
.csr_data (csrbus_wr_data[42]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_s_hw_set[0]),
.q (imu_logged_error_status_reg_csrbus_read_data[42])
// synopsys translate_off
.omni_data (omni_data[43]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_s[1]),
.csr_data (csrbus_wr_data[43]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_s_hw_set[1]),
.q (imu_logged_error_status_reg_csrbus_read_data[43])
// synopsys translate_off
.omni_data (omni_data[44]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_s[2]),
.csr_data (csrbus_wr_data[44]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_s_hw_set[2]),
.q (imu_logged_error_status_reg_csrbus_read_data[44])
// synopsys translate_off
.omni_data (omni_data[45]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_s[3]),
.csr_data (csrbus_wr_data[45]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_s_hw_set[3]),
.q (imu_logged_error_status_reg_csrbus_read_data[45])
// synopsys translate_off
.omni_data (omni_data[46]),
.omni_rw1c_alias (omni_rw1c_alias),
.omni_rw1s_alias (omni_rw1s_alias),
.rst (por_l_active_high),
.rst_val (reset_spare_s[4]),
.csr_data (csrbus_wr_data[46]),
.rw1c_alias (rw1c_alias),
.rw1s_alias (rw1s_alias),
.hw_ld (imu_logged_error_status_reg_spare_s_hw_set[4]),
.q (imu_logged_error_status_reg_csrbus_read_data[46])
assign imu_logged_error_status_reg_csrbus_read_data[47] = 1'b0; // bit 47
assign imu_logged_error_status_reg_csrbus_read_data[48] = 1'b0; // bit 48
assign imu_logged_error_status_reg_csrbus_read_data[49] = 1'b0; // bit 49
assign imu_logged_error_status_reg_csrbus_read_data[50] = 1'b0; // bit 50
assign imu_logged_error_status_reg_csrbus_read_data[51] = 1'b0; // bit 51
assign imu_logged_error_status_reg_csrbus_read_data[52] = 1'b0; // bit 52
assign imu_logged_error_status_reg_csrbus_read_data[53] = 1'b0; // bit 53
assign imu_logged_error_status_reg_csrbus_read_data[54] = 1'b0; // bit 54
assign imu_logged_error_status_reg_csrbus_read_data[55] = 1'b0; // bit 55
assign imu_logged_error_status_reg_csrbus_read_data[56] = 1'b0; // bit 56
assign imu_logged_error_status_reg_csrbus_read_data[57] = 1'b0; // bit 57
assign imu_logged_error_status_reg_csrbus_read_data[58] = 1'b0; // bit 58
assign imu_logged_error_status_reg_csrbus_read_data[59] = 1'b0; // bit 59
assign imu_logged_error_status_reg_csrbus_read_data[60] = 1'b0; // bit 60
assign imu_logged_error_status_reg_csrbus_read_data[61] = 1'b0; // bit 61
assign imu_logged_error_status_reg_csrbus_read_data[62] = 1'b0; // bit 62
assign imu_logged_error_status_reg_csrbus_read_data[63] = 1'b0; // bit 63
endmodule // dmu_imu_ics_csr_imu_logged_error_status_reg_entry