| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: dmu_mmu_csr_flts.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module dmu_mmu_csr_flts |
| 36 | ( |
| 37 | clk, |
| 38 | por_l, |
| 39 | flts_w_ld, |
| 40 | csrbus_wr_data, |
| 41 | flts_csrbus_read_data, |
| 42 | flts_entry_hw_ld, |
| 43 | flts_entry_hw_write, |
| 44 | flts_type_hw_ld, |
| 45 | flts_type_hw_write, |
| 46 | flts_id_hw_ld, |
| 47 | flts_id_hw_write |
| 48 | ); |
| 49 | |
| 50 | //==================================================================== |
| 51 | // Polarity declarations |
| 52 | //==================================================================== |
| 53 | input clk; // Clock |
| 54 | input por_l; // Reset signal |
| 55 | input flts_w_ld; // SW load bus |
| 56 | input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 57 | output [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data; // SW read |
| 58 | // data |
| 59 | input flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw |
| 60 | // write signal> will be loaded into flts. |
| 61 | input [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write; |
| 62 | // data bus for hw loading of flts_entry. |
| 63 | input flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw |
| 64 | // write signal> will be loaded into flts. |
| 65 | input [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus |
| 66 | // for hw |
| 67 | // loading of |
| 68 | // flts_type. |
| 69 | input flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write |
| 70 | // signal> will be loaded into flts. |
| 71 | input [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw |
| 72 | // loading of |
| 73 | // flts_id. |
| 74 | |
| 75 | //==================================================================== |
| 76 | // Type declarations |
| 77 | //==================================================================== |
| 78 | wire clk; // Clock |
| 79 | wire por_l; // Reset signal |
| 80 | wire flts_w_ld; // SW load bus |
| 81 | wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data |
| 82 | wire [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] flts_csrbus_read_data; // SW read data |
| 83 | wire flts_entry_hw_ld; // Hardware load enable for flts_entry. When set, <hw |
| 84 | // write signal> will be loaded into flts. |
| 85 | wire [`FIRE_DLC_MMU_CSR_FLTS_ENTRY_INT_SLC] flts_entry_hw_write; // data bus |
| 86 | // for hw |
| 87 | // loading of |
| 88 | // flts_entry. |
| 89 | wire flts_type_hw_ld; // Hardware load enable for flts_type. When set, <hw |
| 90 | // write signal> will be loaded into flts. |
| 91 | wire [`FIRE_DLC_MMU_CSR_FLTS_TYPE_INT_SLC] flts_type_hw_write; // data bus for |
| 92 | // hw loading of |
| 93 | // flts_type. |
| 94 | wire flts_id_hw_ld; // Hardware load enable for flts_id. When set, <hw write |
| 95 | // signal> will be loaded into flts. |
| 96 | wire [`FIRE_DLC_MMU_CSR_FLTS_ID_INT_SLC] flts_id_hw_write; // data bus for hw |
| 97 | // loading of |
| 98 | // flts_id. |
| 99 | |
| 100 | //==================================================================== |
| 101 | // Logic |
| 102 | //==================================================================== |
| 103 | |
| 104 | // synopsys translate_off |
| 105 | // verilint 123 off |
| 106 | // verilint 498 off |
| 107 | reg omni_ld; |
| 108 | reg [`FIRE_DLC_MMU_CSR_FLTS_WIDTH-1:0] omni_data; |
| 109 | |
| 110 | // vlint flag_unsynthesizable_initial off |
| 111 | initial |
| 112 | begin |
| 113 | omni_ld = 1'b0; |
| 114 | omni_data = `FIRE_DLC_MMU_CSR_FLTS_WIDTH'b0; |
| 115 | end// vlint flag_unsynthesizable_initial on |
| 116 | |
| 117 | // verilint 123 on |
| 118 | // verilint 498 on |
| 119 | // synopsys translate_on |
| 120 | |
| 121 | //----- Hardware Data Out Mux Assignments |
| 122 | |
| 123 | //==================================================================== |
| 124 | // Instantiation of entries |
| 125 | //==================================================================== |
| 126 | |
| 127 | //----- Entry 0 |
| 128 | dmu_mmu_csr_flts_entry flts_0 |
| 129 | ( |
| 130 | // synopsys translate_off |
| 131 | .omni_ld (omni_ld), |
| 132 | .omni_data (omni_data), |
| 133 | // synopsys translate_on |
| 134 | .clk (clk), |
| 135 | .por_l (por_l), |
| 136 | .w_ld (flts_w_ld), |
| 137 | .csrbus_wr_data (csrbus_wr_data), |
| 138 | .flts_csrbus_read_data (flts_csrbus_read_data), |
| 139 | .flts_entry_hw_ld (flts_entry_hw_ld), |
| 140 | .flts_entry_hw_write (flts_entry_hw_write), |
| 141 | .flts_type_hw_ld (flts_type_hw_ld), |
| 142 | .flts_type_hw_write (flts_type_hw_write), |
| 143 | .flts_id_hw_ld (flts_id_hw_ld), |
| 144 | .flts_id_hw_write (flts_id_hw_write) |
| 145 | ); |
| 146 | |
| 147 | endmodule // dmu_mmu_csr_flts |