| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: dmu_tsb_defines.h |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | `ifdef FIRE_DLC_TSB_DEFINES |
| 39 | `else |
| 40 | `define FIRE_DLC_TSB_DEFINES |
| 41 | |
| 42 | `define FIRE_DLC_TSB_CSRBUS_EXT_ADDR_WIDTH 5 |
| 43 | `define FIRE_DLC_TSB_CSRBUS_EXT_ADDR_RANGE 4:0 |
| 44 | |
| 45 | `define FIRE_DLC_TSB_INSTANCE_ID_VALUE_A 1'h0 |
| 46 | `define FIRE_DLC_TSB_INSTANCE_ID_VALUE_B 1'h1 |
| 47 | |
| 48 | //------------------------------------------------------- |
| 49 | //----- Variable definitions for register fire_dlc_tsb_csr_tsb_dma |
| 50 | //------------------------------------------------------- |
| 51 | |
| 52 | `define FIRE_DLC_TSB_CSR_A_TSB_DMA_HW_ADDR 27'b000000011001110000000000000 |
| 53 | `define FIRE_DLC_TSB_CSR_A_TSB_DMA_ADDR 30'b000000011001110000000000000000 |
| 54 | `define FIRE_DLC_TSB_CSR_B_TSB_DMA_HW_ADDR 27'b000000011101110000000000000 |
| 55 | `define FIRE_DLC_TSB_CSR_B_TSB_DMA_ADDR 30'b000000011101110000000000000000 |
| 56 | |
| 57 | `define FIRE_DLC_TSB_CSR_TSB_DMA_WIDTH 64 |
| 58 | `define FIRE_DLC_TSB_CSR_TSB_DMA_DEPTH 32 |
| 59 | `define FIRE_DLC_TSB_CSR_TSB_DMA_SLC 63:0 |
| 60 | `define FIRE_DLC_TSB_CSR_TSB_DMA_INT_SLC 63:0 |
| 61 | `define FIRE_DLC_TSB_CSR_TSB_DMA_POSITION 0 |
| 62 | `define FIRE_DLC_TSB_CSR_TSB_DMA_LOW_ADDR_WIDTH 5 |
| 63 | `define FIRE_DLC_TSB_CSR_TSB_DMA_SEL_RANGE 4:0 |
| 64 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ADDR_RANGE 26:5 |
| 65 | `define FIRE_DLC_TSB_CSR_TSB_DMA_READ_MASK 64'b0000000000000000111111111111111111111111111111111111111111111111 |
| 66 | `define FIRE_DLC_TSB_CSR_TSB_DMA_READ_ONLY_MASK 64'b0000000000000000111111111111111111111111111111111111111111111111 |
| 67 | `define FIRE_DLC_TSB_CSR_TSB_DMA_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 68 | `define FIRE_DLC_TSB_CSR_TSB_DMA_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 69 | `define FIRE_DLC_TSB_CSR_TSB_DMA_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 70 | `define FIRE_DLC_TSB_CSR_TSB_DMA_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 71 | `define FIRE_DLC_TSB_CSR_TSB_DMA_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 72 | `define FIRE_DLC_TSB_CSR_TSB_DMA_RMASK 64'b0000000000000000111111111111111111111111111111111111111111111111 |
| 73 | `define FIRE_DLC_TSB_CSR_TSB_DMA_RESERVED_BIT_MASK 64'b1111111111111111000000000000000000000000000000000000000000000000 |
| 74 | `define FIRE_DLC_TSB_CSR_TSB_DMA_HW_LD_MASK 64'b0000000000000000111111111111111111111111111111111111111111111111 |
| 75 | `define FIRE_DLC_TSB_CSR_TSB_DMA_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 76 | `define FIRE_DLC_TSB_CSR_TSB_DMA_INTERNAL_REG 0 |
| 77 | `define FIRE_DLC_TSB_CSR_TSB_DMA_EXTERNAL_DECODE_REG 0 |
| 78 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ZERO_TIME_OMNI 0 |
| 79 | `define FIRE_DLC_TSB_CSR_TSB_DMA_NUM_FIELDS 1 |
| 80 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_FID 0 |
| 81 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_SLC 47:0 |
| 82 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_WIDTH 48 |
| 83 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_INT_SLC 47:0 |
| 84 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_POSITION 0 |
| 85 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_FMASK 64'b0000000000000000111111111111111111111111111111111111111111111111 |
| 86 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_HW_LD_MASK 64'b0000000000000000111111111111111111111111111111111111111111111111 |
| 87 | `define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_POR_VALUE 48'b000000000000000000000000000000000000000000000000 |
| 88 | |
| 89 | //------------------------------------------------------- |
| 90 | //----- Variable definitions for register fire_dlc_tsb_csr_tsb_sts |
| 91 | //------------------------------------------------------- |
| 92 | |
| 93 | `define FIRE_DLC_TSB_CSR_A_TSB_STS_HW_ADDR 27'b000000011001110000000100000 |
| 94 | `define FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR 30'b000000011001110000000100000000 |
| 95 | `define FIRE_DLC_TSB_CSR_B_TSB_STS_HW_ADDR 27'b000000011101110000000100000 |
| 96 | `define FIRE_DLC_TSB_CSR_B_TSB_STS_ADDR 30'b000000011101110000000100000000 |
| 97 | |
| 98 | `define FIRE_DLC_TSB_CSR_TSB_STS_WIDTH 64 |
| 99 | `define FIRE_DLC_TSB_CSR_TSB_STS_DEPTH 1 |
| 100 | `define FIRE_DLC_TSB_CSR_TSB_STS_SLC 63:0 |
| 101 | `define FIRE_DLC_TSB_CSR_TSB_STS_INT_SLC 63:0 |
| 102 | `define FIRE_DLC_TSB_CSR_TSB_STS_POSITION 0 |
| 103 | `define FIRE_DLC_TSB_CSR_TSB_STS_LOW_ADDR_WIDTH 0 |
| 104 | `define FIRE_DLC_TSB_CSR_TSB_STS_ADDR_RANGE 26:0 |
| 105 | `define FIRE_DLC_TSB_CSR_TSB_STS_READ_MASK 64'b0000000000000000000000000000000000000000000000000000000011111111 |
| 106 | `define FIRE_DLC_TSB_CSR_TSB_STS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000011111111 |
| 107 | `define FIRE_DLC_TSB_CSR_TSB_STS_WRITE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 108 | `define FIRE_DLC_TSB_CSR_TSB_STS_WRITE_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 109 | `define FIRE_DLC_TSB_CSR_TSB_STS_SET_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 110 | `define FIRE_DLC_TSB_CSR_TSB_STS_CLEAR_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 111 | `define FIRE_DLC_TSB_CSR_TSB_STS_TOGGLE_MASK 64'b0000000000000000000000000000000000000000000000000000000000000000 |
| 112 | `define FIRE_DLC_TSB_CSR_TSB_STS_RMASK 64'b0000000000000000000000000000000000000000000000000000000011111111 |
| 113 | `define FIRE_DLC_TSB_CSR_TSB_STS_RESERVED_BIT_MASK 64'b1111111111111111111111111111111111111111111111111111111100000000 |
| 114 | `define FIRE_DLC_TSB_CSR_TSB_STS_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000011111111 |
| 115 | `define FIRE_DLC_TSB_CSR_TSB_STS_POR_VALUE 64'b0000000000000000000000000000000000000000000000000000000000000001 |
| 116 | `define FIRE_DLC_TSB_CSR_TSB_STS_INTERNAL_REG 0 |
| 117 | `define FIRE_DLC_TSB_CSR_TSB_STS_EXTERNAL_DECODE_REG 1 |
| 118 | `define FIRE_DLC_TSB_CSR_TSB_STS_ZERO_TIME_OMNI 0 |
| 119 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_FIELDS 3 |
| 120 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_FID 0 |
| 121 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_SLC 7:7 |
| 122 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_WIDTH 1 |
| 123 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_INT_SLC 0:0 |
| 124 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_POSITION 7 |
| 125 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_FMASK 64'b0000000000000000000000000000000000000000000000000000000010000000 |
| 126 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000010000000 |
| 127 | `define FIRE_DLC_TSB_CSR_TSB_STS_FULL_POR_VALUE 1'b0 |
| 128 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_FID 1 |
| 129 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_SLC 6:1 |
| 130 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_WIDTH 6 |
| 131 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_INT_SLC 5:0 |
| 132 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_POSITION 1 |
| 133 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_FMASK 64'b0000000000000000000000000000000000000000000000000000000001111110 |
| 134 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001111110 |
| 135 | `define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_POR_VALUE 6'b000000 |
| 136 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_FID 2 |
| 137 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_SLC 0:0 |
| 138 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_WIDTH 1 |
| 139 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_INT_SLC 0:0 |
| 140 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_POSITION 0 |
| 141 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_FMASK 64'b0000000000000000000000000000000000000000000000000000000000000001 |
| 142 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000000000001 |
| 143 | `define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_POR_VALUE 1'b1 |
| 144 | |
| 145 | |
| 146 | `endif |