design/sys/iop/dmu/rtl/dmu_tsb_defines.h

/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: dmu_tsb_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
`ifdef FIRE_DLC_TSB_DEFINES
`else
`define FIRE_DLC_TSB_DEFINES

`define FIRE_DLC_TSB_CSRBUS_EXT_ADDR_WIDTH      5
`define FIRE_DLC_TSB_CSRBUS_EXT_ADDR_RANGE      4:0

`define FIRE_DLC_TSB_INSTANCE_ID_VALUE_A 1'h0
`define FIRE_DLC_TSB_INSTANCE_ID_VALUE_B 1'h1

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_tsb_csr_tsb_dma
//-------------------------------------------------------

`define FIRE_DLC_TSB_CSR_A_TSB_DMA_HW_ADDR      27'b000000011001110000000000000
`define FIRE_DLC_TSB_CSR_A_TSB_DMA_ADDR 30'b000000011001110000000000000000
`define FIRE_DLC_TSB_CSR_B_TSB_DMA_HW_ADDR      27'b000000011101110000000000000
`define FIRE_DLC_TSB_CSR_B_TSB_DMA_ADDR 30'b000000011101110000000000000000

`define FIRE_DLC_TSB_CSR_TSB_DMA_WIDTH  64
`define FIRE_DLC_TSB_CSR_TSB_DMA_DEPTH  32
`define FIRE_DLC_TSB_CSR_TSB_DMA_SLC    63:0
`define FIRE_DLC_TSB_CSR_TSB_DMA_INT_SLC        63:0
`define FIRE_DLC_TSB_CSR_TSB_DMA_POSITION       0
`define FIRE_DLC_TSB_CSR_TSB_DMA_LOW_ADDR_WIDTH 5
`define FIRE_DLC_TSB_CSR_TSB_DMA_SEL_RANGE      4:0
`define FIRE_DLC_TSB_CSR_TSB_DMA_ADDR_RANGE     26:5
`define FIRE_DLC_TSB_CSR_TSB_DMA_READ_MASK      64'b0000000000000000111111111111111111111111111111111111111111111111
`define FIRE_DLC_TSB_CSR_TSB_DMA_READ_ONLY_MASK 64'b0000000000000000111111111111111111111111111111111111111111111111
`define FIRE_DLC_TSB_CSR_TSB_DMA_WRITE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_DMA_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_DMA_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_DMA_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_DMA_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_DMA_RMASK  64'b0000000000000000111111111111111111111111111111111111111111111111
`define FIRE_DLC_TSB_CSR_TSB_DMA_RESERVED_BIT_MASK      64'b1111111111111111000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_DMA_HW_LD_MASK     64'b0000000000000000111111111111111111111111111111111111111111111111
`define FIRE_DLC_TSB_CSR_TSB_DMA_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_DMA_INTERNAL_REG   0
`define FIRE_DLC_TSB_CSR_TSB_DMA_EXTERNAL_DECODE_REG    0
`define FIRE_DLC_TSB_CSR_TSB_DMA_ZERO_TIME_OMNI 0
`define FIRE_DLC_TSB_CSR_TSB_DMA_NUM_FIELDS     1
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_FID      0
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_SLC      47:0
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_WIDTH    48
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_INT_SLC  47:0
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_POSITION 0
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_FMASK    64'b0000000000000000111111111111111111111111111111111111111111111111
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_HW_LD_MASK       64'b0000000000000000111111111111111111111111111111111111111111111111
`define FIRE_DLC_TSB_CSR_TSB_DMA_ENTRY_POR_VALUE        48'b000000000000000000000000000000000000000000000000

//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_tsb_csr_tsb_sts
//-------------------------------------------------------

`define FIRE_DLC_TSB_CSR_A_TSB_STS_HW_ADDR      27'b000000011001110000000100000
`define FIRE_DLC_TSB_CSR_A_TSB_STS_ADDR 30'b000000011001110000000100000000
`define FIRE_DLC_TSB_CSR_B_TSB_STS_HW_ADDR      27'b000000011101110000000100000
`define FIRE_DLC_TSB_CSR_B_TSB_STS_ADDR 30'b000000011101110000000100000000

`define FIRE_DLC_TSB_CSR_TSB_STS_WIDTH  64
`define FIRE_DLC_TSB_CSR_TSB_STS_DEPTH  1
`define FIRE_DLC_TSB_CSR_TSB_STS_SLC    63:0
`define FIRE_DLC_TSB_CSR_TSB_STS_INT_SLC        63:0
`define FIRE_DLC_TSB_CSR_TSB_STS_POSITION       0
`define FIRE_DLC_TSB_CSR_TSB_STS_LOW_ADDR_WIDTH 0
`define FIRE_DLC_TSB_CSR_TSB_STS_ADDR_RANGE     26:0
`define FIRE_DLC_TSB_CSR_TSB_STS_READ_MASK      64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_DLC_TSB_CSR_TSB_STS_READ_ONLY_MASK 64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_DLC_TSB_CSR_TSB_STS_WRITE_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_STS_WRITE_ONLY_MASK        64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_STS_SET_MASK       64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_STS_CLEAR_MASK     64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_STS_TOGGLE_MASK    64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_TSB_CSR_TSB_STS_RMASK  64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_DLC_TSB_CSR_TSB_STS_RESERVED_BIT_MASK      64'b1111111111111111111111111111111111111111111111111111111100000000
`define FIRE_DLC_TSB_CSR_TSB_STS_HW_LD_MASK     64'b0000000000000000000000000000000000000000000000000000000011111111
`define FIRE_DLC_TSB_CSR_TSB_STS_POR_VALUE      64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_TSB_CSR_TSB_STS_INTERNAL_REG   0
`define FIRE_DLC_TSB_CSR_TSB_STS_EXTERNAL_DECODE_REG    1
`define FIRE_DLC_TSB_CSR_TSB_STS_ZERO_TIME_OMNI 0
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_FIELDS     3
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_FID       0
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_SLC       7:7
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_WIDTH     1
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_INT_SLC   0:0
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_POSITION  7
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_FMASK     64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_HW_LD_MASK        64'b0000000000000000000000000000000000000000000000000000000010000000
`define FIRE_DLC_TSB_CSR_TSB_STS_FULL_POR_VALUE 1'b0
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_FID        1
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_SLC        6:1
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_WIDTH      6
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_INT_SLC    5:0
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_POSITION   1
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_FMASK      64'b0000000000000000000000000000000000000000000000000000000001111110
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_HW_LD_MASK 64'b0000000000000000000000000000000000000000000000000000000001111110
`define FIRE_DLC_TSB_CSR_TSB_STS_NUM_PND_DMA_POR_VALUE  6'b000000
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_FID      2
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_SLC      0:0
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_WIDTH    1
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_INT_SLC  0:0
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_POSITION 0
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_FMASK    64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_HW_LD_MASK       64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_TSB_CSR_TSB_STS_EMPTY_POR_VALUE        1'b1


`endif