| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcu_crcn_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mcu_crcn_ctl ( |
| 36 | crcnd_crc0_0, |
| 37 | crcnd_crc0_1, |
| 38 | crcnd_crc1_0, |
| 39 | crcnd_crc1_1, |
| 40 | crcndf_crc0_0, |
| 41 | crcndf_crc0_1, |
| 42 | crcndf_crc1_0, |
| 43 | crcndf_crc1_1, |
| 44 | bd00, |
| 45 | bd01, |
| 46 | bd10, |
| 47 | bd11, |
| 48 | drl2clk, |
| 49 | scan_in, |
| 50 | scan_out, |
| 51 | tcu_pce_ov, |
| 52 | tcu_aclk, |
| 53 | tcu_bclk, |
| 54 | tcu_scan_en); |
| 55 | wire pce_ov; |
| 56 | wire siclk; |
| 57 | wire soclk; |
| 58 | wire se; |
| 59 | wire l1clk; |
| 60 | wire spares_scanin; |
| 61 | wire spares_scanout; |
| 62 | |
| 63 | |
| 64 | output [11:0] crcnd_crc0_0; |
| 65 | output [11:0] crcnd_crc0_1; |
| 66 | output [11:0] crcnd_crc1_0; |
| 67 | output [11:0] crcnd_crc1_1; |
| 68 | |
| 69 | output [5:0] crcndf_crc0_0; |
| 70 | output [5:0] crcndf_crc0_1; |
| 71 | output [5:0] crcndf_crc1_0; |
| 72 | output [5:0] crcndf_crc1_1; |
| 73 | |
| 74 | input [71:0] bd00; |
| 75 | input [71:0] bd01; |
| 76 | input [71:0] bd10; |
| 77 | input [71:0] bd11; |
| 78 | |
| 79 | input drl2clk; |
| 80 | input scan_in; |
| 81 | output scan_out; |
| 82 | input tcu_pce_ov; |
| 83 | input tcu_aclk; |
| 84 | input tcu_bclk; |
| 85 | input tcu_scan_en; |
| 86 | |
| 87 | // Code |
| 88 | assign pce_ov = tcu_pce_ov; |
| 89 | assign siclk = tcu_aclk; |
| 90 | assign soclk = tcu_bclk; |
| 91 | assign se = tcu_scan_en; |
| 92 | |
| 93 | // 0in set_clock drl2clk -default |
| 94 | mcu_crcn_ctl_l1clkhdr_ctl_macro clkgen ( |
| 95 | .l2clk(drl2clk), |
| 96 | .l1en (1'b1 ), |
| 97 | .stop(1'b0), |
| 98 | .l1clk(l1clk), |
| 99 | .pce_ov(pce_ov), |
| 100 | .se(se)); |
| 101 | |
| 102 | mcu_crcnd_ctl crcnd0_0 ( |
| 103 | .in(bd00[71:0]), |
| 104 | .crc(crcnd_crc0_0[11:0]) |
| 105 | ); |
| 106 | |
| 107 | mcu_crcndf_ctl crcndf0_0 ( |
| 108 | .in(bd00[71:0]), |
| 109 | .crc(crcndf_crc0_0[5:0]) |
| 110 | ); |
| 111 | |
| 112 | mcu_crcnd_ctl crcnd0_1 ( |
| 113 | .in(bd01[71:0]), |
| 114 | .crc(crcnd_crc0_1[11:0]) |
| 115 | ); |
| 116 | |
| 117 | mcu_crcndf_ctl crcndf0_1 ( |
| 118 | .in(bd01[71:0]), |
| 119 | .crc(crcndf_crc0_1[5:0]) |
| 120 | ); |
| 121 | |
| 122 | mcu_crcnd_ctl crcnd1_0 ( |
| 123 | .in(bd10[71:0]), |
| 124 | .crc(crcnd_crc1_0[11:0]) |
| 125 | ); |
| 126 | |
| 127 | mcu_crcndf_ctl crcndf1_0 ( |
| 128 | .in(bd10[71:0]), |
| 129 | .crc(crcndf_crc1_0[5:0]) |
| 130 | ); |
| 131 | |
| 132 | mcu_crcnd_ctl crcnd1_1 ( |
| 133 | .in(bd11[71:0]), |
| 134 | .crc(crcnd_crc1_1[11:0]) |
| 135 | ); |
| 136 | |
| 137 | mcu_crcndf_ctl crcndf1_1 ( |
| 138 | .in(bd11[71:0]), |
| 139 | .crc(crcndf_crc1_1[5:0]) |
| 140 | ); |
| 141 | |
| 142 | mcu_crcn_ctl_spare_ctl_macro__num_1 spares ( |
| 143 | .scan_in(spares_scanin), |
| 144 | .scan_out(spares_scanout), |
| 145 | .l1clk(l1clk), |
| 146 | .siclk(siclk), |
| 147 | .soclk(soclk) |
| 148 | ); |
| 149 | |
| 150 | // fixscan start: |
| 151 | assign spares_scanin = scan_in ; |
| 152 | assign scan_out = spares_scanout ; |
| 153 | // fixscan end: |
| 154 | endmodule |
| 155 | |
| 156 | |
| 157 | |
| 158 | |
| 159 | |
| 160 | |
| 161 | |
| 162 | // any PARAMS parms go into naming of macro |
| 163 | |
| 164 | module mcu_crcn_ctl_l1clkhdr_ctl_macro ( |
| 165 | l2clk, |
| 166 | l1en, |
| 167 | pce_ov, |
| 168 | stop, |
| 169 | se, |
| 170 | l1clk); |
| 171 | |
| 172 | |
| 173 | input l2clk; |
| 174 | input l1en; |
| 175 | input pce_ov; |
| 176 | input stop; |
| 177 | input se; |
| 178 | output l1clk; |
| 179 | |
| 180 | |
| 181 | |
| 182 | |
| 183 | |
| 184 | cl_sc1_l1hdr_8x c_0 ( |
| 185 | |
| 186 | |
| 187 | .l2clk(l2clk), |
| 188 | .pce(l1en), |
| 189 | .l1clk(l1clk), |
| 190 | .se(se), |
| 191 | .pce_ov(pce_ov), |
| 192 | .stop(stop) |
| 193 | ); |
| 194 | |
| 195 | endmodule |
| 196 | |
| 197 | |
| 198 | // Description: Spare gate macro for control blocks |
| 199 | // |
| 200 | // Param num controls the number of times the macro is added |
| 201 | // flops=0 can be used to use only combination spare logic |
| 202 | |
| 203 | |
| 204 | module mcu_crcn_ctl_spare_ctl_macro__num_1 ( |
| 205 | l1clk, |
| 206 | scan_in, |
| 207 | siclk, |
| 208 | soclk, |
| 209 | scan_out); |
| 210 | wire si_0; |
| 211 | wire so_0; |
| 212 | wire spare0_flop_unused; |
| 213 | wire spare0_buf_32x_unused; |
| 214 | wire spare0_nand3_8x_unused; |
| 215 | wire spare0_inv_8x_unused; |
| 216 | wire spare0_aoi22_4x_unused; |
| 217 | wire spare0_buf_8x_unused; |
| 218 | wire spare0_oai22_4x_unused; |
| 219 | wire spare0_inv_16x_unused; |
| 220 | wire spare0_nand2_16x_unused; |
| 221 | wire spare0_nor3_4x_unused; |
| 222 | wire spare0_nand2_8x_unused; |
| 223 | wire spare0_buf_16x_unused; |
| 224 | wire spare0_nor2_16x_unused; |
| 225 | wire spare0_inv_32x_unused; |
| 226 | |
| 227 | |
| 228 | input l1clk; |
| 229 | input scan_in; |
| 230 | input siclk; |
| 231 | input soclk; |
| 232 | output scan_out; |
| 233 | |
| 234 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 235 | .siclk(siclk), |
| 236 | .soclk(soclk), |
| 237 | .si(si_0), |
| 238 | .so(so_0), |
| 239 | .d(1'b0), |
| 240 | .q(spare0_flop_unused)); |
| 241 | assign si_0 = scan_in; |
| 242 | |
| 243 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 244 | .out(spare0_buf_32x_unused)); |
| 245 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 246 | .in1(1'b1), |
| 247 | .in2(1'b1), |
| 248 | .out(spare0_nand3_8x_unused)); |
| 249 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 250 | .out(spare0_inv_8x_unused)); |
| 251 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 252 | .in01(1'b1), |
| 253 | .in10(1'b1), |
| 254 | .in11(1'b1), |
| 255 | .out(spare0_aoi22_4x_unused)); |
| 256 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 257 | .out(spare0_buf_8x_unused)); |
| 258 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 259 | .in01(1'b1), |
| 260 | .in10(1'b1), |
| 261 | .in11(1'b1), |
| 262 | .out(spare0_oai22_4x_unused)); |
| 263 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 264 | .out(spare0_inv_16x_unused)); |
| 265 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 266 | .in1(1'b1), |
| 267 | .out(spare0_nand2_16x_unused)); |
| 268 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 269 | .in1(1'b0), |
| 270 | .in2(1'b0), |
| 271 | .out(spare0_nor3_4x_unused)); |
| 272 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 273 | .in1(1'b1), |
| 274 | .out(spare0_nand2_8x_unused)); |
| 275 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 276 | .out(spare0_buf_16x_unused)); |
| 277 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 278 | .in1(1'b0), |
| 279 | .out(spare0_nor2_16x_unused)); |
| 280 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 281 | .out(spare0_inv_32x_unused)); |
| 282 | assign scan_out = so_0; |
| 283 | |
| 284 | |
| 285 | |
| 286 | endmodule |
| 287 | |