| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mcu_dmmdly_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module mcu_dmmdly_ctl ( |
| 36 | rrd_cnt_is_zero, |
| 37 | rtw_cnt_is_zero, |
| 38 | wtr_cnt_is_zero, |
| 39 | rtr_cnt_is_zero, |
| 40 | wtw_cnt_is_zero, |
| 41 | dmmdly_4_activate_stall, |
| 42 | rrd_reg, |
| 43 | rtw_reg, |
| 44 | wtr_reg, |
| 45 | faw_reg, |
| 46 | drif_rd_ras_picked, |
| 47 | drif_wr_ras_picked, |
| 48 | drif_wrbc_ras_picked, |
| 49 | fbdic_sync_frame_req_l, |
| 50 | l1clk, |
| 51 | scan_in, |
| 52 | scan_out, |
| 53 | tcu_aclk, |
| 54 | tcu_bclk, |
| 55 | tcu_scan_en); |
| 56 | wire siclk; |
| 57 | wire soclk; |
| 58 | wire se; |
| 59 | wire drif_ras_picked; |
| 60 | wire [3:0] rrd_cnt_next; |
| 61 | wire [3:0] rrd_cnt; |
| 62 | wire ff_rrd_cnt_scanin; |
| 63 | wire ff_rrd_cnt_scanout; |
| 64 | wire [3:0] rtw_cnt_next; |
| 65 | wire [3:0] rtw_cnt; |
| 66 | wire ff_rtw_cnt_scanin; |
| 67 | wire ff_rtw_cnt_scanout; |
| 68 | wire [3:0] wtr_cnt_next; |
| 69 | wire [3:0] wtr_cnt; |
| 70 | wire ff_wtr_cnt_scanin; |
| 71 | wire ff_wtr_cnt_scanout; |
| 72 | wire rtr_cnt_next; |
| 73 | wire dmmdly_rd_cas_picked; |
| 74 | wire rtr_cnt; |
| 75 | wire ff_rtr_cnt_scanin; |
| 76 | wire ff_rtr_cnt_scanout; |
| 77 | wire [1:0] wtw_cnt_next; |
| 78 | wire dmmdly_wr_cas_picked; |
| 79 | wire dmmdly_wrbc_cas_picked; |
| 80 | wire [1:0] wtw_cnt; |
| 81 | wire ff_wtw_cnt_scanin; |
| 82 | wire ff_wtw_cnt_scanout; |
| 83 | wire drif_activate_cmd; |
| 84 | wire [4:0] faw0_cnt_in; |
| 85 | wire faw0_cnt_is_zero; |
| 86 | wire [4:0] faw0_cnt; |
| 87 | wire ff_faw0_cnt_scanin; |
| 88 | wire ff_faw0_cnt_scanout; |
| 89 | wire [4:0] faw1_cnt_in; |
| 90 | wire faw1_cnt_is_zero; |
| 91 | wire [4:0] faw1_cnt; |
| 92 | wire ff_faw1_cnt_scanin; |
| 93 | wire ff_faw1_cnt_scanout; |
| 94 | wire [4:0] faw2_cnt_in; |
| 95 | wire faw2_cnt_is_zero; |
| 96 | wire [4:0] faw2_cnt; |
| 97 | wire ff_faw2_cnt_scanin; |
| 98 | wire ff_faw2_cnt_scanout; |
| 99 | wire [4:0] faw3_cnt_in; |
| 100 | wire faw3_cnt_is_zero; |
| 101 | wire [4:0] faw3_cnt; |
| 102 | wire ff_faw3_cnt_scanin; |
| 103 | wire ff_faw3_cnt_scanout; |
| 104 | wire ff_cas_picked_scanin; |
| 105 | wire ff_cas_picked_scanout; |
| 106 | |
| 107 | |
| 108 | output rrd_cnt_is_zero; |
| 109 | output rtw_cnt_is_zero; |
| 110 | output wtr_cnt_is_zero; |
| 111 | output rtr_cnt_is_zero; |
| 112 | output wtw_cnt_is_zero; |
| 113 | output dmmdly_4_activate_stall; |
| 114 | |
| 115 | input [3:0] rrd_reg; |
| 116 | input [3:0] rtw_reg; |
| 117 | input [3:0] wtr_reg; |
| 118 | input [4:0] faw_reg; |
| 119 | |
| 120 | input drif_rd_ras_picked; |
| 121 | input drif_wr_ras_picked; |
| 122 | input drif_wrbc_ras_picked; |
| 123 | |
| 124 | input fbdic_sync_frame_req_l; |
| 125 | |
| 126 | input l1clk; |
| 127 | input scan_in; |
| 128 | output scan_out; |
| 129 | input tcu_aclk; |
| 130 | input tcu_bclk; |
| 131 | input tcu_scan_en; |
| 132 | |
| 133 | assign siclk = tcu_aclk; |
| 134 | assign soclk = tcu_bclk; |
| 135 | assign se = tcu_scan_en; |
| 136 | |
| 137 | assign drif_ras_picked = drif_rd_ras_picked | drif_wr_ras_picked; |
| 138 | |
| 139 | // ras to ras (bankA to bankB) delay timer. |
| 140 | assign rrd_cnt_next[3:0] = drif_ras_picked & rrd_cnt_is_zero ? rrd_reg[3:0] - 4'h1 : |
| 141 | drif_wrbc_ras_picked & rrd_cnt_is_zero ? rrd_reg[3:0] : |
| 142 | (rrd_cnt[3:0] == 4'h0) ? 4'h0 : |
| 143 | fbdic_sync_frame_req_l ? rrd_cnt[3:0] - 4'h1 : rrd_cnt[3:0]; |
| 144 | |
| 145 | mcu_dmmdly_ctl_msff_ctl_macro__width_4 ff_rrd_cnt ( |
| 146 | .scan_in(ff_rrd_cnt_scanin), |
| 147 | .scan_out(ff_rrd_cnt_scanout), |
| 148 | .din(rrd_cnt_next[3:0]), |
| 149 | .dout(rrd_cnt[3:0]), |
| 150 | .l1clk(l1clk), |
| 151 | .siclk(siclk), |
| 152 | .soclk(soclk)); |
| 153 | |
| 154 | assign rrd_cnt_is_zero = (rrd_cnt[3:0] == 4'h0); |
| 155 | |
| 156 | // read to write cas to cas (bankA to bankA/bankB) delay timer for not clashing read and write data. |
| 157 | // If read is picked during cas assert rtw_cnt to regular cnt + rtw delay. |
| 158 | assign rtw_cnt_next[3:0] = drif_rd_ras_picked ? rtw_reg[3:0] : |
| 159 | (rtw_cnt[3:0] == 4'h0) ? 4'h0 : |
| 160 | fbdic_sync_frame_req_l ? rtw_cnt[3:0] - 4'h1 : rtw_cnt[3:0]; |
| 161 | |
| 162 | mcu_dmmdly_ctl_msff_ctl_macro__width_4 ff_rtw_cnt ( |
| 163 | .scan_in(ff_rtw_cnt_scanin), |
| 164 | .scan_out(ff_rtw_cnt_scanout), |
| 165 | .din(rtw_cnt_next[3:0]), |
| 166 | .dout(rtw_cnt[3:0]), |
| 167 | .l1clk(l1clk), |
| 168 | .siclk(siclk), |
| 169 | .soclk(soclk)); |
| 170 | |
| 171 | assign rtw_cnt_is_zero = (rtw_cnt[3:0] == 4'h0); |
| 172 | |
| 173 | // write to read cas to cas (bankA to bankA/bankB) delay timer for not clashing read and write data. |
| 174 | assign wtr_cnt_next[3:0] = drif_wr_ras_picked ? wtr_reg[3:0] : |
| 175 | drif_wrbc_ras_picked ? wtr_reg[3:0] + 4'h1: |
| 176 | (wtr_cnt[3:0] == 4'h0) ? 4'h0 : |
| 177 | fbdic_sync_frame_req_l ? wtr_cnt[3:0] - 4'h1 : wtr_cnt[3:0]; |
| 178 | |
| 179 | mcu_dmmdly_ctl_msff_ctl_macro__width_4 ff_wtr_cnt ( |
| 180 | .scan_in(ff_wtr_cnt_scanin), |
| 181 | .scan_out(ff_wtr_cnt_scanout), |
| 182 | .din(wtr_cnt_next[3:0]), |
| 183 | .dout(wtr_cnt[3:0]), |
| 184 | .l1clk(l1clk), |
| 185 | .siclk(siclk), |
| 186 | .soclk(soclk)); |
| 187 | |
| 188 | assign wtr_cnt_is_zero = (wtr_cnt[3:0] == 4'h0); |
| 189 | |
| 190 | // read to read cas to cas (bankA to bankA/bankB) delay timer for not clashing read data. |
| 191 | assign rtr_cnt_next = dmmdly_rd_cas_picked & fbdic_sync_frame_req_l ? 1'h1 : |
| 192 | (rtr_cnt == 1'h0) ? 1'h0 : rtr_cnt - 1'h1; |
| 193 | |
| 194 | mcu_dmmdly_ctl_msff_ctl_macro__width_1 ff_rtr_cnt ( |
| 195 | .scan_in(ff_rtr_cnt_scanin), |
| 196 | .scan_out(ff_rtr_cnt_scanout), |
| 197 | .din(rtr_cnt_next), |
| 198 | .dout(rtr_cnt), |
| 199 | .l1clk(l1clk), |
| 200 | .siclk(siclk), |
| 201 | .soclk(soclk)); |
| 202 | |
| 203 | assign rtr_cnt_is_zero = (rtr_cnt == 1'h0); |
| 204 | |
| 205 | // write to write cas to cas (bankA to bankA/bankB) delay timer for not clashing store data. |
| 206 | assign wtw_cnt_next[1:0] = dmmdly_wr_cas_picked & fbdic_sync_frame_req_l ? 2'h1 : |
| 207 | dmmdly_wrbc_cas_picked & fbdic_sync_frame_req_l ? 2'h1 : |
| 208 | (wtw_cnt[1:0] == 2'h0) ? 2'h0 : wtw_cnt[1:0] - 2'h1; |
| 209 | |
| 210 | mcu_dmmdly_ctl_msff_ctl_macro__width_2 ff_wtw_cnt ( |
| 211 | .scan_in(ff_wtw_cnt_scanin), |
| 212 | .scan_out(ff_wtw_cnt_scanout), |
| 213 | .din(wtw_cnt_next[1:0]), |
| 214 | .dout(wtw_cnt[1:0]), |
| 215 | .l1clk(l1clk), |
| 216 | .siclk(siclk), |
| 217 | .soclk(soclk)); |
| 218 | |
| 219 | assign wtw_cnt_is_zero = (wtw_cnt[1:0] == 2'h0); |
| 220 | |
| 221 | ////////////////////////////////////////////////////////////////// |
| 222 | // Limit number of activates within tFAW to 4 |
| 223 | // Whenever an activate cmd is detected, a counter is started at |
| 224 | // the tFAW value. If all four counters are active, then the scheduler |
| 225 | // is stalled until one becomes inactive. |
| 226 | ////////////////////////////////////////////////////////////////// |
| 227 | |
| 228 | assign drif_activate_cmd = drif_rd_ras_picked | drif_wr_ras_picked | drif_wrbc_ras_picked; |
| 229 | |
| 230 | assign faw0_cnt_in[4:0] = faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ? faw_reg[4:0] - 5'h1 : |
| 231 | faw0_cnt_is_zero ? 5'h0 : faw0_cnt[4:0] - 5'h1; |
| 232 | |
| 233 | mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw0_cnt ( |
| 234 | .scan_in(ff_faw0_cnt_scanin), |
| 235 | .scan_out(ff_faw0_cnt_scanout), |
| 236 | .din(faw0_cnt_in[4:0]), |
| 237 | .dout(faw0_cnt[4:0]), |
| 238 | // .en(drif_sync_frame_req_l), |
| 239 | .l1clk(l1clk), |
| 240 | .siclk(siclk), |
| 241 | .soclk(soclk)); |
| 242 | |
| 243 | assign faw0_cnt_is_zero = (faw0_cnt[4:0] == 5'h0); |
| 244 | |
| 245 | assign faw1_cnt_in[4:0] = faw1_cnt_is_zero & ~faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ? faw_reg[4:0] - 5'h1 : |
| 246 | faw1_cnt_is_zero ? 5'h0 : faw1_cnt[4:0] - 5'h1; |
| 247 | |
| 248 | mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw1_cnt ( |
| 249 | .scan_in(ff_faw1_cnt_scanin), |
| 250 | .scan_out(ff_faw1_cnt_scanout), |
| 251 | .din(faw1_cnt_in[4:0]), |
| 252 | .dout(faw1_cnt[4:0]), |
| 253 | // .en(drif_sync_frame_req_l), |
| 254 | .l1clk(l1clk), |
| 255 | .siclk(siclk), |
| 256 | .soclk(soclk)); |
| 257 | |
| 258 | assign faw1_cnt_is_zero = (faw1_cnt[4:0] == 5'h0); |
| 259 | |
| 260 | assign faw2_cnt_in[4:0] = faw2_cnt_is_zero & ~faw1_cnt_is_zero & ~faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ? faw_reg[4:0] - 5'h1 : |
| 261 | faw2_cnt_is_zero ? 5'h0 : faw2_cnt[4:0] - 5'h1; |
| 262 | |
| 263 | mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw2_cnt ( |
| 264 | .scan_in(ff_faw2_cnt_scanin), |
| 265 | .scan_out(ff_faw2_cnt_scanout), |
| 266 | .din(faw2_cnt_in[4:0]), |
| 267 | .dout(faw2_cnt[4:0]), |
| 268 | // .en(drif_sync_frame_req_l), |
| 269 | .l1clk(l1clk), |
| 270 | .siclk(siclk), |
| 271 | .soclk(soclk)); |
| 272 | |
| 273 | assign faw2_cnt_is_zero = (faw2_cnt[4:0] == 5'h0); |
| 274 | |
| 275 | assign faw3_cnt_in[4:0] = faw3_cnt_is_zero & ~faw2_cnt_is_zero & ~faw1_cnt_is_zero & ~faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ? |
| 276 | faw_reg[4:0] - 5'h1 : faw3_cnt_is_zero ? 5'h0 : faw3_cnt[4:0] - 5'h1; |
| 277 | |
| 278 | mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw3_cnt ( |
| 279 | .scan_in(ff_faw3_cnt_scanin), |
| 280 | .scan_out(ff_faw3_cnt_scanout), |
| 281 | .din(faw3_cnt_in[4:0]), |
| 282 | .dout(faw3_cnt[4:0]), |
| 283 | // .en(drif_sync_frame_req_l), |
| 284 | .l1clk(l1clk), |
| 285 | .siclk(siclk), |
| 286 | .soclk(soclk)); |
| 287 | |
| 288 | assign faw3_cnt_is_zero = (faw3_cnt[4:0] == 5'h0); |
| 289 | |
| 290 | assign dmmdly_4_activate_stall = ~faw0_cnt_is_zero & ~faw1_cnt_is_zero & ~faw2_cnt_is_zero & ~faw3_cnt_is_zero; |
| 291 | |
| 292 | mcu_dmmdly_ctl_msff_ctl_macro__width_3 ff_cas_picked ( |
| 293 | .scan_in(ff_cas_picked_scanin), |
| 294 | .scan_out(ff_cas_picked_scanout), |
| 295 | .din({drif_rd_ras_picked,drif_wr_ras_picked,drif_wrbc_ras_picked}), |
| 296 | .dout({dmmdly_rd_cas_picked,dmmdly_wr_cas_picked,dmmdly_wrbc_cas_picked}), |
| 297 | .l1clk(l1clk), |
| 298 | .siclk(siclk), |
| 299 | .soclk(soclk)); |
| 300 | |
| 301 | // fixscan start: |
| 302 | assign ff_rrd_cnt_scanin = scan_in ; |
| 303 | assign ff_rtw_cnt_scanin = ff_rrd_cnt_scanout ; |
| 304 | assign ff_wtr_cnt_scanin = ff_rtw_cnt_scanout ; |
| 305 | assign ff_rtr_cnt_scanin = ff_wtr_cnt_scanout ; |
| 306 | assign ff_wtw_cnt_scanin = ff_rtr_cnt_scanout ; |
| 307 | assign ff_faw0_cnt_scanin = ff_wtw_cnt_scanout ; |
| 308 | assign ff_faw1_cnt_scanin = ff_faw0_cnt_scanout ; |
| 309 | assign ff_faw2_cnt_scanin = ff_faw1_cnt_scanout ; |
| 310 | assign ff_faw3_cnt_scanin = ff_faw2_cnt_scanout ; |
| 311 | assign ff_cas_picked_scanin = ff_faw3_cnt_scanout ; |
| 312 | assign scan_out = ff_cas_picked_scanout ; |
| 313 | // fixscan end: |
| 314 | endmodule |
| 315 | |
| 316 | |
| 317 | |
| 318 | |
| 319 | |
| 320 | |
| 321 | // any PARAMS parms go into naming of macro |
| 322 | |
| 323 | module mcu_dmmdly_ctl_msff_ctl_macro__width_4 ( |
| 324 | din, |
| 325 | l1clk, |
| 326 | scan_in, |
| 327 | siclk, |
| 328 | soclk, |
| 329 | dout, |
| 330 | scan_out); |
| 331 | wire [3:0] fdin; |
| 332 | wire [2:0] so; |
| 333 | |
| 334 | input [3:0] din; |
| 335 | input l1clk; |
| 336 | input scan_in; |
| 337 | |
| 338 | |
| 339 | input siclk; |
| 340 | input soclk; |
| 341 | |
| 342 | output [3:0] dout; |
| 343 | output scan_out; |
| 344 | assign fdin[3:0] = din[3:0]; |
| 345 | |
| 346 | |
| 347 | |
| 348 | |
| 349 | |
| 350 | |
| 351 | dff #(4) d0_0 ( |
| 352 | .l1clk(l1clk), |
| 353 | .siclk(siclk), |
| 354 | .soclk(soclk), |
| 355 | .d(fdin[3:0]), |
| 356 | .si({scan_in,so[2:0]}), |
| 357 | .so({so[2:0],scan_out}), |
| 358 | .q(dout[3:0]) |
| 359 | ); |
| 360 | |
| 361 | |
| 362 | |
| 363 | |
| 364 | |
| 365 | |
| 366 | |
| 367 | |
| 368 | |
| 369 | |
| 370 | |
| 371 | |
| 372 | endmodule |
| 373 | |
| 374 | |
| 375 | |
| 376 | |
| 377 | |
| 378 | |
| 379 | |
| 380 | |
| 381 | |
| 382 | |
| 383 | |
| 384 | |
| 385 | |
| 386 | // any PARAMS parms go into naming of macro |
| 387 | |
| 388 | module mcu_dmmdly_ctl_msff_ctl_macro__width_1 ( |
| 389 | din, |
| 390 | l1clk, |
| 391 | scan_in, |
| 392 | siclk, |
| 393 | soclk, |
| 394 | dout, |
| 395 | scan_out); |
| 396 | wire [0:0] fdin; |
| 397 | |
| 398 | input [0:0] din; |
| 399 | input l1clk; |
| 400 | input scan_in; |
| 401 | |
| 402 | |
| 403 | input siclk; |
| 404 | input soclk; |
| 405 | |
| 406 | output [0:0] dout; |
| 407 | output scan_out; |
| 408 | assign fdin[0:0] = din[0:0]; |
| 409 | |
| 410 | |
| 411 | |
| 412 | |
| 413 | |
| 414 | |
| 415 | dff #(1) d0_0 ( |
| 416 | .l1clk(l1clk), |
| 417 | .siclk(siclk), |
| 418 | .soclk(soclk), |
| 419 | .d(fdin[0:0]), |
| 420 | .si(scan_in), |
| 421 | .so(scan_out), |
| 422 | .q(dout[0:0]) |
| 423 | ); |
| 424 | |
| 425 | |
| 426 | |
| 427 | |
| 428 | |
| 429 | |
| 430 | |
| 431 | |
| 432 | |
| 433 | |
| 434 | |
| 435 | |
| 436 | endmodule |
| 437 | |
| 438 | |
| 439 | |
| 440 | |
| 441 | |
| 442 | |
| 443 | |
| 444 | |
| 445 | |
| 446 | |
| 447 | |
| 448 | |
| 449 | |
| 450 | // any PARAMS parms go into naming of macro |
| 451 | |
| 452 | module mcu_dmmdly_ctl_msff_ctl_macro__width_2 ( |
| 453 | din, |
| 454 | l1clk, |
| 455 | scan_in, |
| 456 | siclk, |
| 457 | soclk, |
| 458 | dout, |
| 459 | scan_out); |
| 460 | wire [1:0] fdin; |
| 461 | wire [0:0] so; |
| 462 | |
| 463 | input [1:0] din; |
| 464 | input l1clk; |
| 465 | input scan_in; |
| 466 | |
| 467 | |
| 468 | input siclk; |
| 469 | input soclk; |
| 470 | |
| 471 | output [1:0] dout; |
| 472 | output scan_out; |
| 473 | assign fdin[1:0] = din[1:0]; |
| 474 | |
| 475 | |
| 476 | |
| 477 | |
| 478 | |
| 479 | |
| 480 | dff #(2) d0_0 ( |
| 481 | .l1clk(l1clk), |
| 482 | .siclk(siclk), |
| 483 | .soclk(soclk), |
| 484 | .d(fdin[1:0]), |
| 485 | .si({scan_in,so[0:0]}), |
| 486 | .so({so[0:0],scan_out}), |
| 487 | .q(dout[1:0]) |
| 488 | ); |
| 489 | |
| 490 | |
| 491 | |
| 492 | |
| 493 | |
| 494 | |
| 495 | |
| 496 | |
| 497 | |
| 498 | |
| 499 | |
| 500 | |
| 501 | endmodule |
| 502 | |
| 503 | |
| 504 | |
| 505 | |
| 506 | |
| 507 | |
| 508 | |
| 509 | |
| 510 | |
| 511 | |
| 512 | |
| 513 | |
| 514 | |
| 515 | // any PARAMS parms go into naming of macro |
| 516 | |
| 517 | module mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ( |
| 518 | din, |
| 519 | l1clk, |
| 520 | scan_in, |
| 521 | siclk, |
| 522 | soclk, |
| 523 | dout, |
| 524 | scan_out); |
| 525 | wire [4:0] fdin; |
| 526 | wire [3:0] so; |
| 527 | |
| 528 | input [4:0] din; |
| 529 | input l1clk; |
| 530 | input scan_in; |
| 531 | |
| 532 | |
| 533 | input siclk; |
| 534 | input soclk; |
| 535 | |
| 536 | output [4:0] dout; |
| 537 | output scan_out; |
| 538 | assign fdin[4:0] = din[4:0]; |
| 539 | |
| 540 | |
| 541 | |
| 542 | |
| 543 | |
| 544 | |
| 545 | dff #(5) d0_0 ( |
| 546 | .l1clk(l1clk), |
| 547 | .siclk(siclk), |
| 548 | .soclk(soclk), |
| 549 | .d(fdin[4:0]), |
| 550 | .si({scan_in,so[3:0]}), |
| 551 | .so({so[3:0],scan_out}), |
| 552 | .q(dout[4:0]) |
| 553 | ); |
| 554 | |
| 555 | |
| 556 | |
| 557 | |
| 558 | |
| 559 | |
| 560 | |
| 561 | |
| 562 | |
| 563 | |
| 564 | |
| 565 | |
| 566 | endmodule |
| 567 | |
| 568 | |
| 569 | |
| 570 | |
| 571 | |
| 572 | |
| 573 | |
| 574 | |
| 575 | |
| 576 | |
| 577 | |
| 578 | |
| 579 | |
| 580 | // any PARAMS parms go into naming of macro |
| 581 | |
| 582 | module mcu_dmmdly_ctl_msff_ctl_macro__width_3 ( |
| 583 | din, |
| 584 | l1clk, |
| 585 | scan_in, |
| 586 | siclk, |
| 587 | soclk, |
| 588 | dout, |
| 589 | scan_out); |
| 590 | wire [2:0] fdin; |
| 591 | wire [1:0] so; |
| 592 | |
| 593 | input [2:0] din; |
| 594 | input l1clk; |
| 595 | input scan_in; |
| 596 | |
| 597 | |
| 598 | input siclk; |
| 599 | input soclk; |
| 600 | |
| 601 | output [2:0] dout; |
| 602 | output scan_out; |
| 603 | assign fdin[2:0] = din[2:0]; |
| 604 | |
| 605 | |
| 606 | |
| 607 | |
| 608 | |
| 609 | |
| 610 | dff #(3) d0_0 ( |
| 611 | .l1clk(l1clk), |
| 612 | .siclk(siclk), |
| 613 | .soclk(soclk), |
| 614 | .d(fdin[2:0]), |
| 615 | .si({scan_in,so[1:0]}), |
| 616 | .so({so[1:0],scan_out}), |
| 617 | .q(dout[2:0]) |
| 618 | ); |
| 619 | |
| 620 | |
| 621 | |
| 622 | |
| 623 | |
| 624 | |
| 625 | |
| 626 | |
| 627 | |
| 628 | |
| 629 | |
| 630 | |
| 631 | endmodule |
| 632 | |
| 633 | |
| 634 | |
| 635 | |
| 636 | |
| 637 | |
| 638 | |
| 639 | |