// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: mcu_dmmdly_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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// ========== Copyright Header End ============================================
wire dmmdly_rd_cas_picked;
wire dmmdly_wr_cas_picked;
wire dmmdly_wrbc_cas_picked;
wire ff_faw0_cnt_scanout;
wire ff_faw1_cnt_scanout;
wire ff_faw2_cnt_scanout;
wire ff_faw3_cnt_scanout;
wire ff_cas_picked_scanin;
wire ff_cas_picked_scanout;
output dmmdly_4_activate_stall;
input drif_rd_ras_picked;
input drif_wr_ras_picked;
input drif_wrbc_ras_picked;
input fbdic_sync_frame_req_l;
assign drif_ras_picked = drif_rd_ras_picked | drif_wr_ras_picked;
// ras to ras (bankA to bankB) delay timer.
assign rrd_cnt_next[3:0] = drif_ras_picked & rrd_cnt_is_zero ? rrd_reg[3:0] - 4'h1 :
drif_wrbc_ras_picked & rrd_cnt_is_zero ? rrd_reg[3:0] :
(rrd_cnt[3:0] == 4'h0) ? 4'h0 :
fbdic_sync_frame_req_l ? rrd_cnt[3:0] - 4'h1 : rrd_cnt[3:0];
mcu_dmmdly_ctl_msff_ctl_macro__width_4 ff_rrd_cnt (
.scan_in(ff_rrd_cnt_scanin),
.scan_out(ff_rrd_cnt_scanout),
assign rrd_cnt_is_zero = (rrd_cnt[3:0] == 4'h0);
// read to write cas to cas (bankA to bankA/bankB) delay timer for not clashing read and write data.
// If read is picked during cas assert rtw_cnt to regular cnt + rtw delay.
assign rtw_cnt_next[3:0] = drif_rd_ras_picked ? rtw_reg[3:0] :
(rtw_cnt[3:0] == 4'h0) ? 4'h0 :
fbdic_sync_frame_req_l ? rtw_cnt[3:0] - 4'h1 : rtw_cnt[3:0];
mcu_dmmdly_ctl_msff_ctl_macro__width_4 ff_rtw_cnt (
.scan_in(ff_rtw_cnt_scanin),
.scan_out(ff_rtw_cnt_scanout),
assign rtw_cnt_is_zero = (rtw_cnt[3:0] == 4'h0);
// write to read cas to cas (bankA to bankA/bankB) delay timer for not clashing read and write data.
assign wtr_cnt_next[3:0] = drif_wr_ras_picked ? wtr_reg[3:0] :
drif_wrbc_ras_picked ? wtr_reg[3:0] + 4'h1:
(wtr_cnt[3:0] == 4'h0) ? 4'h0 :
fbdic_sync_frame_req_l ? wtr_cnt[3:0] - 4'h1 : wtr_cnt[3:0];
mcu_dmmdly_ctl_msff_ctl_macro__width_4 ff_wtr_cnt (
.scan_in(ff_wtr_cnt_scanin),
.scan_out(ff_wtr_cnt_scanout),
assign wtr_cnt_is_zero = (wtr_cnt[3:0] == 4'h0);
// read to read cas to cas (bankA to bankA/bankB) delay timer for not clashing read data.
assign rtr_cnt_next = dmmdly_rd_cas_picked & fbdic_sync_frame_req_l ? 1'h1 :
(rtr_cnt == 1'h0) ? 1'h0 : rtr_cnt - 1'h1;
mcu_dmmdly_ctl_msff_ctl_macro__width_1 ff_rtr_cnt (
.scan_in(ff_rtr_cnt_scanin),
.scan_out(ff_rtr_cnt_scanout),
assign rtr_cnt_is_zero = (rtr_cnt == 1'h0);
// write to write cas to cas (bankA to bankA/bankB) delay timer for not clashing store data.
assign wtw_cnt_next[1:0] = dmmdly_wr_cas_picked & fbdic_sync_frame_req_l ? 2'h1 :
dmmdly_wrbc_cas_picked & fbdic_sync_frame_req_l ? 2'h1 :
(wtw_cnt[1:0] == 2'h0) ? 2'h0 : wtw_cnt[1:0] - 2'h1;
mcu_dmmdly_ctl_msff_ctl_macro__width_2 ff_wtw_cnt (
.scan_in(ff_wtw_cnt_scanin),
.scan_out(ff_wtw_cnt_scanout),
assign wtw_cnt_is_zero = (wtw_cnt[1:0] == 2'h0);
//////////////////////////////////////////////////////////////////
// Limit number of activates within tFAW to 4
// Whenever an activate cmd is detected, a counter is started at
// the tFAW value. If all four counters are active, then the scheduler
// is stalled until one becomes inactive.
//////////////////////////////////////////////////////////////////
assign drif_activate_cmd = drif_rd_ras_picked | drif_wr_ras_picked | drif_wrbc_ras_picked;
assign faw0_cnt_in[4:0] = faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ? faw_reg[4:0] - 5'h1 :
faw0_cnt_is_zero ? 5'h0 : faw0_cnt[4:0] - 5'h1;
mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw0_cnt (
.scan_in(ff_faw0_cnt_scanin),
.scan_out(ff_faw0_cnt_scanout),
// .en(drif_sync_frame_req_l),
assign faw0_cnt_is_zero = (faw0_cnt[4:0] == 5'h0);
assign faw1_cnt_in[4:0] = faw1_cnt_is_zero & ~faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ? faw_reg[4:0] - 5'h1 :
faw1_cnt_is_zero ? 5'h0 : faw1_cnt[4:0] - 5'h1;
mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw1_cnt (
.scan_in(ff_faw1_cnt_scanin),
.scan_out(ff_faw1_cnt_scanout),
// .en(drif_sync_frame_req_l),
assign faw1_cnt_is_zero = (faw1_cnt[4:0] == 5'h0);
assign faw2_cnt_in[4:0] = faw2_cnt_is_zero & ~faw1_cnt_is_zero & ~faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ? faw_reg[4:0] - 5'h1 :
faw2_cnt_is_zero ? 5'h0 : faw2_cnt[4:0] - 5'h1;
mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw2_cnt (
.scan_in(ff_faw2_cnt_scanin),
.scan_out(ff_faw2_cnt_scanout),
// .en(drif_sync_frame_req_l),
assign faw2_cnt_is_zero = (faw2_cnt[4:0] == 5'h0);
assign faw3_cnt_in[4:0] = faw3_cnt_is_zero & ~faw2_cnt_is_zero & ~faw1_cnt_is_zero & ~faw0_cnt_is_zero & drif_activate_cmd & fbdic_sync_frame_req_l ?
faw_reg[4:0] - 5'h1 : faw3_cnt_is_zero ? 5'h0 : faw3_cnt[4:0] - 5'h1;
mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 ff_faw3_cnt (
.scan_in(ff_faw3_cnt_scanin),
.scan_out(ff_faw3_cnt_scanout),
// .en(drif_sync_frame_req_l),
assign faw3_cnt_is_zero = (faw3_cnt[4:0] == 5'h0);
assign dmmdly_4_activate_stall = ~faw0_cnt_is_zero & ~faw1_cnt_is_zero & ~faw2_cnt_is_zero & ~faw3_cnt_is_zero;
mcu_dmmdly_ctl_msff_ctl_macro__width_3 ff_cas_picked (
.scan_in(ff_cas_picked_scanin),
.scan_out(ff_cas_picked_scanout),
.din({drif_rd_ras_picked,drif_wr_ras_picked,drif_wrbc_ras_picked}),
.dout({dmmdly_rd_cas_picked,dmmdly_wr_cas_picked,dmmdly_wrbc_cas_picked}),
assign ff_rrd_cnt_scanin = scan_in ;
assign ff_rtw_cnt_scanin = ff_rrd_cnt_scanout ;
assign ff_wtr_cnt_scanin = ff_rtw_cnt_scanout ;
assign ff_rtr_cnt_scanin = ff_wtr_cnt_scanout ;
assign ff_wtw_cnt_scanin = ff_rtr_cnt_scanout ;
assign ff_faw0_cnt_scanin = ff_wtw_cnt_scanout ;
assign ff_faw1_cnt_scanin = ff_faw0_cnt_scanout ;
assign ff_faw2_cnt_scanin = ff_faw1_cnt_scanout ;
assign ff_faw3_cnt_scanin = ff_faw2_cnt_scanout ;
assign ff_cas_picked_scanin = ff_faw3_cnt_scanout ;
assign scan_out = ff_cas_picked_scanout ;
// any PARAMS parms go into naming of macro
module mcu_dmmdly_ctl_msff_ctl_macro__width_4 (
assign fdin[3:0] = din[3:0];
// any PARAMS parms go into naming of macro
module mcu_dmmdly_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module mcu_dmmdly_ctl_msff_ctl_macro__width_2 (
assign fdin[1:0] = din[1:0];
// any PARAMS parms go into naming of macro
module mcu_dmmdly_ctl_msff_ctl_macro__en_0__width_5 (
assign fdin[4:0] = din[4:0];
// any PARAMS parms go into naming of macro
module mcu_dmmdly_ctl_msff_ctl_macro__width_3 (
assign fdin[2:0] = din[2:0];