| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: MDIO2P_FRMR.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | //////////////////////////////////////////////////////////////////////////////// |
| 36 | // |
| 37 | // Copyright (c) 2003 Texas Instruments, Inc. |
| 38 | // All rights reserved |
| 39 | // |
| 40 | // This is an unpublished work created in the year stated above. |
| 41 | // Texas Instruments owns all rights in and to the work and intends to |
| 42 | // maintain it and protect it as unpublished copyright. In the event |
| 43 | // of either inadvertant or deliberate publication, the above stated |
| 44 | // date shall be treated as the year of first publication. In the event |
| 45 | // of such publication, Texas Instruments intends to enforce its rights |
| 46 | // in the work under the copyright laws as a published work. |
| 47 | // |
| 48 | // These commodities are under U.S. Government distribution license |
| 49 | // control. As such, they are not be re-exported without prior approval |
| 50 | // from the U.S. Department of Commerce. |
| 51 | // |
| 52 | //////////////////////////////////////////////////////////////////////////////// |
| 53 | |
| 54 | //////////////////////////////////////////////////////////////////////////////// |
| 55 | // |
| 56 | // FUNCTION: Identify MDIO Frames, and identify keys cycles within each |
| 57 | // frame |
| 58 | // COMMENTS: Uses a 6-bit LFSR to map out the MDIO frame. Cycles within the |
| 59 | // frame are identified as follows: |
| 60 | // |
| 61 | // Cycle MDIO Code Parameter Comment |
| 62 | // ----- ---- ------ --------- ------------------- |
| 63 | // - 1 000000 frmr_WT >= 32 bits of preamble complete |
| 64 | // - 1 110010 frmr_PRE Start of Preamble |
| 65 | // 0 1 100100 . |
| 66 | // 1 0/1 001001 frmr_SOF Clause specifier |
| 67 | // 2 OP 010010 Opcode |
| 68 | // 3 OP 100101 Opcode |
| 69 | // 4 PA 001011 Port Address |
| 70 | // 5 PA 010110 . |
| 71 | // 6 PA 101101 . |
| 72 | // 7 PA 011011 . |
| 73 | // 8 PA 110111 . |
| 74 | // 9 DA 101110 Device Address |
| 75 | // 10 DA 011101 . |
| 76 | // 11 DA 111011 . |
| 77 | // 12 DA 110110 . |
| 78 | // 13 DA 101100 . |
| 79 | // 14 1/Z 011001 frmr_ADD Z on reads, 1 on writes |
| 80 | // 15 0 110011 frmr_TA Turn around |
| 81 | // 16 D 100110 Data |
| 82 | // 17 D 001101 . |
| 83 | // 18 D 011010 . |
| 84 | // 19 D 110101 . |
| 85 | // 20 D 101010 . |
| 86 | // 21 D 010101 . |
| 87 | // 22 D 101011 . |
| 88 | // 23 D 010111 . |
| 89 | // 24 D 101111 . |
| 90 | // 25 D 011111 . |
| 91 | // 26 D 111111 . |
| 92 | // 27 D 111110 . |
| 93 | // 28 D 111100 . |
| 94 | // 29 D 111000 . |
| 95 | // 30 D 110000 . |
| 96 | // 31 D 100000 frmr_EOF End of frame |
| 97 | // |
| 98 | // VERSION: #VERSION# |
| 99 | // DATE: #DATE# |
| 100 | // |
| 101 | // Date Author Changes |
| 102 | // ------- ------ ----------------------------------------------------- |
| 103 | // 27Jan05 Andre Asynchronous reset removed |
| 104 | // |
| 105 | //////////////////////////////////////////////////////////////////////////////// |
| 106 | |
| 107 | `timescale 1ns / 1ps |
| 108 | |
| 109 | module MDIO2P_FRMR |
| 110 | ( |
| 111 | IO_MDCLK, |
| 112 | IO_RESET, |
| 113 | MDIN, |
| 114 | FRMR_STATE |
| 115 | ); |
| 116 | |
| 117 | //////////////////////////////////////////////////////////////////////////////// |
| 118 | // |
| 119 | // Port Declarations |
| 120 | // |
| 121 | //////////////////////////////////////////////////////////////////////////////// |
| 122 | |
| 123 | input IO_RESET; // Global reset |
| 124 | |
| 125 | // MDIO Interface |
| 126 | input IO_MDCLK; // Clock |
| 127 | input MDIN; // Data in |
| 128 | |
| 129 | // Interface to Framer |
| 130 | output[5:0] FRMR_STATE; // LFSR encoded frame state |
| 131 | |
| 132 | |
| 133 | //////////////////////////////////////////////////////////////////////////////// |
| 134 | // |
| 135 | // Outputs which are not wires |
| 136 | // |
| 137 | //////////////////////////////////////////////////////////////////////////////// |
| 138 | |
| 139 | |
| 140 | //////////////////////////////////////////////////////////////////////////////// |
| 141 | // |
| 142 | // Parameters for frame sequencing |
| 143 | // |
| 144 | //////////////////////////////////////////////////////////////////////////////// |
| 145 | |
| 146 | parameter frmr_WT = 6'b000000; |
| 147 | parameter frmr_PRE = 6'b110010; |
| 148 | parameter frmr_SOF = 6'b001001; |
| 149 | parameter frmr_EOF = 6'b100000; |
| 150 | |
| 151 | |
| 152 | //////////////////////////////////////////////////////////////////////////////// |
| 153 | // |
| 154 | // Internal Declarations |
| 155 | // |
| 156 | //////////////////////////////////////////////////////////////////////////////// |
| 157 | |
| 158 | // Flops |
| 159 | reg[5:0] state; |
| 160 | reg preamble; // Preamble in progress |
| 161 | |
| 162 | // Combinatorials |
| 163 | wire frame_done; // EOF state decode |
| 164 | wire preamble_done; // Preamble at least 32 cycles long |
| 165 | |
| 166 | |
| 167 | //////////////////////////////////////////////////////////////////////////////// |
| 168 | // |
| 169 | // Framer |
| 170 | // - Frame requires 32 states. |
| 171 | // - Frames start with a 0 on MDIN, and can repeat back to back. |
| 172 | // - Preamble is arbitrarily long, during which LFSR is held at zero. |
| 173 | // - Starting position is chosen to make force to zero as simple as possible |
| 174 | // |
| 175 | //////////////////////////////////////////////////////////////////////////////// |
| 176 | |
| 177 | assign frame_done = (state == frmr_EOF); |
| 178 | assign preamble_done = frame_done | (state == frmr_WT); |
| 179 | |
| 180 | always @(posedge IO_MDCLK) |
| 181 | begin |
| 182 | if(IO_RESET) |
| 183 | begin |
| 184 | state <= frmr_PRE; |
| 185 | preamble <= 1'b1; |
| 186 | end |
| 187 | else if(preamble & ~preamble_done & ~MDIN) |
| 188 | state <= frmr_PRE; |
| 189 | else if(preamble & preamble_done & MDIN) |
| 190 | state <= frmr_WT; |
| 191 | else if(preamble & preamble_done & ~MDIN) |
| 192 | begin |
| 193 | state <= frmr_SOF; |
| 194 | preamble <= ~preamble; |
| 195 | end |
| 196 | else if(frame_done) |
| 197 | begin |
| 198 | state <= frmr_PRE; |
| 199 | preamble <= ~preamble; |
| 200 | end |
| 201 | else |
| 202 | state <= {state[4:0], state[5] ^ state[4]}; |
| 203 | end |
| 204 | |
| 205 | |
| 206 | //////////////////////////////////////////////////////////////////////////////// |
| 207 | // |
| 208 | // Output Assignments |
| 209 | // |
| 210 | //////////////////////////////////////////////////////////////////////////////// |
| 211 | |
| 212 | assign FRMR_STATE = preamble ? 5'b0 : state; |
| 213 | |
| 214 | endmodule |