// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: MDIO2P_FRMR.v
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2003 Texas Instruments, Inc.
// This is an unpublished work created in the year stated above.
// Texas Instruments owns all rights in and to the work and intends to
// maintain it and protect it as unpublished copyright. In the event
// of either inadvertant or deliberate publication, the above stated
// date shall be treated as the year of first publication. In the event
// of such publication, Texas Instruments intends to enforce its rights
// in the work under the copyright laws as a published work.
// These commodities are under U.S. Government distribution license
// control. As such, they are not be re-exported without prior approval
// from the U.S. Department of Commerce.
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// FUNCTION: Identify MDIO Frames, and identify keys cycles within each
// COMMENTS: Uses a 6-bit LFSR to map out the MDIO frame. Cycles within the
// frame are identified as follows:
// Cycle MDIO Code Parameter Comment
// ----- ---- ------ --------- -------------------
// - 1 000000 frmr_WT >= 32 bits of preamble complete
// - 1 110010 frmr_PRE Start of Preamble
// 1 0/1 001001 frmr_SOF Clause specifier
// 4 PA 001011 Port Address
// 9 DA 101110 Device Address
// 14 1/Z 011001 frmr_ADD Z on reads, 1 on writes
// 15 0 110011 frmr_TA Turn around
// 31 D 100000 frmr_EOF End of frame
// ------- ------ -----------------------------------------------------
// 27Jan05 Andre Asynchronous reset removed
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
input IO_RESET; // Global reset
output[5:0] FRMR_STATE; // LFSR encoded frame state
////////////////////////////////////////////////////////////////////////////////
// Outputs which are not wires
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Parameters for frame sequencing
////////////////////////////////////////////////////////////////////////////////
parameter frmr_WT = 6'b000000;
parameter frmr_PRE = 6'b110010;
parameter frmr_SOF = 6'b001001;
parameter frmr_EOF = 6'b100000;
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
reg preamble; // Preamble in progress
wire frame_done; // EOF state decode
wire preamble_done; // Preamble at least 32 cycles long
////////////////////////////////////////////////////////////////////////////////
// - Frame requires 32 states.
// - Frames start with a 0 on MDIN, and can repeat back to back.
// - Preamble is arbitrarily long, during which LFSR is held at zero.
// - Starting position is chosen to make force to zero as simple as possible
////////////////////////////////////////////////////////////////////////////////
assign frame_done = (state == frmr_EOF);
assign preamble_done = frame_done | (state == frmr_WT);
always @(posedge IO_MDCLK)
else if(preamble & ~preamble_done & ~MDIN)
else if(preamble & preamble_done & MDIN)
else if(preamble & preamble_done & ~MDIN)
state <= {state[4:0], state[5] ^ state[4]};
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
assign FRMR_STATE = preamble ? 5'b0 : state;