| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: P2REGS_CFG_STS.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | //////////////////////////////////////////////////////////////////////////////// |
| 36 | // |
| 37 | // Copyright (c) 2004 Texas Instruments, Inc. |
| 38 | // All rights reserved |
| 39 | // |
| 40 | // This is an unpublished work created in the year stated above. |
| 41 | // Texas Instruments owns all rights in and to the work and intends to |
| 42 | // maintain it and protect it as unpublished copyright. In the event |
| 43 | // of either inadvertant or deliberate publication, the above stated |
| 44 | // date shall be treated as the year of first publication. In the event |
| 45 | // of such publication, Texas Instruments intends to enforce its rights |
| 46 | // in the work under the copyright laws as a published work. |
| 47 | // |
| 48 | // These commodities are under U.S. Government distribution license |
| 49 | // control. As such, they are not be re-exported without prior approval |
| 50 | // from the U.S. Department of Commerce. |
| 51 | // |
| 52 | //////////////////////////////////////////////////////////////////////////////// |
| 53 | // *********************************************************************** |
| 54 | // |
| 55 | // File: P2REGS_CFG_STS.v |
| 56 | // |
| 57 | // Author: Andre Szczepanek |
| 58 | // |
| 59 | // Purpose: CFG/STS register block |
| 60 | // |
| 61 | // |
| 62 | // Date Author Changes |
| 63 | // ------- ------ ----------------------------------------------------- |
| 64 | // 21May04 Andre Created |
| 65 | // 27Jan05 Andre Asynchronous reset removed |
| 66 | // 31Jan05 Andre Asynchronous sticky input removed |
| 67 | // |
| 68 | // *********************************************************************** |
| 69 | //////////////////////////////////////////////////////////////////////////////// |
| 70 | // |
| 71 | // ____ ____ ___ |
| 72 | // MDCLK ___/ \____/ \____/ |
| 73 | // _________ |
| 74 | // PW XXXXX_________/ XXX |
| 75 | // _________ _________ |
| 76 | // PA XXXXX____A1___X____A2___XXX |
| 77 | // _________ |
| 78 | // PR XXXXX_________/ XXX |
| 79 | // _________ |
| 80 | // WRITE_DATA XXXXXXXXXXXXXXX____Q1___XXX |
| 81 | // ___ |
| 82 | // READ_DATA XXXXXXXXXXXXXXXXXXXXX<D2_>X |
| 83 | // |
| 84 | //////////////////////////////////////////////////////////////////////////////// |
| 85 | |
| 86 | `timescale 1ns / 1ps |
| 87 | |
| 88 | module P2REGS_CFG_STS |
| 89 | ( |
| 90 | RESET, |
| 91 | MDCLK, |
| 92 | WDCLK, |
| 93 | PW, |
| 94 | PR, |
| 95 | PA, |
| 96 | READ_DATA, |
| 97 | WRITE_DATA, |
| 98 | CONFIG_BUS, |
| 99 | STATUS_BUS |
| 100 | ); |
| 101 | |
| 102 | |
| 103 | //////////////////////////////////////////////////////////////////////////////// |
| 104 | // |
| 105 | // Parameters |
| 106 | // |
| 107 | //////////////////////////////////////////////////////////////////////////////// |
| 108 | |
| 109 | parameter cfg_width=32; // (default) config bus width |
| 110 | parameter cfg_reset=32'h5555_5555; // (default) config reg reset value |
| 111 | parameter cfg_instn=32'h0000_000f; // (default) config reg bit instantiations |
| 112 | |
| 113 | parameter sts_width=32; // (default) status bus width |
| 114 | parameter sts_reset=32'h5555_5555; // (default) status reg reset value |
| 115 | parameter sts_instn=32'h0000_000f; // (default) status reg bit instantiations |
| 116 | parameter sts_stiky=32'h0000_0001; // (default) status sticky reg bits |
| 117 | |
| 118 | //////////////////////////////////////////////////////////////////////////////// |
| 119 | // |
| 120 | // Port Declarations |
| 121 | // |
| 122 | //////////////////////////////////////////////////////////////////////////////// |
| 123 | |
| 124 | |
| 125 | // MDIO Interface |
| 126 | input RESET; // Global reset |
| 127 | input MDCLK; // MDIO Clock |
| 128 | input WDCLK; // WORD Clock |
| 129 | |
| 130 | // Parallel Interface to MDIO framer |
| 131 | input PW; // Write enable |
| 132 | input PR; // Read enable |
| 133 | input [1:0] PA; // LSB of Address |
| 134 | input [15:0] WRITE_DATA; // Data in |
| 135 | output[15:0] READ_DATA; // Data out |
| 136 | |
| 137 | |
| 138 | // Interface to MACRO |
| 139 | output[cfg_width-1:0] CONFIG_BUS; // Config bus output to Macro |
| 140 | input [sts_width-1:0] STATUS_BUS; // Status bus from Macro |
| 141 | |
| 142 | |
| 143 | |
| 144 | |
| 145 | //////////////////////////////////////////////////////////////////////////////// |
| 146 | // |
| 147 | // Internal Declarations |
| 148 | // |
| 149 | //////////////////////////////////////////////////////////////////////////////// |
| 150 | |
| 151 | // Flops |
| 152 | reg [31:0] this_config_reg; // This value for config register |
| 153 | reg [31:0] this_status_reg; // This value for status register |
| 154 | |
| 155 | |
| 156 | // Combinatorials |
| 157 | reg [31:0] new__config_reg; // New value for config register |
| 158 | wire [31:0] next_config_reg; // Next value for config register |
| 159 | reg [31:0] new__status_reg; // New value for status register |
| 160 | wire [31:0] new2_status_reg; // New value for status register |
| 161 | wire [31:0] next_status_reg; // Next value for status register |
| 162 | |
| 163 | wire [31:0] inst_config_reg; // Value of config reg with non-instanced bits masked |
| 164 | wire [31:0] inst_status_reg; // Value of status reg with non-instanced bits masked |
| 165 | |
| 166 | |
| 167 | // WDCLK Latches |
| 168 | wire [31:0] wd_sr_set, wd_sr_reset; // set/reset inputs |
| 169 | wire [31:0] next_wd_sr_reg; // WDCLK Set/Reset Latch |
| 170 | reg [31:0] this_wd_sr_reg; // WDCLK Set/Reset Latch |
| 171 | wire [31:0] next_wd_sync_0; // Sync to WDCLK Domain stage 0 |
| 172 | reg [31:0] this_wd_sync_0; // Sync to WDCLK Domain stage 0 |
| 173 | reg [31:0] this_wd_sync_1; // Sync to WDCLK Domain stage 1 |
| 174 | |
| 175 | // MDCLK Latches |
| 176 | wire [31:0] md_sr_set, md_sr_reset; // set/reset inputs |
| 177 | wire [31:0] next_md_sr_reg; // MDCLK Set/Reset Latch |
| 178 | reg [31:0] this_md_sr_reg; // MDCLK Set/Reset Latch |
| 179 | wire [31:0] next_md_sync_0; // Sync to MDCLK Domain stage 0 |
| 180 | reg [31:0] this_md_sync_0; // Sync to MDCLK Domain stage 0 |
| 181 | |
| 182 | |
| 183 | //////////////////////////////////////////////////////////////////////////////// |
| 184 | // |
| 185 | // Write register |
| 186 | // |
| 187 | //////////////////////////////////////////////////////////////////////////////// |
| 188 | |
| 189 | always @(PW or PA or WRITE_DATA or this_config_reg) |
| 190 | begin |
| 191 | // defaults |
| 192 | new__config_reg = this_config_reg; |
| 193 | |
| 194 | // MDIO register writes to low and high locations |
| 195 | // |
| 196 | if (PW & ~PA[1] & ~PA[0]) |
| 197 | new__config_reg[15:0] = WRITE_DATA; |
| 198 | else if (PW & ~PA[1] & PA[0]) |
| 199 | new__config_reg[31:16] = WRITE_DATA; |
| 200 | end |
| 201 | |
| 202 | // Force reset values on uninstantiated bits |
| 203 | // |
| 204 | // cfg_instn is bit mask indicating bits to instantiate |
| 205 | // cfg_reset is bit mask indicating register reset values |
| 206 | // |
| 207 | assign next_config_reg = (new__config_reg & cfg_instn) | (cfg_reset & ~cfg_instn); |
| 208 | |
| 209 | |
| 210 | |
| 211 | //////////////////////////////////////////////////////////////////////////////// |
| 212 | // |
| 213 | // Sequential registers for config |
| 214 | // |
| 215 | //////////////////////////////////////////////////////////////////////////////// |
| 216 | |
| 217 | always @(posedge MDCLK) |
| 218 | begin |
| 219 | if(RESET) |
| 220 | begin |
| 221 | this_config_reg <= cfg_reset; |
| 222 | end |
| 223 | else |
| 224 | begin |
| 225 | this_config_reg <= next_config_reg; |
| 226 | end |
| 227 | end |
| 228 | |
| 229 | assign inst_config_reg = (this_config_reg & cfg_instn) | (cfg_reset & ~cfg_instn); |
| 230 | |
| 231 | |
| 232 | //////////////////////////////////////////////////////////////////////////////// |
| 233 | // |
| 234 | // Load STS register |
| 235 | // |
| 236 | //////////////////////////////////////////////////////////////////////////////// |
| 237 | |
| 238 | always @(STATUS_BUS) |
| 239 | begin |
| 240 | // defaults |
| 241 | new__status_reg = sts_reset; |
| 242 | |
| 243 | new__status_reg[sts_width-1:0] = STATUS_BUS; |
| 244 | |
| 245 | end |
| 246 | |
| 247 | // Selected Synced SR latch value for sticky bits |
| 248 | // |
| 249 | // sts_stiky is bit mask indicating bits that are sticky |
| 250 | // |
| 251 | assign new2_status_reg = (this_md_sync_0 & sts_stiky) | (new__status_reg & ~sts_stiky); |
| 252 | |
| 253 | // Force reset values on uninstantiated bits |
| 254 | // |
| 255 | // sts_instn is bit mask indicating bits to instantiate |
| 256 | // sts_reset is bit mask indicating register reset values |
| 257 | // |
| 258 | assign next_status_reg = (new2_status_reg & sts_instn) | (sts_reset & ~sts_instn); |
| 259 | |
| 260 | // Create Reset signal for sticky bits |
| 261 | // |
| 262 | // sts_clr is a bit mask indicating bits to clear (synchronous to MDCLK)) |
| 263 | // |
| 264 | wire [31:0] sts_clr = sts_instn & sts_stiky & {32{PA[1]& ~PA[0] & PR}}; |
| 265 | |
| 266 | |
| 267 | |
| 268 | |
| 269 | |
| 270 | |
| 271 | //////////////////////////////////////////////////////////////////////////////// |
| 272 | // |
| 273 | // WDCLK Domain |
| 274 | // |
| 275 | //////////////////////////////////////////////////////////////////////////////// |
| 276 | |
| 277 | SYNC_CELL RESET_WDCLK_SYNC_CELL (.D(RESET),.CP(WDCLK),.Q(RESET_WDCLK)); // loj@8-30-05 |
| 278 | |
| 279 | // Reset over Set synchronous SR latch |
| 280 | // |
| 281 | assign wd_sr_set = new__status_reg; // Status bus pulse input |
| 282 | assign wd_sr_reset = this_wd_sync_1; // Clear on synced read of a 1 on MDIO |
| 283 | assign next_wd_sr_reg = (~wd_sr_reset) & (this_wd_sr_reg | wd_sr_set) & sts_stiky; |
| 284 | |
| 285 | assign next_wd_sync_0 = this_md_sr_reg; |
| 286 | |
| 287 | always @(posedge WDCLK) |
| 288 | begin |
| 289 | if(RESET_WDCLK) // loj@8-30-05 |
| 290 | begin |
| 291 | this_wd_sr_reg <= 32'h0000_0000; |
| 292 | this_wd_sync_0 <= 32'h0000_0000; |
| 293 | this_wd_sync_1 <= 32'h0000_0000; |
| 294 | end |
| 295 | else |
| 296 | begin |
| 297 | this_wd_sr_reg <= next_wd_sr_reg; |
| 298 | this_wd_sync_0 <= next_wd_sync_0; |
| 299 | this_wd_sync_1 <= this_wd_sync_0; |
| 300 | end |
| 301 | end |
| 302 | |
| 303 | |
| 304 | |
| 305 | //////////////////////////////////////////////////////////////////////////////// |
| 306 | // |
| 307 | // MDCLK Domain |
| 308 | // |
| 309 | //////////////////////////////////////////////////////////////////////////////// |
| 310 | |
| 311 | |
| 312 | |
| 313 | // Reset over Set synchronous SR latch |
| 314 | // |
| 315 | assign md_sr_set = this_status_reg & sts_clr & sts_stiky; //STS read clears flag |
| 316 | assign md_sr_reset = ~this_md_sync_0; |
| 317 | assign next_md_sr_reg = (~md_sr_reset) & (this_md_sr_reg | md_sr_set) & sts_stiky; |
| 318 | |
| 319 | assign next_md_sync_0 = this_wd_sr_reg; |
| 320 | |
| 321 | always @(posedge MDCLK) |
| 322 | begin |
| 323 | if(RESET) |
| 324 | begin |
| 325 | this_md_sr_reg <= 32'h0000_0000; |
| 326 | this_md_sync_0 <= 32'h0000_0000; |
| 327 | this_status_reg <= sts_reset; |
| 328 | end |
| 329 | else |
| 330 | begin |
| 331 | this_md_sr_reg <= next_md_sr_reg; |
| 332 | this_md_sync_0 <= next_md_sync_0; |
| 333 | this_status_reg <= next_status_reg; |
| 334 | end |
| 335 | end |
| 336 | |
| 337 | |
| 338 | |
| 339 | //////////////////////////////////////////////////////////////////////////////// |
| 340 | // |
| 341 | // Output Assignments |
| 342 | // |
| 343 | //////////////////////////////////////////////////////////////////////////////// |
| 344 | |
| 345 | assign inst_status_reg = (this_status_reg & sts_instn) | (sts_reset & ~sts_instn); |
| 346 | |
| 347 | assign CONFIG_BUS = inst_config_reg[cfg_width-1:0]; |
| 348 | assign READ_DATA = PA[1] ? (PA[0] ? inst_status_reg[31:16] : inst_status_reg[15:0]) : |
| 349 | (PA[0] ? inst_config_reg[31:16] : inst_config_reg[15:0]) ; |
| 350 | |
| 351 | endmodule |