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// OpenSPARC T2 Processor File: P2REGS_CFG_STS.v
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////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 2004 Texas Instruments, Inc.
// This is an unpublished work created in the year stated above.
// Texas Instruments owns all rights in and to the work and intends to
// maintain it and protect it as unpublished copyright. In the event
// of either inadvertant or deliberate publication, the above stated
// date shall be treated as the year of first publication. In the event
// of such publication, Texas Instruments intends to enforce its rights
// in the work under the copyright laws as a published work.
// These commodities are under U.S. Government distribution license
// control. As such, they are not be re-exported without prior approval
// from the U.S. Department of Commerce.
////////////////////////////////////////////////////////////////////////////////
// ***********************************************************************
// File: P2REGS_CFG_STS.v
// Author: Andre Szczepanek
// Purpose: CFG/STS register block
// ------- ------ -----------------------------------------------------
// 27Jan05 Andre Asynchronous reset removed
// 31Jan05 Andre Asynchronous sticky input removed
// ***********************************************************************
////////////////////////////////////////////////////////////////////////////////
// MDCLK ___/ \____/ \____/
// PW XXXXX_________/ XXX
// PA XXXXX____A1___X____A2___XXX
// PR XXXXX_________/ XXX
// WRITE_DATA XXXXXXXXXXXXXXX____Q1___XXX
// READ_DATA XXXXXXXXXXXXXXXXXXXXX<D2_>X
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
parameter cfg_width=32; // (default) config bus width
parameter cfg_reset=32'h5555_5555; // (default) config reg reset value
parameter cfg_instn=32'h0000_000f; // (default) config reg bit instantiations
parameter sts_width=32; // (default) status bus width
parameter sts_reset=32'h5555_5555; // (default) status reg reset value
parameter sts_instn=32'h0000_000f; // (default) status reg bit instantiations
parameter sts_stiky=32'h0000_0001; // (default) status sticky reg bits
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
input RESET; // Global reset
input MDCLK; // MDIO Clock
input WDCLK; // WORD Clock
// Parallel Interface to MDIO framer
input PW; // Write enable
input [1:0] PA; // LSB of Address
input [15:0] WRITE_DATA; // Data in
output[15:0] READ_DATA; // Data out
output[cfg_width-1:0] CONFIG_BUS; // Config bus output to Macro
input [sts_width-1:0] STATUS_BUS; // Status bus from Macro
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
reg [31:0] this_config_reg; // This value for config register
reg [31:0] this_status_reg; // This value for status register
reg [31:0] new__config_reg; // New value for config register
wire [31:0] next_config_reg; // Next value for config register
reg [31:0] new__status_reg; // New value for status register
wire [31:0] new2_status_reg; // New value for status register
wire [31:0] next_status_reg; // Next value for status register
wire [31:0] inst_config_reg; // Value of config reg with non-instanced bits masked
wire [31:0] inst_status_reg; // Value of status reg with non-instanced bits masked
wire [31:0] wd_sr_set, wd_sr_reset; // set/reset inputs
wire [31:0] next_wd_sr_reg; // WDCLK Set/Reset Latch
reg [31:0] this_wd_sr_reg; // WDCLK Set/Reset Latch
wire [31:0] next_wd_sync_0; // Sync to WDCLK Domain stage 0
reg [31:0] this_wd_sync_0; // Sync to WDCLK Domain stage 0
reg [31:0] this_wd_sync_1; // Sync to WDCLK Domain stage 1
wire [31:0] md_sr_set, md_sr_reset; // set/reset inputs
wire [31:0] next_md_sr_reg; // MDCLK Set/Reset Latch
reg [31:0] this_md_sr_reg; // MDCLK Set/Reset Latch
wire [31:0] next_md_sync_0; // Sync to MDCLK Domain stage 0
reg [31:0] this_md_sync_0; // Sync to MDCLK Domain stage 0
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
always @(PW or PA or WRITE_DATA or this_config_reg)
new__config_reg = this_config_reg;
// MDIO register writes to low and high locations
if (PW & ~PA[1] & ~PA[0])
new__config_reg[15:0] = WRITE_DATA;
else if (PW & ~PA[1] & PA[0])
new__config_reg[31:16] = WRITE_DATA;
// Force reset values on uninstantiated bits
// cfg_instn is bit mask indicating bits to instantiate
// cfg_reset is bit mask indicating register reset values
assign next_config_reg = (new__config_reg & cfg_instn) | (cfg_reset & ~cfg_instn);
////////////////////////////////////////////////////////////////////////////////
// Sequential registers for config
////////////////////////////////////////////////////////////////////////////////
this_config_reg <= cfg_reset;
this_config_reg <= next_config_reg;
assign inst_config_reg = (this_config_reg & cfg_instn) | (cfg_reset & ~cfg_instn);
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
new__status_reg = sts_reset;
new__status_reg[sts_width-1:0] = STATUS_BUS;
// Selected Synced SR latch value for sticky bits
// sts_stiky is bit mask indicating bits that are sticky
assign new2_status_reg = (this_md_sync_0 & sts_stiky) | (new__status_reg & ~sts_stiky);
// Force reset values on uninstantiated bits
// sts_instn is bit mask indicating bits to instantiate
// sts_reset is bit mask indicating register reset values
assign next_status_reg = (new2_status_reg & sts_instn) | (sts_reset & ~sts_instn);
// Create Reset signal for sticky bits
// sts_clr is a bit mask indicating bits to clear (synchronous to MDCLK))
wire [31:0] sts_clr = sts_instn & sts_stiky & {32{PA[1]& ~PA[0] & PR}};
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
SYNC_CELL RESET_WDCLK_SYNC_CELL (.D(RESET),.CP(WDCLK),.Q(RESET_WDCLK)); // loj@8-30-05
// Reset over Set synchronous SR latch
assign wd_sr_set = new__status_reg; // Status bus pulse input
assign wd_sr_reset = this_wd_sync_1; // Clear on synced read of a 1 on MDIO
assign next_wd_sr_reg = (~wd_sr_reset) & (this_wd_sr_reg | wd_sr_set) & sts_stiky;
assign next_wd_sync_0 = this_md_sr_reg;
if(RESET_WDCLK) // loj@8-30-05
this_wd_sr_reg <= 32'h0000_0000;
this_wd_sync_0 <= 32'h0000_0000;
this_wd_sync_1 <= 32'h0000_0000;
this_wd_sr_reg <= next_wd_sr_reg;
this_wd_sync_0 <= next_wd_sync_0;
this_wd_sync_1 <= this_wd_sync_0;
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Reset over Set synchronous SR latch
assign md_sr_set = this_status_reg & sts_clr & sts_stiky; //STS read clears flag
assign md_sr_reset = ~this_md_sync_0;
assign next_md_sr_reg = (~md_sr_reset) & (this_md_sr_reg | md_sr_set) & sts_stiky;
assign next_md_sync_0 = this_wd_sr_reg;
this_md_sr_reg <= 32'h0000_0000;
this_md_sync_0 <= 32'h0000_0000;
this_status_reg <= sts_reset;
this_md_sr_reg <= next_md_sr_reg;
this_md_sync_0 <= next_md_sync_0;
this_status_reg <= next_status_reg;
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
assign inst_status_reg = (this_status_reg & sts_instn) | (sts_reset & ~sts_instn);
assign CONFIG_BUS = inst_config_reg[cfg_width-1:0];
assign READ_DATA = PA[1] ? (PA[0] ? inst_status_reg[31:16] : inst_status_reg[15:0]) :
(PA[0] ? inst_config_reg[31:16] : inst_config_reg[15:0]) ;
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