| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: lib.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | /*%W% %G%*/ |
| 36 | //************************************************************************* |
| 37 | // |
| 38 | // File Name : lib.v |
| 39 | // Author Name : John Lo |
| 40 | // Description : This is a collection of library elements from big_mac, |
| 41 | // xmac, xpcs, pcs ... etc. |
| 42 | // Parent Module: many |
| 43 | // Child Module: many |
| 44 | // Interface Mod: many |
| 45 | // |
| 46 | // Copyright (c) 2008, Sun Microsystems, Inc. |
| 47 | // Sun Proprietary and Confidential |
| 48 | // |
| 49 | //************************************************************************* |
| 50 | |
| 51 | module CtsRoot (Z, A); |
| 52 | |
| 53 | output Z; |
| 54 | input A; |
| 55 | |
| 56 | assign Z = A; |
| 57 | |
| 58 | endmodule |
| 59 | |
| 60 | |
| 61 | /* ----------------------------------------------------------------------- |
| 62 | * If the 10 bit data stream is i,i,i,....,i,i,a,b,c,d,e,f,g, |
| 63 | * the 20 bit interface can be one of the two: |
| 64 | * 1. {a,i} -> {c,b} -> {e,d} -> {g,f} |
| 65 | * 2. {b,a} -> {d,c} -> {f,e} -> {h,g} |
| 66 | * |
| 67 | * The a,b,c,d,e,f,g order remains the same between the above two data |
| 68 | * ----------------------------------------------------------------------- |
| 69 | */ |
| 70 | |
| 71 | module mac_10to20 ( |
| 72 | clk10b, |
| 73 | din10b, |
| 74 | clk20b, |
| 75 | dout20b |
| 76 | ); |
| 77 | input clk10b; |
| 78 | input [9:0] din10b; |
| 79 | input clk20b; |
| 80 | output [19:0] dout20b; |
| 81 | |
| 82 | wire [9:0] din10b; |
| 83 | wire [9:0] din10b_lo; |
| 84 | wire [9:0] din10b_hi; |
| 85 | wire clk; |
| 86 | |
| 87 | `ifdef NEPTUNE |
| 88 | CtsRoot clk_CtsRoot (.Z(clk),.A(clk20b)); |
| 89 | `else |
| 90 | assign clk = clk20b; |
| 91 | `endif |
| 92 | |
| 93 | RegDff #(10) din10b_hi_10to20_RegDff (.din(din10b), .clk(clk10b),.qout(din10b_hi)); |
| 94 | RegDff #(10) din10b_lo_10to20_RegDff (.din(din10b_hi),.clk(clk10b),.qout(din10b_lo)); |
| 95 | |
| 96 | RegDff #(20) dout20b_10to20_RegDff (.din({din10b_hi[9:0],din10b_lo[9:0]}),.clk(clk),.qout(dout20b[19:0])); |
| 97 | |
| 98 | |
| 99 | endmodule // mac_10to20 |
| 100 | |
| 101 | |
| 102 | module mac_20to10 ( |
| 103 | FUNC_MODE, |
| 104 | clk20b, |
| 105 | din20b, |
| 106 | clk10b, |
| 107 | dout10b |
| 108 | ); |
| 109 | input FUNC_MODE; |
| 110 | input clk20b; |
| 111 | input [19:0] din20b; |
| 112 | input clk10b; |
| 113 | output [9:0] dout10b; |
| 114 | |
| 115 | wire [19:0] din20b; |
| 116 | wire [19:0] din20b_reg; |
| 117 | wire [9:0] dout10b; |
| 118 | wire [9:0] ddr_out; |
| 119 | wire clk; |
| 120 | wire clk_FUNC_MODE; |
| 121 | |
| 122 | `ifdef NEPTUNE |
| 123 | CtsRoot clk_CtsRoot (.Z(clk),.A(clk20b)); |
| 124 | `else |
| 125 | assign clk = clk20b; |
| 126 | `endif |
| 127 | |
| 128 | RegDff #(20) din_20to10_RegDff (.din(din20b[19:0]),.clk(clk),.qout(din20b_reg[19:0])); |
| 129 | // SYNC RULE 3 of LV requirements to intercept offending path in LV_TM mode. |
| 130 | assign clk_FUNC_MODE = clk | (~FUNC_MODE); |
| 131 | assign ddr_out = clk_FUNC_MODE ? din20b_reg[9:0] : din20b_reg[19:10]; |
| 132 | |
| 133 | RegDff #(10) dout10b_20to10_RegDff (.din(ddr_out[9:0]),.clk(clk10b),.qout(dout10b[9:0])); |
| 134 | |
| 135 | |
| 136 | endmodule // mac_20to10 |
| 137 | |
| 138 | |
| 139 | // digitally delay 4 clk. |
| 140 | module DLY8CLK ( |
| 141 | clk, |
| 142 | din, |
| 143 | dly4, |
| 144 | dly8 |
| 145 | ); |
| 146 | |
| 147 | input clk; |
| 148 | input din; |
| 149 | output dly4; |
| 150 | output dly8; |
| 151 | |
| 152 | reg dly1,dly2,dly3,dly4,dly5,dly6,dly7,dly8; |
| 153 | |
| 154 | always @ (posedge clk) |
| 155 | begin |
| 156 | dly1 <= din; |
| 157 | dly2 <= dly1; |
| 158 | dly3 <= dly2; |
| 159 | dly4 <= dly3; |
| 160 | dly5 <= dly4; |
| 161 | dly6 <= dly5; |
| 162 | dly7 <= dly6; |
| 163 | dly8 <= dly7; |
| 164 | end |
| 165 | |
| 166 | endmodule // DLY8CLK |
| 167 | |
| 168 | module DIV4_CLK ( |
| 169 | reset, |
| 170 | clk, |
| 171 | clk4 |
| 172 | ); |
| 173 | |
| 174 | input reset; |
| 175 | input clk; |
| 176 | output clk4; |
| 177 | |
| 178 | wire hw_reset_clk; |
| 179 | wire hw_reset_clk_lead; |
| 180 | reg [1:0] count; |
| 181 | |
| 182 | SYNC_CELL hw_reset_clk_SYNC_CELL(.D(reset),.CP(clk),.Q(hw_reset_clk)); |
| 183 | |
| 184 | pls_gen hw_reset_clk_lead_pls_gen (.clk(clk),.in(hw_reset_clk),.out(hw_reset_clk_lead)); |
| 185 | |
| 186 | |
| 187 | always @ (posedge clk) |
| 188 | if (hw_reset_clk_lead) |
| 189 | count <= 0; |
| 190 | else count <= count + 1; |
| 191 | |
| 192 | assign clk4 = count[1]; |
| 193 | |
| 194 | |
| 195 | endmodule // DIV4_CLK |
| 196 | |
| 197 | module DIV2_CLK ( |
| 198 | reset, |
| 199 | clk, |
| 200 | clk2 |
| 201 | ); |
| 202 | |
| 203 | input reset; |
| 204 | input clk; |
| 205 | output clk2; |
| 206 | |
| 207 | wire hw_reset_clk; |
| 208 | wire hw_reset_clk_lead; |
| 209 | |
| 210 | SYNC_CELL hw_reset_clk_SYNC_CELL(.D(reset),.CP(clk),.Q(hw_reset_clk)); |
| 211 | |
| 212 | pls_gen hw_reset_clk_lead_pls_gen (.clk(clk),.in(hw_reset_clk),.out(hw_reset_clk_lead)); |
| 213 | |
| 214 | TFF clk2_TFF (.toggle(1'b1), |
| 215 | .clk(clk), |
| 216 | .reset(hw_reset_clk_lead), |
| 217 | .qout(clk2)); |
| 218 | |
| 219 | endmodule // DIV2_CLK |
| 220 | |
| 221 | |
| 222 | /*********************************** |
| 223 | * Counter |
| 224 | ***********************************/ |
| 225 | module Counter (reset,clk,ce,count); |
| 226 | parameter dwidth = 9; |
| 227 | input reset,clk,ce; |
| 228 | output [dwidth-1:0] count; |
| 229 | |
| 230 | reg [dwidth-1:0] count; |
| 231 | |
| 232 | always @ (posedge clk) |
| 233 | if (reset) |
| 234 | count <= 0; |
| 235 | else |
| 236 | casex(ce) // synopsys parallel_case full_case |
| 237 | 1'b0: count <= count; |
| 238 | 1'b1: count <= count + 1; |
| 239 | endcase |
| 240 | |
| 241 | endmodule // Counter |
| 242 | |
| 243 | |
| 244 | //***************************** |
| 245 | // Set Reset Flip Flop |
| 246 | //***************************** |
| 247 | module SRFF (reset,clk,iSet,iRst,oQ); |
| 248 | |
| 249 | input reset, clk, iSet, iRst; |
| 250 | output oQ; |
| 251 | |
| 252 | reg oQ; |
| 253 | |
| 254 | always @ (posedge clk) |
| 255 | if (reset) |
| 256 | oQ <= 0; |
| 257 | else |
| 258 | casex({iSet, iRst}) // synopsys parallel_case full_case |
| 259 | 2'b00: oQ <= oQ; |
| 260 | 2'b01: oQ <= 0; |
| 261 | 2'b1x: oQ <= 1; |
| 262 | endcase |
| 263 | |
| 264 | endmodule // end of Set Reset Flip Flop |
| 265 | |
| 266 | |
| 267 | //***************************** |
| 268 | // Reset Set Flip Flop |
| 269 | //***************************** |
| 270 | module RSFF (reset,clk,iSet,iRst,oQ); |
| 271 | |
| 272 | input reset, clk, iSet, iRst; |
| 273 | output oQ; |
| 274 | |
| 275 | reg oQ; |
| 276 | |
| 277 | always @ (posedge clk) |
| 278 | if (reset) |
| 279 | oQ <= 0; |
| 280 | else |
| 281 | casex({iSet, iRst}) // synopsys parallel_case full_case |
| 282 | 2'b00: oQ <= oQ; |
| 283 | 2'bx1: oQ <= 0; |
| 284 | 2'b10: oQ <= 1; |
| 285 | endcase |
| 286 | |
| 287 | endmodule // end of Reset Set Flip Flop |
| 288 | |
| 289 | |
| 290 | //***************************** |
| 291 | // Register xREG |
| 292 | //***************************** |
| 293 | module xREG (clk,reset,en,din,qout); |
| 294 | parameter dwidth = 10; |
| 295 | input clk, en, reset; |
| 296 | input [dwidth-1:0] din; |
| 297 | output [dwidth-1:0] qout; |
| 298 | |
| 299 | reg [dwidth-1:0] qout; |
| 300 | |
| 301 | always @ (posedge clk) |
| 302 | if (reset) |
| 303 | qout <= 0; |
| 304 | else if (en) |
| 305 | qout <= din; |
| 306 | else |
| 307 | qout <= qout; |
| 308 | |
| 309 | |
| 310 | endmodule // end of xREG |
| 311 | |
| 312 | |
| 313 | //***************************** |
| 314 | // Register xREG2 |
| 315 | //***************************** |
| 316 | module xREG2 (clk,reset,reset_value,load,din,qout); |
| 317 | |
| 318 | parameter dwidth = 10; |
| 319 | input clk; |
| 320 | input reset; |
| 321 | input [dwidth-1:0] reset_value; |
| 322 | input load; |
| 323 | input [dwidth-1:0] din; |
| 324 | output [dwidth-1:0] qout; |
| 325 | |
| 326 | reg [dwidth-1:0] qout; |
| 327 | |
| 328 | |
| 329 | always @ (posedge clk) |
| 330 | if (reset) |
| 331 | qout <= reset_value; |
| 332 | else if (load) |
| 333 | qout <= din; |
| 334 | else |
| 335 | qout <= qout; |
| 336 | |
| 337 | endmodule // end of xREG2 |
| 338 | |
| 339 | |
| 340 | //***************************** |
| 341 | // Register xREG3 |
| 342 | //***************************** |
| 343 | module xREG3 (clk,reset,rst,en,din,qout); |
| 344 | parameter dwidth = 10; |
| 345 | input clk, en, reset, rst; |
| 346 | input [dwidth-1:0] din; |
| 347 | output [dwidth-1:0] qout; |
| 348 | |
| 349 | reg [dwidth-1:0] qout; |
| 350 | |
| 351 | always @ (posedge clk) |
| 352 | if (reset) |
| 353 | qout <= 0; |
| 354 | else if (rst) |
| 355 | qout <= 0; |
| 356 | else if (en) |
| 357 | qout <= din; |
| 358 | else |
| 359 | qout <= qout; |
| 360 | |
| 361 | |
| 362 | endmodule // end of xREG3 |
| 363 | |
| 364 | |
| 365 | /************************************ |
| 366 | * Rising edge pulse gen |
| 367 | *************************************/ |
| 368 | module PlsGen (reset,clk,iSigIn,oPlsOut); |
| 369 | |
| 370 | input reset, clk, iSigIn; |
| 371 | output oPlsOut; |
| 372 | |
| 373 | reg Q; |
| 374 | |
| 375 | always @ (posedge clk) |
| 376 | if (reset) |
| 377 | Q <= 0; |
| 378 | else |
| 379 | Q <= iSigIn; |
| 380 | |
| 381 | wire Qb = ~Q; |
| 382 | |
| 383 | wire oPlsOut = iSigIn & Qb; |
| 384 | |
| 385 | endmodule |
| 386 | |
| 387 | |
| 388 | |
| 389 | |
| 390 | //******************************* |
| 391 | // High Speed Loadable Counter |
| 392 | //******************************* |
| 393 | module hs_cntr_cell_X16 ( |
| 394 | // Outputs |
| 395 | Q, |
| 396 | // Inputs |
| 397 | clk, reset, cnt, clr, load, load_value |
| 398 | ); |
| 399 | |
| 400 | input clk; |
| 401 | input reset; |
| 402 | input cnt; |
| 403 | input clr; |
| 404 | input load; |
| 405 | input [15:0] load_value; |
| 406 | output [15:0] Q; |
| 407 | |
| 408 | wire [15:1] toggle; |
| 409 | reg [15:0] Q; |
| 410 | |
| 411 | assign toggle[15] = Q[14] & Q[13] & Q[12] & Q[11] & Q[10] & Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 412 | assign toggle[14] = Q[13] & Q[12] & Q[11] & Q[10] & Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 413 | assign toggle[13] = Q[12] & Q[11] & Q[10] & Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 414 | assign toggle[12] = Q[11] & Q[10] & Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 415 | assign toggle[11] = Q[10] & Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 416 | assign toggle[10] = Q[9] & Q[8] & Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 417 | assign toggle[9] = Q[8] & Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 418 | assign toggle[8] = Q[7] & Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 419 | assign toggle[7] = Q[6] & Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 420 | assign toggle[6] = Q[5] & Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 421 | assign toggle[5] = Q[4] & Q[3] & Q[2] & Q[1] & Q[0] ; |
| 422 | assign toggle[4] = Q[3] & Q[2] & Q[1] & Q[0] ; |
| 423 | assign toggle[3] = Q[2] & Q[1] & Q[0] ; |
| 424 | assign toggle[2] = Q[1] & Q[0] ; |
| 425 | assign toggle[1] = Q[0] ; |
| 426 | |
| 427 | |
| 428 | always @ (posedge clk) |
| 429 | if (reset | clr) |
| 430 | Q <= 16'b0; |
| 431 | else if (load) |
| 432 | Q <= load_value[15:0]; |
| 433 | else if (cnt) |
| 434 | begin |
| 435 | Q[15] <= toggle[15] ? ~Q[15] : Q[15]; |
| 436 | Q[14] <= toggle[14] ? ~Q[14] : Q[14]; |
| 437 | Q[13] <= toggle[13] ? ~Q[13] : Q[13]; |
| 438 | Q[12] <= toggle[12] ? ~Q[12] : Q[12]; |
| 439 | Q[11] <= toggle[11] ? ~Q[11] : Q[11]; |
| 440 | Q[10] <= toggle[10] ? ~Q[10] : Q[10]; |
| 441 | Q[9] <= toggle[9] ? ~Q[9] : Q[9] ; |
| 442 | Q[8] <= toggle[8] ? ~Q[8] : Q[8] ; |
| 443 | Q[7] <= toggle[7] ? ~Q[7] : Q[7] ; |
| 444 | Q[6] <= toggle[6] ? ~Q[6] : Q[6] ; |
| 445 | Q[5] <= toggle[5] ? ~Q[5] : Q[5] ; |
| 446 | Q[4] <= toggle[4] ? ~Q[4] : Q[4] ; |
| 447 | Q[3] <= toggle[3] ? ~Q[3] : Q[3] ; |
| 448 | Q[2] <= toggle[2] ? ~Q[2] : Q[2] ; |
| 449 | Q[1] <= toggle[1] ? ~Q[1] : Q[1] ; |
| 450 | Q[0] <= ~Q[0] ; |
| 451 | end |
| 452 | else |
| 453 | Q <= Q; // Hold the value. |
| 454 | |
| 455 | |
| 456 | endmodule // hs_cntr_cell_X16 |
| 457 | |
| 458 | |
| 459 | |
| 460 | |
| 461 | //******************************* |
| 462 | // High Speed Loadable Counter |
| 463 | //******************************* |
| 464 | module hs_ld_counter_X32 ( |
| 465 | // Outputs |
| 466 | Q, max_value_reached, |
| 467 | // Inputs |
| 468 | clk, reset, inc, clr, max_value, load, load_value |
| 469 | ); |
| 470 | |
| 471 | input clk; |
| 472 | input reset; // global signals |
| 473 | input inc; // Count Enable |
| 474 | input clr; // read auto clear input. |
| 475 | input [31:0] max_value; // compared value |
| 476 | input load; |
| 477 | input [31:0] load_value; // compared value |
| 478 | output [31:0] Q ; |
| 479 | output max_value_reached; |
| 480 | |
| 481 | wire inc_msb; |
| 482 | wire set_flag; |
| 483 | wire [31:0] max_value; |
| 484 | wire [15:0] Q1; |
| 485 | wire [15:0] Q0; |
| 486 | wire [31:0] Q = {Q1[15:0],Q0[15:0]}; |
| 487 | wire flag_lv; |
| 488 | |
| 489 | wire max_value_reached = (max_value[31:0] == Q[31:0]); |
| 490 | |
| 491 | wire inc_count = ~max_value_reached & inc; |
| 492 | |
| 493 | assign set_flag = (Q0[15:0] == 16'hFFFE) & inc_count; |
| 494 | |
| 495 | SR_FF flag_count_SR_FF(.set(set_flag), |
| 496 | .rst(inc_msb), |
| 497 | .clk(clk), |
| 498 | .reset(reset | clr), // loj @6-16-06 |
| 499 | .qout(flag_lv)); |
| 500 | |
| 501 | // flag_lv = (Q0 == 16'hFFFF) |
| 502 | assign inc_msb = flag_lv & inc_count; |
| 503 | |
| 504 | |
| 505 | |
| 506 | /* ----- counter instantiation ----- */ |
| 507 | hs_cntr_cell_X16 lsb_hs_cntr_cell_X16( |
| 508 | .clk(clk), |
| 509 | .reset(reset), |
| 510 | .cnt(inc_count), |
| 511 | .clr(clr), |
| 512 | .load(load), |
| 513 | .load_value(load_value[15:0]), |
| 514 | .Q(Q0[15:0]) |
| 515 | ); |
| 516 | |
| 517 | hs_cntr_cell_X16 msb_hs_cntr_cell_X16( |
| 518 | .clk(clk), |
| 519 | .reset(reset), |
| 520 | .cnt(inc_msb), |
| 521 | .clr(clr), |
| 522 | .load(load), |
| 523 | .load_value(load_value[31:16]), |
| 524 | .Q(Q1[15:0]) |
| 525 | ); |
| 526 | |
| 527 | |
| 528 | |
| 529 | endmodule // hs_ld_counter_X31 |
| 530 | |
| 531 | |
| 532 | |
| 533 | //***************************** |
| 534 | // Register RAC_FF |
| 535 | //***************************** |
| 536 | module RAC_FF (clk,reset,set,rst, |
| 537 | load,load_data,dout); |
| 538 | |
| 539 | input clk,reset ; // global signals |
| 540 | input set,rst ; |
| 541 | input load ; |
| 542 | input load_data ; // compared value |
| 543 | output dout ; |
| 544 | |
| 545 | reg dout; |
| 546 | |
| 547 | always @ (posedge clk) |
| 548 | if (reset | rst) |
| 549 | dout <= 0; |
| 550 | else if (set) |
| 551 | dout <= 1; |
| 552 | else if (load) |
| 553 | dout <= load_data; |
| 554 | else |
| 555 | dout <= dout; |
| 556 | |
| 557 | endmodule // RAC_FF |
| 558 | |
| 559 | |
| 560 | |
| 561 | |
| 562 | |
| 563 | |
| 564 | // \\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\ |
| 565 | |
| 566 | /********************************************************************** |
| 567 | * From here on are mainly for mac and xmac design |
| 568 | * ********************************************************************/ |
| 569 | |
| 570 | /* ------------------------------ Flip-Flops ------------------------------- */ |
| 571 | |
| 572 | |
| 573 | module FD1(CP, D, Q); |
| 574 | |
| 575 | input CP, D; |
| 576 | output Q; |
| 577 | |
| 578 | reg Q; |
| 579 | |
| 580 | always @(posedge CP) Q <= D; |
| 581 | |
| 582 | endmodule // FD1 |
| 583 | |
| 584 | module FD1H(CP, D, Q); |
| 585 | |
| 586 | input CP, D; |
| 587 | output Q; |
| 588 | |
| 589 | reg Q; |
| 590 | // vlint flag_negedge_always_block off |
| 591 | always @(negedge CP) Q <= D; |
| 592 | // vlint flag_negedge_always_block on |
| 593 | |
| 594 | endmodule // FD1H |
| 595 | |
| 596 | /* ----------------------- Synchronizers ----------------------------- */ |
| 597 | |
| 598 | /****************************************** |
| 599 | * The following SYNC_CELLs are used by mac |
| 600 | ******************************************/ |
| 601 | module SYNC_CELL(D,CP,Q); |
| 602 | input D; |
| 603 | input CP; |
| 604 | output Q; |
| 605 | |
| 606 | `ifdef NEPTUNE |
| 607 | |
| 608 | reg Q,sync1; |
| 609 | |
| 610 | always @ (posedge CP) |
| 611 | begin |
| 612 | sync1 <= D; |
| 613 | Q <= sync1; |
| 614 | end |
| 615 | |
| 616 | |
| 617 | `else |
| 618 | |
| 619 | // vlint flag_dangling_net_within_module off |
| 620 | // vlint flag_net_has_no_load off |
| 621 | wire so; |
| 622 | // vlint flag_net_has_no_load on |
| 623 | // vlint flag_dangling_net_within_module on |
| 624 | |
| 625 | |
| 626 | cl_a1_clksyncff_4x SYNC_CELL (.l1clk(CP), |
| 627 | .d(D), |
| 628 | .si(1'b0), |
| 629 | .siclk(1'b0), |
| 630 | .soclk(1'b0), |
| 631 | .q(Q), |
| 632 | .so(so) ); |
| 633 | |
| 634 | `endif |
| 635 | |
| 636 | endmodule // SYNC_CELL |
| 637 | |
| 638 | module FAST_SYNC_CELL(D,CP,Q); |
| 639 | input D; |
| 640 | input CP; |
| 641 | output Q; |
| 642 | |
| 643 | reg Q,sync1; |
| 644 | always @ (posedge CP) |
| 645 | sync1 <= D; |
| 646 | |
| 647 | // vlint flag_negedge_always_block off |
| 648 | always @ (negedge CP) // Negative edge clock |
| 649 | Q <= sync1; |
| 650 | // vlint flag_negedge_always_block on |
| 651 | |
| 652 | endmodule // FAST_SYNC_CELL |
| 653 | |
| 654 | module FAST_INV_SYNC_CELL(D,CP,Q); |
| 655 | input D; |
| 656 | input CP; |
| 657 | output Q; |
| 658 | |
| 659 | reg Q,sync1; |
| 660 | |
| 661 | |
| 662 | // vlint flag_negedge_always_block off |
| 663 | always @ (negedge CP) |
| 664 | sync1 <= D; |
| 665 | // vlint flag_negedge_always_block on |
| 666 | |
| 667 | always @ (posedge CP) |
| 668 | Q <= sync1; |
| 669 | |
| 670 | endmodule // FAST_INV_SYNC_CELL |
| 671 | |
| 672 | //***************************** |
| 673 | //* SYNC_MOD |
| 674 | //***************************** |
| 675 | module SYNC_PLS (src_pls,src_clk,src_reset,des_clk,out_pls); |
| 676 | input src_pls; |
| 677 | input src_clk; |
| 678 | input src_reset; // power on reset |
| 679 | input des_clk; |
| 680 | output out_pls; |
| 681 | |
| 682 | wire sr_ff_2_sync_cell,src_rst_internal,des_level_out; |
| 683 | |
| 684 | SR_FF SR_FF_u1(.set(src_pls), |
| 685 | .rst(src_rst_internal), |
| 686 | .clk(src_clk), |
| 687 | .reset(src_reset), |
| 688 | .qout(sr_ff_2_sync_cell)); |
| 689 | |
| 690 | SYNC_CELL go_to_des_SYNC_CELL (.D(sr_ff_2_sync_cell),.CP(des_clk), |
| 691 | .Q(des_level_out)); |
| 692 | |
| 693 | SYNC_CELL back_to_src_SYNC_CELL(.D(des_level_out),.CP(src_clk), |
| 694 | .Q(src_rst_internal)); |
| 695 | |
| 696 | pls_gen pls_gen_u6(.clk(des_clk),.in(des_level_out),.out(out_pls)); |
| 697 | |
| 698 | endmodule // SYNC_PLS |
| 699 | |
| 700 | |
| 701 | /****************************************** |
| 702 | * The following SYNC_CELLs are used by pcs |
| 703 | ******************************************/ |
| 704 | |
| 705 | /* |
| 706 | ** NEC library dependent wrapper for SYNC generic |
| 707 | */ |
| 708 | module SYNCREG (qout, clk, din); |
| 709 | //non-resettable variable width register |
| 710 | //only one Q output |
| 711 | |
| 712 | output qout; |
| 713 | input clk; |
| 714 | input din; |
| 715 | |
| 716 | SYNC_CELL PCS_SYNC_CELL(.D(din),.CP(clk),.Q(qout)); |
| 717 | |
| 718 | endmodule |
| 719 | |
| 720 | |
| 721 | module SYNCREG16 (qout, clk, din); |
| 722 | //non-resettable variable width register |
| 723 | //only one Q output |
| 724 | |
| 725 | output [15:0] qout; |
| 726 | input clk; |
| 727 | input [15:0] din; |
| 728 | |
| 729 | SYNCREG R_SYNC_0(.din(din[0]), .clk(clk), .qout(qout[0])); |
| 730 | |
| 731 | SYNCREG R_SYNC_1(.din(din[1]), .clk(clk), .qout(qout[1])); |
| 732 | |
| 733 | SYNCREG R_SYNC_2(.din(din[2]), .clk(clk), .qout(qout[2])); |
| 734 | |
| 735 | SYNCREG R_SYNC_3(.din(din[3]), .clk(clk), .qout(qout[3])); |
| 736 | |
| 737 | SYNCREG R_SYNC_4(.din(din[4]), .clk(clk), .qout(qout[4])); |
| 738 | |
| 739 | SYNCREG R_SYNC_5(.din(din[5]), .clk(clk), .qout(qout[5])); |
| 740 | |
| 741 | SYNCREG R_SYNC_6(.din(din[6]), .clk(clk), .qout(qout[6])); |
| 742 | |
| 743 | SYNCREG R_SYNC_7(.din(din[7]), .clk(clk), .qout(qout[7])); |
| 744 | |
| 745 | SYNCREG R_SYNC_8(.din(din[8]), .clk(clk), .qout(qout[8])); |
| 746 | |
| 747 | SYNCREG R_SYNC_9(.din(din[9]), .clk(clk), .qout(qout[9])); |
| 748 | |
| 749 | SYNCREG R_SYNC_10(.din(din[10]), .clk(clk), .qout(qout[10])); |
| 750 | |
| 751 | SYNCREG R_SYNC_11(.din(din[11]), .clk(clk), .qout(qout[11])); |
| 752 | |
| 753 | SYNCREG R_SYNC_12(.din(din[12]), .clk(clk), .qout(qout[12])); |
| 754 | |
| 755 | SYNCREG R_SYNC_13(.din(din[13]), .clk(clk), .qout(qout[13])); |
| 756 | |
| 757 | SYNCREG R_SYNC_14(.din(din[14]), .clk(clk), .qout(qout[14])); |
| 758 | |
| 759 | SYNCREG R_SYNC_15(.din(din[15]), .clk(clk), .qout(qout[15])); |
| 760 | |
| 761 | endmodule |
| 762 | |
| 763 | // @(#)SYNCREG17.v 1.2 06/07/99 |
| 764 | module SYNCREG17 (qout, clk, din); |
| 765 | //non-resettable variable width register |
| 766 | //only one Q output |
| 767 | |
| 768 | output [16:0] qout; |
| 769 | input clk; |
| 770 | input [16:0] din; |
| 771 | |
| 772 | SYNCREG R_SYNC_0(.din(din[0]), .clk(clk), .qout(qout[0])); |
| 773 | |
| 774 | SYNCREG R_SYNC_1(.din(din[1]), .clk(clk), .qout(qout[1])); |
| 775 | |
| 776 | SYNCREG R_SYNC_2(.din(din[2]), .clk(clk), .qout(qout[2])); |
| 777 | |
| 778 | SYNCREG R_SYNC_3(.din(din[3]), .clk(clk), .qout(qout[3])); |
| 779 | |
| 780 | SYNCREG R_SYNC_4(.din(din[4]), .clk(clk), .qout(qout[4])); |
| 781 | |
| 782 | SYNCREG R_SYNC_5(.din(din[5]), .clk(clk), .qout(qout[5])); |
| 783 | |
| 784 | SYNCREG R_SYNC_6(.din(din[6]), .clk(clk), .qout(qout[6])); |
| 785 | |
| 786 | SYNCREG R_SYNC_7(.din(din[7]), .clk(clk), .qout(qout[7])); |
| 787 | |
| 788 | SYNCREG R_SYNC_8(.din(din[8]), .clk(clk), .qout(qout[8])); |
| 789 | |
| 790 | SYNCREG R_SYNC_9(.din(din[9]), .clk(clk), .qout(qout[9])); |
| 791 | |
| 792 | SYNCREG R_SYNC_10(.din(din[10]), .clk(clk), .qout(qout[10])); |
| 793 | |
| 794 | SYNCREG R_SYNC_11(.din(din[11]), .clk(clk), .qout(qout[11])); |
| 795 | |
| 796 | SYNCREG R_SYNC_12(.din(din[12]), .clk(clk), .qout(qout[12])); |
| 797 | |
| 798 | SYNCREG R_SYNC_13(.din(din[13]), .clk(clk), .qout(qout[13])); |
| 799 | |
| 800 | SYNCREG R_SYNC_14(.din(din[14]), .clk(clk), .qout(qout[14])); |
| 801 | |
| 802 | SYNCREG R_SYNC_15(.din(din[15]), .clk(clk), .qout(qout[15])); |
| 803 | |
| 804 | SYNCREG R_SYNC_16(.din(din[16]), .clk(clk), .qout(qout[16])); |
| 805 | |
| 806 | endmodule |
| 807 | |
| 808 | |
| 809 | // @(#)SYNCREG22.v 1.2 06/07/99 |
| 810 | module SYNCREG22 (qout, clk, din); |
| 811 | //non-resettable variable width register |
| 812 | //only one Q output |
| 813 | |
| 814 | output [21:0] qout; |
| 815 | input clk; |
| 816 | input [21:0] din; |
| 817 | |
| 818 | SYNCREG R_SYNC_0(.din(din[0]), .clk(clk), .qout(qout[0])); |
| 819 | |
| 820 | SYNCREG R_SYNC_1(.din(din[1]), .clk(clk), .qout(qout[1])); |
| 821 | |
| 822 | SYNCREG R_SYNC_2(.din(din[2]), .clk(clk), .qout(qout[2])); |
| 823 | |
| 824 | SYNCREG R_SYNC_3(.din(din[3]), .clk(clk), .qout(qout[3])); |
| 825 | |
| 826 | SYNCREG R_SYNC_4(.din(din[4]), .clk(clk), .qout(qout[4])); |
| 827 | |
| 828 | SYNCREG R_SYNC_5(.din(din[5]), .clk(clk), .qout(qout[5])); |
| 829 | |
| 830 | SYNCREG R_SYNC_6(.din(din[6]), .clk(clk), .qout(qout[6])); |
| 831 | |
| 832 | SYNCREG R_SYNC_7(.din(din[7]), .clk(clk), .qout(qout[7])); |
| 833 | |
| 834 | SYNCREG R_SYNC_8(.din(din[8]), .clk(clk), .qout(qout[8])); |
| 835 | |
| 836 | SYNCREG R_SYNC_9(.din(din[9]), .clk(clk), .qout(qout[9])); |
| 837 | |
| 838 | SYNCREG R_SYNC_10(.din(din[10]), .clk(clk), .qout(qout[10])); |
| 839 | |
| 840 | SYNCREG R_SYNC_11(.din(din[11]), .clk(clk), .qout(qout[11])); |
| 841 | |
| 842 | SYNCREG R_SYNC_12(.din(din[12]), .clk(clk), .qout(qout[12])); |
| 843 | |
| 844 | SYNCREG R_SYNC_13(.din(din[13]), .clk(clk), .qout(qout[13])); |
| 845 | |
| 846 | SYNCREG R_SYNC_14(.din(din[14]), .clk(clk), .qout(qout[14])); |
| 847 | |
| 848 | SYNCREG R_SYNC_15(.din(din[15]), .clk(clk), .qout(qout[15])); |
| 849 | |
| 850 | SYNCREG R_SYNC_16(.din(din[16]), .clk(clk), .qout(qout[16])); |
| 851 | |
| 852 | SYNCREG R_SYNC_17(.din(din[17]), .clk(clk), .qout(qout[17])); |
| 853 | |
| 854 | SYNCREG R_SYNC_18(.din(din[18]), .clk(clk), .qout(qout[18])); |
| 855 | |
| 856 | SYNCREG R_SYNC_19(.din(din[19]), .clk(clk), .qout(qout[19])); |
| 857 | |
| 858 | SYNCREG R_SYNC_20(.din(din[20]), .clk(clk), .qout(qout[20])); |
| 859 | |
| 860 | SYNCREG R_SYNC_21(.din(din[21]), .clk(clk), .qout(qout[21])); |
| 861 | |
| 862 | endmodule |
| 863 | |
| 864 | |
| 865 | // @(#)SYNCREG6.v 1.2 06/07/99 |
| 866 | module SYNCREG6 (qout, clk, din); |
| 867 | //non-resettable variable width register |
| 868 | //only one Q output |
| 869 | |
| 870 | output [5:0] qout; |
| 871 | input clk; |
| 872 | input [5:0] din; |
| 873 | |
| 874 | SYNCREG R_SYNC_0(.din(din[0]), .clk(clk), .qout(qout[0])); |
| 875 | |
| 876 | SYNCREG R_SYNC_1(.din(din[1]), .clk(clk), .qout(qout[1])); |
| 877 | |
| 878 | SYNCREG R_SYNC_2(.din(din[2]), .clk(clk), .qout(qout[2])); |
| 879 | |
| 880 | SYNCREG R_SYNC_3(.din(din[3]), .clk(clk), .qout(qout[3])); |
| 881 | |
| 882 | SYNCREG R_SYNC_4(.din(din[4]), .clk(clk), .qout(qout[4])); |
| 883 | |
| 884 | SYNCREG R_SYNC_5(.din(din[5]), .clk(clk), .qout(qout[5])); |
| 885 | |
| 886 | endmodule |
| 887 | |
| 888 | /* -----------------end of Synchronizers ----------------------------- */ |
| 889 | |
| 890 | |
| 891 | /* ------------------------- Registers ------------------------------- */ |
| 892 | |
| 893 | module register_X8(clk,din,dout); |
| 894 | input clk; |
| 895 | input [7:0] din; |
| 896 | output [7:0] dout; |
| 897 | |
| 898 | |
| 899 | wire [7:0] din; |
| 900 | reg [7:0] dout; |
| 901 | |
| 902 | always @ (posedge clk) |
| 903 | dout <= din; |
| 904 | |
| 905 | endmodule // register_X8 |
| 906 | |
| 907 | |
| 908 | |
| 909 | module register_X8_inv(clk,din,dout); |
| 910 | input clk; |
| 911 | input [7:0] din; |
| 912 | output [7:0] dout; |
| 913 | |
| 914 | wire clk_n = ~clk; |
| 915 | wire [7:0] din; |
| 916 | reg [7:0] dout; |
| 917 | |
| 918 | always @ (posedge clk_n) |
| 919 | dout <= din; |
| 920 | |
| 921 | endmodule // register_X8_inv |
| 922 | |
| 923 | |
| 924 | module register_X10(clk,din,dout); |
| 925 | input clk; |
| 926 | input [9:0] din; |
| 927 | output [9:0] dout; |
| 928 | |
| 929 | |
| 930 | wire [9:0] din; |
| 931 | reg [9:0] dout; |
| 932 | |
| 933 | always @ (posedge clk) |
| 934 | dout <= din; |
| 935 | |
| 936 | |
| 937 | endmodule // register_X10 |
| 938 | |
| 939 | module register_X14(clk,din,dout); |
| 940 | input clk; |
| 941 | input [13:0] din; |
| 942 | output [13:0] dout; |
| 943 | |
| 944 | wire [13:0] din; |
| 945 | reg [13:0] dout; |
| 946 | |
| 947 | always @ (posedge clk) |
| 948 | dout <= din; |
| 949 | |
| 950 | |
| 951 | endmodule |
| 952 | |
| 953 | module register_X15(clk,din,dout); |
| 954 | input clk; |
| 955 | input [14:0] din; |
| 956 | output [14:0] dout; |
| 957 | |
| 958 | wire [14:0] din; |
| 959 | reg [14:0] dout; |
| 960 | |
| 961 | always @ (posedge clk) |
| 962 | dout <= din; |
| 963 | |
| 964 | |
| 965 | endmodule |
| 966 | |
| 967 | module register_X16(clk,din,dout); |
| 968 | input clk; |
| 969 | input [15:0] din; |
| 970 | output [15:0] dout; |
| 971 | |
| 972 | wire [15:0] din; |
| 973 | reg [15:0] dout; |
| 974 | |
| 975 | always @ (posedge clk) |
| 976 | dout <= din; |
| 977 | |
| 978 | |
| 979 | endmodule // register_X16 |
| 980 | |
| 981 | module register_X17(clk,din,dout); |
| 982 | input clk; |
| 983 | input [16:0] din; |
| 984 | output [16:0] dout; |
| 985 | |
| 986 | wire [16:0] din; |
| 987 | reg [16:0] dout; |
| 988 | |
| 989 | always @ (posedge clk) |
| 990 | dout <= din; |
| 991 | |
| 992 | |
| 993 | endmodule // register_X17 |
| 994 | |
| 995 | module register_X32(clk,din,dout,dout_n); |
| 996 | input clk; |
| 997 | input [31:0] din; |
| 998 | output [31:0] dout; |
| 999 | output [31:0] dout_n; |
| 1000 | |
| 1001 | |
| 1002 | wire [31:0] din; |
| 1003 | wire [31:0] dout_n; |
| 1004 | reg [31:0] dout; |
| 1005 | |
| 1006 | always @ (posedge clk) |
| 1007 | dout <= din; |
| 1008 | |
| 1009 | |
| 1010 | assign dout_n = ~dout; |
| 1011 | |
| 1012 | endmodule // register_X32 |
| 1013 | |
| 1014 | |
| 1015 | module register_load_X4(clk,load,din,dout); |
| 1016 | input clk; |
| 1017 | input load; |
| 1018 | input [3:0] din; |
| 1019 | output [3:0] dout; |
| 1020 | |
| 1021 | wire clk; |
| 1022 | wire load; |
| 1023 | wire [3:0] din; |
| 1024 | reg [3:0] dout; |
| 1025 | |
| 1026 | always @ (posedge clk) |
| 1027 | if (load) |
| 1028 | dout <= din; |
| 1029 | else |
| 1030 | dout <= dout; |
| 1031 | |
| 1032 | endmodule |
| 1033 | |
| 1034 | module register_load_X8(clk,load,din,dout); |
| 1035 | input clk; |
| 1036 | input load; |
| 1037 | input [7:0] din; |
| 1038 | output [7:0] dout; |
| 1039 | |
| 1040 | wire clk; |
| 1041 | wire load; |
| 1042 | wire [7:0] din; |
| 1043 | reg [7:0] dout; |
| 1044 | |
| 1045 | always @ (posedge clk) |
| 1046 | if (load) |
| 1047 | dout <= din; |
| 1048 | else |
| 1049 | dout <= dout; |
| 1050 | |
| 1051 | endmodule // register_load_X8 |
| 1052 | |
| 1053 | module register_load_X10(clk,load,din,dout); |
| 1054 | input clk; |
| 1055 | input load; |
| 1056 | input [9:0] din; |
| 1057 | output [9:0] dout; |
| 1058 | |
| 1059 | wire clk; |
| 1060 | wire load; |
| 1061 | wire [9:0] din; |
| 1062 | reg [9:0] dout; |
| 1063 | |
| 1064 | always @ (posedge clk) |
| 1065 | if (load) |
| 1066 | dout <= din; |
| 1067 | else |
| 1068 | dout <= dout; |
| 1069 | |
| 1070 | endmodule // register_load_X10 |
| 1071 | |
| 1072 | module register_load_X14(clk,load,din,dout); |
| 1073 | input clk; |
| 1074 | input load; |
| 1075 | input [13:0] din; |
| 1076 | output [13:0] dout; |
| 1077 | |
| 1078 | wire clk; |
| 1079 | wire load; |
| 1080 | wire [13:0] din; |
| 1081 | reg [13:0] dout; |
| 1082 | |
| 1083 | always @ (posedge clk) |
| 1084 | if (load) |
| 1085 | dout <= din; |
| 1086 | else |
| 1087 | dout <= dout; |
| 1088 | |
| 1089 | endmodule // register_load_X14 |
| 1090 | |
| 1091 | |
| 1092 | module register_load_X15(clk,load,din,dout); |
| 1093 | input clk; |
| 1094 | input load; |
| 1095 | input [14:0] din; |
| 1096 | output [14:0] dout; |
| 1097 | |
| 1098 | wire clk; |
| 1099 | wire load; |
| 1100 | wire [14:0] din; |
| 1101 | reg [14:0] dout; |
| 1102 | |
| 1103 | always @ (posedge clk) |
| 1104 | if (load) |
| 1105 | dout <= din; |
| 1106 | else |
| 1107 | dout <= dout; |
| 1108 | |
| 1109 | endmodule // register_load_X15 |
| 1110 | |
| 1111 | |
| 1112 | |
| 1113 | module register_load_X16(clk,load,din,dout); |
| 1114 | input clk; |
| 1115 | input load; |
| 1116 | input [15:0] din; |
| 1117 | output [15:0] dout; |
| 1118 | |
| 1119 | wire clk; |
| 1120 | wire load; |
| 1121 | wire [15:0] din; |
| 1122 | reg [15:0] dout; |
| 1123 | |
| 1124 | always @ (posedge clk) |
| 1125 | if (load) |
| 1126 | dout <= din; |
| 1127 | else |
| 1128 | dout <= dout; |
| 1129 | |
| 1130 | endmodule // register_load_X16 |
| 1131 | |
| 1132 | module register_load_X17(clk,load,din,dout); |
| 1133 | input clk; |
| 1134 | input load; |
| 1135 | input [16:0] din; |
| 1136 | output [16:0] dout; |
| 1137 | |
| 1138 | wire clk; |
| 1139 | wire load; |
| 1140 | wire [16:0] din; |
| 1141 | reg [16:0] dout; |
| 1142 | |
| 1143 | always @ (posedge clk) |
| 1144 | if (load) |
| 1145 | dout <= din; |
| 1146 | else |
| 1147 | dout <= dout; |
| 1148 | |
| 1149 | |
| 1150 | endmodule // register_load_X17 |
| 1151 | |
| 1152 | module register_load_X64(clk,load,din,dout); |
| 1153 | input clk; |
| 1154 | input load; |
| 1155 | input [63:0] din; |
| 1156 | output [63:0] dout; |
| 1157 | |
| 1158 | wire clk; |
| 1159 | wire load; |
| 1160 | wire [63:0] din; |
| 1161 | reg [63:0] dout; |
| 1162 | |
| 1163 | always @ (posedge clk) |
| 1164 | if (load) |
| 1165 | dout <= din; |
| 1166 | else |
| 1167 | dout <= dout; |
| 1168 | |
| 1169 | endmodule |
| 1170 | |
| 1171 | |
| 1172 | module register_load_X66(clk,load,din,dout); |
| 1173 | input clk; |
| 1174 | input load; |
| 1175 | input [65:0] din; |
| 1176 | output [65:0] dout; |
| 1177 | |
| 1178 | wire clk; |
| 1179 | wire load; |
| 1180 | wire [65:0] din; |
| 1181 | reg [65:0] dout; |
| 1182 | |
| 1183 | always @ (posedge clk) |
| 1184 | if (load) |
| 1185 | dout <= din; |
| 1186 | else |
| 1187 | dout <= dout; |
| 1188 | |
| 1189 | endmodule // register_load_X66 |
| 1190 | |
| 1191 | |
| 1192 | |
| 1193 | /* ------------------------------- Pipelines ------------------------------- */ |
| 1194 | module pipeline_4X8(clk,din,dout); |
| 1195 | input clk; |
| 1196 | input [7:0] din; |
| 1197 | output [7:0] dout; |
| 1198 | |
| 1199 | wire [7:0] stage0_dout,stage1_dout,stage2_dout; |
| 1200 | |
| 1201 | register_X8 STAGE0(clk,din,stage0_dout); |
| 1202 | register_X8 STAGE1(clk,stage0_dout,stage1_dout); |
| 1203 | register_X8 STAGE2(clk,stage1_dout,stage2_dout); |
| 1204 | register_X8 STAGE3(clk,stage2_dout,dout); |
| 1205 | |
| 1206 | endmodule |
| 1207 | |
| 1208 | module bit_shifter_en_ld_X32(reset,clk,ld_en,shift_en,shift_in,din,shift_out,dout); |
| 1209 | input reset; |
| 1210 | input clk; |
| 1211 | input ld_en; |
| 1212 | input shift_en; |
| 1213 | input shift_in; |
| 1214 | input [31:0] din; |
| 1215 | output shift_out; |
| 1216 | output [31:0] dout; |
| 1217 | |
| 1218 | |
| 1219 | wire shift_in; |
| 1220 | wire shift_out; |
| 1221 | wire [31:0] din; |
| 1222 | reg [31:0] dout; |
| 1223 | |
| 1224 | always @ (posedge clk) |
| 1225 | if (reset) |
| 1226 | dout <= 0; |
| 1227 | else if (ld_en) |
| 1228 | dout <= din; |
| 1229 | else if (shift_en) |
| 1230 | begin |
| 1231 | dout[0 ] <= shift_in; |
| 1232 | dout[1 ] <= dout[0 ]; |
| 1233 | dout[2 ] <= dout[1 ]; |
| 1234 | dout[3 ] <= dout[2 ]; |
| 1235 | dout[4 ] <= dout[3 ]; |
| 1236 | dout[5 ] <= dout[4 ]; |
| 1237 | dout[6 ] <= dout[5 ]; |
| 1238 | dout[7 ] <= dout[6 ]; |
| 1239 | dout[8 ] <= dout[7 ]; |
| 1240 | dout[9 ] <= dout[8 ]; |
| 1241 | dout[10] <= dout[9 ]; |
| 1242 | dout[11] <= dout[10]; |
| 1243 | dout[12] <= dout[11]; |
| 1244 | dout[13] <= dout[12]; |
| 1245 | dout[14] <= dout[13]; |
| 1246 | dout[15] <= dout[14]; |
| 1247 | dout[16] <= dout[15]; |
| 1248 | dout[17] <= dout[16]; |
| 1249 | dout[18] <= dout[17]; |
| 1250 | dout[19] <= dout[18]; |
| 1251 | dout[20] <= dout[19]; |
| 1252 | dout[21] <= dout[20]; |
| 1253 | dout[22] <= dout[21]; |
| 1254 | dout[23] <= dout[22]; |
| 1255 | dout[24] <= dout[23]; |
| 1256 | dout[25] <= dout[24]; |
| 1257 | dout[26] <= dout[25]; |
| 1258 | dout[27] <= dout[26]; |
| 1259 | dout[28] <= dout[27]; |
| 1260 | dout[29] <= dout[28]; |
| 1261 | dout[30] <= dout[29]; |
| 1262 | dout[31] <= dout[30]; |
| 1263 | end |
| 1264 | |
| 1265 | assign shift_out = dout[31]; |
| 1266 | |
| 1267 | |
| 1268 | endmodule // bit_shifter_en_ld_X32 |
| 1269 | |
| 1270 | module nibble_shifter_X16(clk,din,dout); |
| 1271 | input clk; |
| 1272 | input [3:0] din; |
| 1273 | output [15:0] dout; |
| 1274 | |
| 1275 | FD1 FD1_0(.D(din[0]),.CP(clk),.Q(dout[0])); |
| 1276 | FD1 FD1_1(.D(din[1]),.CP(clk),.Q(dout[1])); |
| 1277 | FD1 FD1_2(.D(din[2]),.CP(clk),.Q(dout[2])); |
| 1278 | FD1 FD1_3(.D(din[3]),.CP(clk),.Q(dout[3])); |
| 1279 | FD1 FD1_4(.D(dout[0]),.CP(clk),.Q(dout[4])); |
| 1280 | FD1 FD1_5(.D(dout[1]),.CP(clk),.Q(dout[5])); |
| 1281 | FD1 FD1_6(.D(dout[2]),.CP(clk),.Q(dout[6])); |
| 1282 | FD1 FD1_7(.D(dout[3]),.CP(clk),.Q(dout[7])); |
| 1283 | FD1 FD1_8(.D(dout[4]),.CP(clk),.Q(dout[8])); |
| 1284 | FD1 FD1_9(.D(dout[5]),.CP(clk),.Q(dout[9])); |
| 1285 | FD1 FD1_10(.D(dout[6]),.CP(clk),.Q(dout[10])); |
| 1286 | FD1 FD1_11(.D(dout[7]),.CP(clk),.Q(dout[11])); |
| 1287 | FD1 FD1_12(.D(dout[8]),.CP(clk),.Q(dout[12])); |
| 1288 | FD1 FD1_13(.D(dout[9]),.CP(clk),.Q(dout[13])); |
| 1289 | FD1 FD1_14(.D(dout[10]),.CP(clk),.Q(dout[14])); |
| 1290 | FD1 FD1_15(.D(dout[11]),.CP(clk),.Q(dout[15])); |
| 1291 | |
| 1292 | endmodule // nibble_shifter_X16 |
| 1293 | |
| 1294 | module byte_shifter_X16(clk,din,dout); // for fedx |
| 1295 | input clk; |
| 1296 | input [7:0] din; |
| 1297 | output [15:0] dout; |
| 1298 | |
| 1299 | wire [7:0] stage0_dout,stage1_dout; |
| 1300 | |
| 1301 | register_X8 STAGE0(clk,din,stage0_dout); |
| 1302 | register_X8 STAGE1(clk,stage0_dout,stage1_dout); |
| 1303 | |
| 1304 | assign dout = {stage0_dout,stage1_dout}; |
| 1305 | |
| 1306 | endmodule // byte_shifter_X16 |
| 1307 | |
| 1308 | module byte_shifter_X64(clk,din,dout); // for cassini |
| 1309 | input clk; |
| 1310 | input [7:0] din; |
| 1311 | output [63:0] dout; |
| 1312 | |
| 1313 | wire [7:0] stage0_dout,stage1_dout,stage2_dout,stage3_dout, |
| 1314 | stage4_dout,stage5_dout,stage6_dout,stage7_dout; |
| 1315 | |
| 1316 | register_X8 STAGE0(clk,din,stage0_dout); |
| 1317 | register_X8 STAGE1(clk,stage0_dout,stage1_dout); |
| 1318 | register_X8 STAGE2(clk,stage1_dout,stage2_dout); |
| 1319 | register_X8 STAGE3(clk,stage2_dout,stage3_dout); |
| 1320 | register_X8 STAGE4(clk,stage3_dout,stage4_dout); |
| 1321 | register_X8 STAGE5(clk,stage4_dout,stage5_dout); |
| 1322 | register_X8 STAGE6(clk,stage5_dout,stage6_dout); |
| 1323 | register_X8 STAGE7(clk,stage6_dout,stage7_dout); |
| 1324 | |
| 1325 | assign dout = {stage0_dout,stage1_dout,stage2_dout,stage3_dout, |
| 1326 | stage4_dout,stage5_dout,stage6_dout,stage7_dout |
| 1327 | }; |
| 1328 | |
| 1329 | endmodule |
| 1330 | |
| 1331 | /* -------------------------------- Counters ------------------------------- */ |
| 1332 | |
| 1333 | module counter_X2(clk,clr,enable,count); |
| 1334 | input clk; |
| 1335 | input clr; |
| 1336 | input enable; |
| 1337 | output [1:0] count; |
| 1338 | |
| 1339 | reg [1:0] count; |
| 1340 | |
| 1341 | always @ (posedge clk) |
| 1342 | if (clr) count <= 0; |
| 1343 | else if (enable) count <= count + 1; |
| 1344 | else count <= count; |
| 1345 | |
| 1346 | endmodule // counter_X2 |
| 1347 | |
| 1348 | module counter_X3(clk,clr,enable,count); |
| 1349 | input clk; |
| 1350 | input clr; |
| 1351 | input enable; |
| 1352 | output [2:0] count; |
| 1353 | |
| 1354 | reg [2:0] count; |
| 1355 | |
| 1356 | always @ (posedge clk) |
| 1357 | if (clr) count <= 0; |
| 1358 | else if (enable) count <= count + 1; |
| 1359 | else count <= count; |
| 1360 | |
| 1361 | endmodule // counter_X3 |
| 1362 | |
| 1363 | module counter_X4(clk,clr,enable,count); |
| 1364 | input clk; |
| 1365 | input clr; |
| 1366 | input enable; |
| 1367 | output [3:0] count; |
| 1368 | |
| 1369 | reg [3:0] count; |
| 1370 | |
| 1371 | always @ (posedge clk) |
| 1372 | if (clr) count <= 0; |
| 1373 | else if (enable) count <= count + 1; |
| 1374 | else count <= count; |
| 1375 | |
| 1376 | endmodule // counter_X4 |
| 1377 | |
| 1378 | module counter_X5(clk,clr,enable,count); |
| 1379 | input clk; |
| 1380 | input clr; |
| 1381 | input enable; |
| 1382 | output [4:0] count; |
| 1383 | |
| 1384 | reg [4:0] count; |
| 1385 | |
| 1386 | always @ (posedge clk) |
| 1387 | if (clr) count <= 0; |
| 1388 | else if (enable) count <= count + 1; |
| 1389 | else count <= count; |
| 1390 | |
| 1391 | endmodule // counter_X5 |
| 1392 | |
| 1393 | module counter_X6(clk,clr,enable,count); |
| 1394 | input clk; |
| 1395 | input clr; |
| 1396 | input enable; |
| 1397 | output [5:0] count; |
| 1398 | |
| 1399 | reg [5:0] count; |
| 1400 | |
| 1401 | always @ (posedge clk) |
| 1402 | if (clr) count <= 0; |
| 1403 | else if (enable) count <= count + 1; |
| 1404 | else count <= count; |
| 1405 | |
| 1406 | endmodule // counter_X6 |
| 1407 | |
| 1408 | module counter_X8(clk,clr,enable,count); |
| 1409 | input clk; |
| 1410 | input clr; |
| 1411 | input enable; |
| 1412 | output [7:0] count; |
| 1413 | |
| 1414 | reg [7:0] count; |
| 1415 | |
| 1416 | always @ (posedge clk) |
| 1417 | if (clr) count <= 0; |
| 1418 | else if (enable) count <= count + 1; |
| 1419 | else count <= count; |
| 1420 | |
| 1421 | endmodule // counter_X8 |
| 1422 | |
| 1423 | module counter_X10(clk,clr,enable,count); |
| 1424 | input clk; |
| 1425 | input clr; |
| 1426 | input enable; |
| 1427 | output [9:0] count; |
| 1428 | |
| 1429 | reg [9:0] count; |
| 1430 | |
| 1431 | always @ (posedge clk) |
| 1432 | if (clr) count <= 0; |
| 1433 | else if (enable) count <= count + 1; |
| 1434 | else count <= count; |
| 1435 | |
| 1436 | endmodule // counter_X10 |
| 1437 | |
| 1438 | module counter_X12(clk,clr,enable,count); |
| 1439 | input clk; |
| 1440 | input clr; |
| 1441 | input enable; |
| 1442 | output [11:0] count; |
| 1443 | |
| 1444 | |
| 1445 | reg [11:0] count; |
| 1446 | |
| 1447 | always @ (posedge clk) |
| 1448 | if (clr) count <= 0; |
| 1449 | else if (enable) count <= count + 1; |
| 1450 | else count <= count; |
| 1451 | |
| 1452 | |
| 1453 | endmodule // counter_X12 |
| 1454 | |
| 1455 | module counter_X14(clk,clr,enable,count); |
| 1456 | input clk; |
| 1457 | input clr; |
| 1458 | input enable; |
| 1459 | output [13:0] count; |
| 1460 | |
| 1461 | reg [13:0] count; |
| 1462 | |
| 1463 | always @ (posedge clk) |
| 1464 | if (clr) count <= 0; |
| 1465 | else if (enable) count <= count + 1; |
| 1466 | else count <= count; |
| 1467 | |
| 1468 | |
| 1469 | endmodule // counter_X14 |
| 1470 | |
| 1471 | |
| 1472 | module counter_X15(clk,clr,enable,count); |
| 1473 | input clk; |
| 1474 | input clr; |
| 1475 | input enable; |
| 1476 | output [14:0] count; |
| 1477 | |
| 1478 | |
| 1479 | reg [14:0] count; |
| 1480 | |
| 1481 | always @ (posedge clk) |
| 1482 | if (clr) count <= 0; |
| 1483 | else if (enable) count <= count + 1; |
| 1484 | else count <= count; |
| 1485 | |
| 1486 | |
| 1487 | endmodule |
| 1488 | |
| 1489 | |
| 1490 | module counter_X16(clk,clr,enable,count); |
| 1491 | input clk; |
| 1492 | input clr; |
| 1493 | input enable; |
| 1494 | output [15:0] count; |
| 1495 | |
| 1496 | |
| 1497 | reg [15:0] count; |
| 1498 | |
| 1499 | always @ (posedge clk) |
| 1500 | if (clr) count <= 0; |
| 1501 | else if (enable) count <= count + 1; |
| 1502 | else count <= count; |
| 1503 | |
| 1504 | |
| 1505 | endmodule // counter_X16 |
| 1506 | |
| 1507 | |
| 1508 | |
| 1509 | module counter_load_X8(clk,clr,enable,load,din,count); |
| 1510 | input clk; |
| 1511 | input clr; |
| 1512 | input enable; |
| 1513 | input load; |
| 1514 | input [7:0] din; |
| 1515 | output [7:0] count; |
| 1516 | |
| 1517 | reg [7:0] count; |
| 1518 | |
| 1519 | always @ (posedge clk) |
| 1520 | if (clr) count <= 0; |
| 1521 | else if (load) count <= din; |
| 1522 | else if (enable) count <= count + 1; |
| 1523 | else count <= count; |
| 1524 | |
| 1525 | endmodule // counter_load_X8 |
| 1526 | |
| 1527 | module counter_rac_load_X8(clk,clr,enable,load,din,count); |
| 1528 | input clk; |
| 1529 | input clr; |
| 1530 | input enable; |
| 1531 | input load; |
| 1532 | input [7:0] din; |
| 1533 | output [7:0] count; |
| 1534 | |
| 1535 | reg [7:0] count; |
| 1536 | |
| 1537 | always @ (posedge clk) |
| 1538 | if (clr) count <= 0; |
| 1539 | else if (load) count <= din; |
| 1540 | else if (enable & (count != {8{1'b1}})) |
| 1541 | count <= count + 1; |
| 1542 | else count <= count; |
| 1543 | |
| 1544 | |
| 1545 | endmodule // counter_rac_load_X8 |
| 1546 | |
| 1547 | module counter_load_X10(clk,clr,enable,load,din,count); |
| 1548 | input clk; |
| 1549 | input clr; |
| 1550 | input enable; |
| 1551 | input load; |
| 1552 | input [9:0] din; |
| 1553 | output [9:0] count; |
| 1554 | |
| 1555 | |
| 1556 | reg [9:0] count; |
| 1557 | |
| 1558 | always @ (posedge clk) |
| 1559 | if (clr) count <= 0; |
| 1560 | else if (load) count <= din; |
| 1561 | else if (enable) count <= count + 1; |
| 1562 | else count <= count; |
| 1563 | |
| 1564 | |
| 1565 | endmodule // counter_load_X10 |
| 1566 | |
| 1567 | module counter_ld_dn_X15(clk,clr,enable,load,din,count); |
| 1568 | input clk; |
| 1569 | input clr; |
| 1570 | input enable; |
| 1571 | input load; |
| 1572 | input [14:0] din; |
| 1573 | output [14:0] count; |
| 1574 | |
| 1575 | |
| 1576 | reg [14:0] count; |
| 1577 | |
| 1578 | always @ (posedge clk) |
| 1579 | if (clr) count <= 0; |
| 1580 | else if (load) count <= din; |
| 1581 | else if (enable) count <= count - 1; |
| 1582 | else count <= count; |
| 1583 | |
| 1584 | |
| 1585 | endmodule // counter_ld_dn_X15 |
| 1586 | |
| 1587 | |
| 1588 | module counter_load_X16(clk,clr,enable,load,din,count); |
| 1589 | input clk; |
| 1590 | input clr; |
| 1591 | input enable; |
| 1592 | input load; |
| 1593 | input [15:0] din; |
| 1594 | output [15:0] count; |
| 1595 | |
| 1596 | reg [15:0] count; |
| 1597 | |
| 1598 | always @ (posedge clk) |
| 1599 | if (clr) count <= 0; |
| 1600 | else if (load) count <= din; |
| 1601 | else if (enable) count <= count + 1; |
| 1602 | else count <= count; |
| 1603 | |
| 1604 | |
| 1605 | endmodule // counter_load_X16 |
| 1606 | |
| 1607 | module counter_rac_load_X16(clk,clr,enable,load,din,count); |
| 1608 | input clk; |
| 1609 | input clr; |
| 1610 | input enable; |
| 1611 | input load; |
| 1612 | input [15:0] din; |
| 1613 | output [15:0] count; |
| 1614 | |
| 1615 | |
| 1616 | reg [15:0] count; |
| 1617 | |
| 1618 | always @ (posedge clk) |
| 1619 | if (clr) count <= 0; |
| 1620 | else if (load) count <= din; |
| 1621 | else if (enable & (count != {16{1'b1}})) |
| 1622 | count <= count + 1; |
| 1623 | else count <= count; |
| 1624 | |
| 1625 | |
| 1626 | endmodule // counter_rac_load_X16 |
| 1627 | |
| 1628 | module counter_load_X17(clk,clr,enable,load,din,count); |
| 1629 | input clk; |
| 1630 | input clr; |
| 1631 | input enable; |
| 1632 | input load; |
| 1633 | input [16:0] din; |
| 1634 | output [16:0] count; |
| 1635 | |
| 1636 | reg [16:0] count; |
| 1637 | |
| 1638 | always @ (posedge clk) |
| 1639 | if (clr) count <= 0; |
| 1640 | else if (load) count <= din; |
| 1641 | else if (enable) count <= count + 1; |
| 1642 | else count <= count; |
| 1643 | |
| 1644 | |
| 1645 | endmodule // counter_load_X17 |
| 1646 | |
| 1647 | module counter_rac_load_X17(clk,clr,enable,load,din,count); |
| 1648 | input clk; |
| 1649 | input clr; |
| 1650 | input enable; |
| 1651 | input load; |
| 1652 | input [16:0] din; |
| 1653 | output [16:0] count; |
| 1654 | |
| 1655 | |
| 1656 | reg [16:0] count; |
| 1657 | |
| 1658 | always @ (posedge clk) |
| 1659 | if (clr) count <= 0; |
| 1660 | else if (load) count <= din; |
| 1661 | else if (enable & (count != {17{1'b1}})) |
| 1662 | count <= count + 1; |
| 1663 | else count <= count; |
| 1664 | |
| 1665 | |
| 1666 | endmodule // counter_rac_load_X17 |
| 1667 | |
| 1668 | module counter_load_X18(clk,clr,enable,load,din,count); |
| 1669 | input clk; |
| 1670 | input clr; |
| 1671 | input enable; |
| 1672 | input load; |
| 1673 | input [17:0] din; |
| 1674 | output [17:0] count; |
| 1675 | |
| 1676 | reg [17:0] count; |
| 1677 | |
| 1678 | always @ (posedge clk) |
| 1679 | if (clr) count <= 0; |
| 1680 | else if (load) count <= din; |
| 1681 | else if (enable) count <= count + 1; |
| 1682 | else count <= count; |
| 1683 | |
| 1684 | |
| 1685 | endmodule // counter_load_X18 |
| 1686 | |
| 1687 | module counter_rac_load_X18(clk,clr,enable,load,din,count); |
| 1688 | input clk; |
| 1689 | input clr; |
| 1690 | input enable; |
| 1691 | input load; |
| 1692 | input [17:0] din; |
| 1693 | output [17:0] count; |
| 1694 | |
| 1695 | |
| 1696 | reg [17:0] count; |
| 1697 | |
| 1698 | always @ (posedge clk) |
| 1699 | if (clr) count <= 0; |
| 1700 | else if (load) count <= din; |
| 1701 | else if (enable & (count != {18{1'b1}})) |
| 1702 | count <= count + 1; |
| 1703 | else count <= count; |
| 1704 | |
| 1705 | |
| 1706 | endmodule // counter_rac_load_X18 |
| 1707 | |
| 1708 | module counter_load_X19(clk,clr,enable,load,din,count); |
| 1709 | input clk; |
| 1710 | input clr; |
| 1711 | input enable; |
| 1712 | input load; |
| 1713 | input [18:0] din; |
| 1714 | output [18:0] count; |
| 1715 | |
| 1716 | reg [18:0] count; |
| 1717 | |
| 1718 | always @ (posedge clk) |
| 1719 | if (clr) count <= 0; |
| 1720 | else if (load) count <= din; |
| 1721 | else if (enable) count <= count + 1; |
| 1722 | else count <= count; |
| 1723 | |
| 1724 | |
| 1725 | endmodule // counter_load_X19 |
| 1726 | |
| 1727 | module counter_rac_load_X19(clk,clr,enable,load,din,count); |
| 1728 | input clk; |
| 1729 | input clr; |
| 1730 | input enable; |
| 1731 | input load; |
| 1732 | input [18:0] din; |
| 1733 | output [18:0] count; |
| 1734 | |
| 1735 | |
| 1736 | reg [18:0] count; |
| 1737 | |
| 1738 | always @ (posedge clk) |
| 1739 | if (clr) count <= 0; |
| 1740 | else if (load) count <= din; |
| 1741 | else if (enable & (count != {19{1'b1}})) |
| 1742 | count <= count + 1; |
| 1743 | else count <= count; |
| 1744 | |
| 1745 | |
| 1746 | endmodule // counter_rac_load_X19 |
| 1747 | |
| 1748 | |
| 1749 | module counter_rac_load_X20(clk,clr,enable,load,din,count); |
| 1750 | input clk; |
| 1751 | input clr; |
| 1752 | input enable; |
| 1753 | input load; |
| 1754 | input [19:0] din; |
| 1755 | output [19:0] count; |
| 1756 | |
| 1757 | |
| 1758 | reg [19:0] count; |
| 1759 | |
| 1760 | always @ (posedge clk) |
| 1761 | if (clr) count <= 0; |
| 1762 | else if (load) count <= din; |
| 1763 | else if (enable & (count != {20{1'b1}})) |
| 1764 | count <= count + 1; |
| 1765 | else count <= count; |
| 1766 | |
| 1767 | |
| 1768 | endmodule // counter_rac_load_X20 |
| 1769 | |
| 1770 | module counter_load_X21(clk,clr,enable,load,din,count); |
| 1771 | input clk; |
| 1772 | input clr; |
| 1773 | input enable; |
| 1774 | input load; |
| 1775 | input [20:0] din; |
| 1776 | output [20:0] count; |
| 1777 | |
| 1778 | reg [20:0] count; |
| 1779 | |
| 1780 | always @ (posedge clk) |
| 1781 | if (clr) count <= 0; |
| 1782 | else if (load) count <= din; |
| 1783 | else if (enable) count <= count + 1; |
| 1784 | else count <= count; |
| 1785 | |
| 1786 | |
| 1787 | endmodule // counter_load_X21 |
| 1788 | |
| 1789 | module counter_rac_load_X21(clk,clr,enable,load,din,count); |
| 1790 | input clk; |
| 1791 | input clr; |
| 1792 | input enable; |
| 1793 | input load; |
| 1794 | input [20:0] din; |
| 1795 | output [20:0] count; |
| 1796 | |
| 1797 | |
| 1798 | reg [20:0] count; |
| 1799 | |
| 1800 | always @ (posedge clk) |
| 1801 | if (clr) count <= 0; |
| 1802 | else if (load) count <= din; |
| 1803 | else if (enable & (count != {21{1'b1}})) |
| 1804 | count <= count + 1; |
| 1805 | else count <= count; |
| 1806 | |
| 1807 | |
| 1808 | endmodule // counter_rac_load_X21 |
| 1809 | |
| 1810 | module counter_load_X24(clk,clr,enable,load,din,count); |
| 1811 | input clk; |
| 1812 | input clr; |
| 1813 | input enable; |
| 1814 | input load; |
| 1815 | input [23:0] din; |
| 1816 | output [23:0] count; |
| 1817 | |
| 1818 | reg [23:0] count; |
| 1819 | |
| 1820 | always @ (posedge clk) |
| 1821 | if (clr) count <= 0; |
| 1822 | else if (load) count <= din; |
| 1823 | else if (enable) count <= count + 1; |
| 1824 | else count <= count; |
| 1825 | |
| 1826 | |
| 1827 | endmodule // counter_load_X24 |
| 1828 | |
| 1829 | module counter_rac_load_X24(clk,clr,enable,load,din,count); |
| 1830 | input clk; |
| 1831 | input clr; |
| 1832 | input enable; |
| 1833 | input load; |
| 1834 | input [23:0] din; |
| 1835 | output [23:0] count; |
| 1836 | |
| 1837 | |
| 1838 | reg [23:0] count; |
| 1839 | |
| 1840 | always @ (posedge clk) |
| 1841 | if (clr) count <= 0; |
| 1842 | else if (load) count <= din; |
| 1843 | else if (enable & (count != {24{1'b1}})) |
| 1844 | count <= count + 1; |
| 1845 | else count <= count; |
| 1846 | |
| 1847 | |
| 1848 | endmodule // counter_rac_load_X24 |
| 1849 | |
| 1850 | module counter_load_X27(clk,clr,enable,load,din,count); |
| 1851 | input clk; |
| 1852 | input clr; |
| 1853 | input enable; |
| 1854 | input load; |
| 1855 | input [26:0] din; |
| 1856 | output [26:0] count; |
| 1857 | |
| 1858 | reg [26:0] count; |
| 1859 | |
| 1860 | always @ (posedge clk) |
| 1861 | if (clr) count <= 0; |
| 1862 | else if (load) count <= din; |
| 1863 | else if (enable) count <= count + 1; |
| 1864 | else count <= count; |
| 1865 | |
| 1866 | |
| 1867 | endmodule // counter_load_X27 |
| 1868 | |
| 1869 | module counter_rac_load_X27(clk,clr,enable,load,din,count); |
| 1870 | input clk; |
| 1871 | input clr; |
| 1872 | input enable; |
| 1873 | input load; |
| 1874 | input [26:0] din; |
| 1875 | output [26:0] count; |
| 1876 | |
| 1877 | |
| 1878 | reg [26:0] count; |
| 1879 | |
| 1880 | always @ (posedge clk) |
| 1881 | if (clr) count <= 0; |
| 1882 | else if (load) count <= din; |
| 1883 | else if (enable & (count != {27{1'b1}})) |
| 1884 | count <= count + 1; |
| 1885 | else count <= count; |
| 1886 | |
| 1887 | |
| 1888 | endmodule // counter_rac_load_X27 |
| 1889 | |
| 1890 | /* ------------------------------------------------------------------------- */ |
| 1891 | |
| 1892 | module counter_ld_dn_X16(clk,clr,enable,load,din,count); |
| 1893 | input clk; |
| 1894 | input clr; |
| 1895 | input enable; |
| 1896 | input load; |
| 1897 | input [15:0] din; |
| 1898 | output [15:0] count; |
| 1899 | |
| 1900 | |
| 1901 | reg [15:0] count; |
| 1902 | |
| 1903 | always @ (posedge clk) |
| 1904 | if (clr) count <= 0; |
| 1905 | else if (load) count <= din; |
| 1906 | else if (enable) count <= count - 1; |
| 1907 | else count <= count; |
| 1908 | |
| 1909 | |
| 1910 | endmodule // counter_ld_dn_X16 |
| 1911 | |
| 1912 | |
| 1913 | module inc_1_2_3_4(clk,clr,inc1,inc2,inc3,inc4,count); |
| 1914 | input clk; |
| 1915 | input clr; |
| 1916 | input inc1; |
| 1917 | input inc2; |
| 1918 | input inc3; |
| 1919 | input inc4; |
| 1920 | output [2:0] count; |
| 1921 | |
| 1922 | wire [2:0] new_count; |
| 1923 | |
| 1924 | function [2:0] counter_logic; |
| 1925 | input clr; |
| 1926 | input inc1; |
| 1927 | input inc2; |
| 1928 | input inc3; |
| 1929 | input inc4; |
| 1930 | input [2:0] count; |
| 1931 | reg [2:0] new_count; |
| 1932 | begin |
| 1933 | if (clr) new_count = 3'h0; |
| 1934 | else |
| 1935 | begin |
| 1936 | case ({inc1,inc2,inc3,inc4}) // synopsys parallel_case full_case |
| 1937 | 4'h0: new_count = count; |
| 1938 | 4'h1: new_count = count + 3'h1; |
| 1939 | 4'h2: new_count = count + 3'h1; |
| 1940 | 4'h3: new_count = count + 3'h2; |
| 1941 | 4'h4: new_count = count + 3'h1; |
| 1942 | 4'h5: new_count = count + 3'h2; |
| 1943 | 4'h6: new_count = count + 3'h2; |
| 1944 | 4'h7: new_count = count + 3'h3; |
| 1945 | 4'h8: new_count = count + 3'h1; |
| 1946 | 4'h9: new_count = count + 3'h2; |
| 1947 | 4'hA: new_count = count + 3'h2; |
| 1948 | 4'hB: new_count = count + 3'h3; |
| 1949 | 4'hC: new_count = count + 3'h2; |
| 1950 | 4'hD: new_count = count + 3'h3; |
| 1951 | 4'hE: new_count = count + 3'h3; |
| 1952 | 4'hF: new_count = count + 3'h4; |
| 1953 | endcase |
| 1954 | end |
| 1955 | counter_logic = new_count; |
| 1956 | end |
| 1957 | endfunction |
| 1958 | assign new_count = counter_logic(clr,inc1,inc2,inc3,inc4,count); |
| 1959 | |
| 1960 | RegDff #(3) inc_1_2_3_4_RegDff(.din(new_count),.clk(clk),.qout(count)); |
| 1961 | |
| 1962 | endmodule // inc_1_2_3_4 |
| 1963 | |
| 1964 | |
| 1965 | module inc_1_2_3_4_5_6_7_8(clk,clr,inc1,inc2,inc3,inc4,inc5,inc6,inc7,inc8,count); |
| 1966 | input clk; |
| 1967 | input clr; |
| 1968 | input inc1; |
| 1969 | input inc2; |
| 1970 | input inc3; |
| 1971 | input inc4; |
| 1972 | input inc5; |
| 1973 | input inc6; |
| 1974 | input inc7; |
| 1975 | input inc8; |
| 1976 | output [2:0] count; |
| 1977 | |
| 1978 | wire [2:0] new_count; |
| 1979 | wire [2:0] add_count_1; |
| 1980 | wire [2:0] add_count_2; |
| 1981 | |
| 1982 | function [2:0] counter_logic_1; |
| 1983 | input inc1; |
| 1984 | input inc2; |
| 1985 | input inc3; |
| 1986 | input inc4; |
| 1987 | reg [2:0] add_count_1; |
| 1988 | begin |
| 1989 | begin |
| 1990 | case ({inc1,inc2,inc3,inc4}) // synopsys parallel_case full_case |
| 1991 | 4'h0: add_count_1 = 3'h0; |
| 1992 | 4'h1: add_count_1 = 3'h1; |
| 1993 | 4'h2: add_count_1 = 3'h1; |
| 1994 | 4'h3: add_count_1 = 3'h2; |
| 1995 | 4'h4: add_count_1 = 3'h1; |
| 1996 | 4'h5: add_count_1 = 3'h2; |
| 1997 | 4'h6: add_count_1 = 3'h2; |
| 1998 | 4'h7: add_count_1 = 3'h3; |
| 1999 | 4'h8: add_count_1 = 3'h1; |
| 2000 | 4'h9: add_count_1 = 3'h2; |
| 2001 | 4'hA: add_count_1 = 3'h2; |
| 2002 | 4'hB: add_count_1 = 3'h3; |
| 2003 | 4'hC: add_count_1 = 3'h2; |
| 2004 | 4'hD: add_count_1 = 3'h3; |
| 2005 | 4'hE: add_count_1 = 3'h3; |
| 2006 | 4'hF: add_count_1 = 3'h4; |
| 2007 | endcase |
| 2008 | end |
| 2009 | counter_logic_1 = add_count_1; |
| 2010 | end |
| 2011 | endfunction |
| 2012 | assign add_count_1 = counter_logic_1(inc1,inc2,inc3,inc4); |
| 2013 | |
| 2014 | function [2:0] counter_logic_2; |
| 2015 | input inc5; |
| 2016 | input inc6; |
| 2017 | input inc7; |
| 2018 | input inc8; |
| 2019 | reg [2:0] add_count_2; |
| 2020 | begin |
| 2021 | begin |
| 2022 | case ({inc5,inc6,inc7,inc8}) // synopsys parallel_case full_case |
| 2023 | 4'h0: add_count_2 = 3'h0; |
| 2024 | 4'h1: add_count_2 = 3'h1; |
| 2025 | 4'h2: add_count_2 = 3'h1; |
| 2026 | 4'h3: add_count_2 = 3'h2; |
| 2027 | 4'h4: add_count_2 = 3'h1; |
| 2028 | 4'h5: add_count_2 = 3'h2; |
| 2029 | 4'h6: add_count_2 = 3'h2; |
| 2030 | 4'h7: add_count_2 = 3'h3; |
| 2031 | 4'h8: add_count_2 = 3'h1; |
| 2032 | 4'h9: add_count_2 = 3'h2; |
| 2033 | 4'hA: add_count_2 = 3'h2; |
| 2034 | 4'hB: add_count_2 = 3'h3; |
| 2035 | 4'hC: add_count_2 = 3'h2; |
| 2036 | 4'hD: add_count_2 = 3'h3; |
| 2037 | 4'hE: add_count_2 = 3'h3; |
| 2038 | 4'hF: add_count_2 = 3'h4; |
| 2039 | endcase |
| 2040 | end |
| 2041 | counter_logic_2 = add_count_2; |
| 2042 | end |
| 2043 | endfunction |
| 2044 | assign add_count_2 = counter_logic_2(inc5,inc6,inc7,inc8); |
| 2045 | |
| 2046 | function [2:0] counter_logic_3; |
| 2047 | input clr; |
| 2048 | input [2:0] add_count_1; |
| 2049 | input [2:0] add_count_2; |
| 2050 | input [2:0] count; |
| 2051 | reg [2:0] new_count; |
| 2052 | begin |
| 2053 | if (clr) new_count = 3'h0; |
| 2054 | else new_count = count + add_count_1 + add_count_2; |
| 2055 | counter_logic_3 = new_count; |
| 2056 | end |
| 2057 | endfunction |
| 2058 | assign new_count = counter_logic_3(clr,add_count_1,add_count_2,count); |
| 2059 | |
| 2060 | RegDff #(3) inc_1_2_3_4_5_6_7_8_RegDff(.din(new_count),.clk(clk),.qout(count)); |
| 2061 | |
| 2062 | endmodule // inc_1_2_3_4_5_6_7_8 |
| 2063 | |
| 2064 | module counter_udh_X3(clk,clr,enable_up,enable_down,count); |
| 2065 | input clk; |
| 2066 | input clr; |
| 2067 | input enable_up; |
| 2068 | input enable_down; |
| 2069 | output [2:0] count; |
| 2070 | |
| 2071 | reg [2:0] count; |
| 2072 | |
| 2073 | always @ (posedge clk) |
| 2074 | if (clr) |
| 2075 | count <= 0; |
| 2076 | else if (enable_up & !enable_down & (count != 3'h7)) |
| 2077 | count <= count + 1; |
| 2078 | else if (!enable_up & enable_down & (count != 3'h0)) |
| 2079 | count <= count - 1; |
| 2080 | else count <= count; |
| 2081 | |
| 2082 | endmodule // counter_udh_X3 |
| 2083 | |
| 2084 | |
| 2085 | |
| 2086 | module inc_1_16(clk,clr,inc1,inc2,inc3,inc4,inc5,inc6,inc7,inc8,inc9,inc10,inc11, |
| 2087 | inc12,inc13,inc14,inc15,inc16,count); |
| 2088 | input clk; |
| 2089 | input clr; |
| 2090 | input inc1; |
| 2091 | input inc2; |
| 2092 | input inc3; |
| 2093 | input inc4; |
| 2094 | input inc5; |
| 2095 | input inc6; |
| 2096 | input inc7; |
| 2097 | input inc8; |
| 2098 | input inc9; |
| 2099 | input inc10; |
| 2100 | input inc11; |
| 2101 | input inc12; |
| 2102 | input inc13; |
| 2103 | input inc14; |
| 2104 | input inc15; |
| 2105 | input inc16; |
| 2106 | output [3:0] count; |
| 2107 | |
| 2108 | wire [2:0] count_1; |
| 2109 | wire [2:0] count_2; |
| 2110 | wire [2:0] count_3; |
| 2111 | wire [2:0] count_4; |
| 2112 | wire [3:0] add_1; |
| 2113 | wire [3:0] add_2; |
| 2114 | wire [3:0] add_3; |
| 2115 | wire [3:0] new_count; |
| 2116 | |
| 2117 | function [2:0] encoder_1; |
| 2118 | input inc1; |
| 2119 | input inc2; |
| 2120 | input inc3; |
| 2121 | input inc4; |
| 2122 | reg [2:0] count_1; |
| 2123 | begin |
| 2124 | begin |
| 2125 | case ({inc1,inc2,inc3,inc4}) // synopsys parallel_case full_case |
| 2126 | 4'h0: count_1 = 3'h0; |
| 2127 | 4'h1: count_1 = 3'h1; |
| 2128 | 4'h2: count_1 = 3'h1; |
| 2129 | 4'h3: count_1 = 3'h2; |
| 2130 | 4'h4: count_1 = 3'h1; |
| 2131 | 4'h5: count_1 = 3'h2; |
| 2132 | 4'h6: count_1 = 3'h2; |
| 2133 | 4'h7: count_1 = 3'h3; |
| 2134 | 4'h8: count_1 = 3'h1; |
| 2135 | 4'h9: count_1 = 3'h2; |
| 2136 | 4'hA: count_1 = 3'h2; |
| 2137 | 4'hB: count_1 = 3'h3; |
| 2138 | 4'hC: count_1 = 3'h2; |
| 2139 | 4'hD: count_1 = 3'h3; |
| 2140 | 4'hE: count_1 = 3'h3; |
| 2141 | 4'hF: count_1 = 3'h4; |
| 2142 | endcase |
| 2143 | end |
| 2144 | encoder_1 = count_1; |
| 2145 | end |
| 2146 | endfunction |
| 2147 | assign count_1 = encoder_1(inc1,inc2,inc3,inc4); |
| 2148 | |
| 2149 | function [2:0] encoder_2; |
| 2150 | input inc5; |
| 2151 | input inc6; |
| 2152 | input inc7; |
| 2153 | input inc8; |
| 2154 | reg [2:0] count_2; |
| 2155 | begin |
| 2156 | begin |
| 2157 | case ({inc5,inc6,inc7,inc8}) // synopsys parallel_case full_case |
| 2158 | 4'h0: count_2 = 3'h0; |
| 2159 | 4'h1: count_2 = 3'h1; |
| 2160 | 4'h2: count_2 = 3'h1; |
| 2161 | 4'h3: count_2 = 3'h2; |
| 2162 | 4'h4: count_2 = 3'h1; |
| 2163 | 4'h5: count_2 = 3'h2; |
| 2164 | 4'h6: count_2 = 3'h2; |
| 2165 | 4'h7: count_2 = 3'h3; |
| 2166 | 4'h8: count_2 = 3'h1; |
| 2167 | 4'h9: count_2 = 3'h2; |
| 2168 | 4'hA: count_2 = 3'h2; |
| 2169 | 4'hB: count_2 = 3'h3; |
| 2170 | 4'hC: count_2 = 3'h2; |
| 2171 | 4'hD: count_2 = 3'h3; |
| 2172 | 4'hE: count_2 = 3'h3; |
| 2173 | 4'hF: count_2 = 3'h4; |
| 2174 | endcase |
| 2175 | end |
| 2176 | encoder_2 = count_2; |
| 2177 | end |
| 2178 | endfunction |
| 2179 | assign count_2 = encoder_2(inc5,inc6,inc7,inc8); |
| 2180 | |
| 2181 | function [2:0] encoder_3; |
| 2182 | input inc9; |
| 2183 | input inc10; |
| 2184 | input inc11; |
| 2185 | input inc12; |
| 2186 | reg [2:0] count_3; |
| 2187 | begin |
| 2188 | begin |
| 2189 | case ({inc9,inc10,inc11,inc12}) // synopsys parallel_case full_case |
| 2190 | 4'h0: count_3 = 3'h0; |
| 2191 | 4'h1: count_3 = 3'h1; |
| 2192 | 4'h2: count_3 = 3'h1; |
| 2193 | 4'h3: count_3 = 3'h2; |
| 2194 | 4'h4: count_3 = 3'h1; |
| 2195 | 4'h5: count_3 = 3'h2; |
| 2196 | 4'h6: count_3 = 3'h2; |
| 2197 | 4'h7: count_3 = 3'h3; |
| 2198 | 4'h8: count_3 = 3'h1; |
| 2199 | 4'h9: count_3 = 3'h2; |
| 2200 | 4'hA: count_3 = 3'h2; |
| 2201 | 4'hB: count_3 = 3'h3; |
| 2202 | 4'hC: count_3 = 3'h2; |
| 2203 | 4'hD: count_3 = 3'h3; |
| 2204 | 4'hE: count_3 = 3'h3; |
| 2205 | 4'hF: count_3 = 3'h4; |
| 2206 | endcase |
| 2207 | end |
| 2208 | encoder_3 = count_3; |
| 2209 | end |
| 2210 | endfunction |
| 2211 | assign count_3 = encoder_3(inc9,inc10,inc11,inc12); |
| 2212 | |
| 2213 | function [2:0] encoder_4; |
| 2214 | input inc13; |
| 2215 | input inc14; |
| 2216 | input inc15; |
| 2217 | input inc16; |
| 2218 | reg [2:0] count_4; |
| 2219 | begin |
| 2220 | begin |
| 2221 | case ({inc13,inc14,inc15,inc16}) // synopsys parallel_case full_case |
| 2222 | 4'h0: count_4 = 3'h0; |
| 2223 | 4'h1: count_4 = 3'h1; |
| 2224 | 4'h2: count_4 = 3'h1; |
| 2225 | 4'h3: count_4 = 3'h2; |
| 2226 | 4'h4: count_4 = 3'h1; |
| 2227 | 4'h5: count_4 = 3'h2; |
| 2228 | 4'h6: count_4 = 3'h2; |
| 2229 | 4'h7: count_4 = 3'h3; |
| 2230 | 4'h8: count_4 = 3'h1; |
| 2231 | 4'h9: count_4 = 3'h2; |
| 2232 | 4'hA: count_4 = 3'h2; |
| 2233 | 4'hB: count_4 = 3'h3; |
| 2234 | 4'hC: count_4 = 3'h2; |
| 2235 | 4'hD: count_4 = 3'h3; |
| 2236 | 4'hE: count_4 = 3'h3; |
| 2237 | 4'hF: count_4 = 3'h4; |
| 2238 | endcase |
| 2239 | end |
| 2240 | encoder_4 = count_4; |
| 2241 | end |
| 2242 | endfunction |
| 2243 | assign count_4 = encoder_4(inc13,inc14,inc15,inc16); |
| 2244 | |
| 2245 | assign add_1 = {1'b0,count_1} + {1'b0,count_2}; |
| 2246 | assign add_2 = {1'b0,count_3} + {1'b0,count_4}; |
| 2247 | assign add_3 = add_1 + add_2; |
| 2248 | |
| 2249 | assign new_count = clr ? 4'h0 : (count + add_3); |
| 2250 | |
| 2251 | RegDff #(4) inc_1_16_RegDff(.din(new_count),.clk(clk),.qout(count)); |
| 2252 | |
| 2253 | |
| 2254 | endmodule // inc_1_16 |
| 2255 | |
| 2256 | |
| 2257 | module counter_udh_X4(clk,clr,enable_up,enable_down,count); |
| 2258 | input clk; |
| 2259 | input clr; |
| 2260 | input enable_up; |
| 2261 | input enable_down; |
| 2262 | output [3:0] count; |
| 2263 | |
| 2264 | reg [3:0] count; |
| 2265 | |
| 2266 | always @ (posedge clk) |
| 2267 | if (clr) |
| 2268 | count <= 0; |
| 2269 | else if (enable_up & !enable_down & (count != 4'hF)) |
| 2270 | count <= count + 1; |
| 2271 | else if (!enable_up & enable_down & (count != 4'h0)) |
| 2272 | count <= count - 1; |
| 2273 | else count <= count; |
| 2274 | |
| 2275 | endmodule // counter_udh_X4 |
| 2276 | |
| 2277 | |
| 2278 | module inc_1_2_dec_1(clk,clr,inc1,inc2,dec,count); |
| 2279 | input clk; |
| 2280 | input clr; |
| 2281 | input inc1; |
| 2282 | input inc2; |
| 2283 | input dec; |
| 2284 | output [1:0] count; |
| 2285 | |
| 2286 | wire [1:0] new_count; |
| 2287 | |
| 2288 | function [1:0] counter_logic; |
| 2289 | input clr; |
| 2290 | input inc1; |
| 2291 | input inc2; |
| 2292 | input dec; |
| 2293 | input [1:0] count; |
| 2294 | reg [1:0] new_count; |
| 2295 | begin |
| 2296 | if (clr) new_count = 2'h0; |
| 2297 | else |
| 2298 | begin |
| 2299 | case ({inc1,inc2,dec}) // synopsys parallel_case full_case |
| 2300 | 3'h0: new_count = count; |
| 2301 | 3'h1: new_count = count - 2'h1; |
| 2302 | 3'h2: new_count = count + 2'h1; |
| 2303 | 3'h3: new_count = count; |
| 2304 | 3'h4: new_count = count + 2'h1; |
| 2305 | 3'h5: new_count = count; |
| 2306 | 3'h6: new_count = count + 2'h2; |
| 2307 | 3'h7: new_count = count + 2'h1; |
| 2308 | endcase |
| 2309 | end |
| 2310 | counter_logic = new_count; |
| 2311 | end |
| 2312 | endfunction |
| 2313 | assign new_count = counter_logic(clr,inc1,inc2,dec,count); |
| 2314 | |
| 2315 | FD1 FD1_0(.D(new_count[0]),.CP(clk),.Q(count[0])); |
| 2316 | FD1 FD1_1(.D(new_count[1]),.CP(clk),.Q(count[1])); |
| 2317 | |
| 2318 | endmodule // inc_1_2_dec_1 |
| 2319 | |
| 2320 | |
| 2321 | /* ------------- ---------- Muxes --------------------------------- */ |
| 2322 | module xMUX_2to1 (din0,din1,sel,dout); |
| 2323 | // variable width row of 2 to 1 muxes; active high output |
| 2324 | |
| 2325 | parameter dwidth = 4; |
| 2326 | input [dwidth-1:0] din0; |
| 2327 | input [dwidth-1:0] din1; |
| 2328 | input sel; |
| 2329 | output [dwidth-1:0] dout; |
| 2330 | |
| 2331 | |
| 2332 | wire [dwidth-1:0] din0; |
| 2333 | wire [dwidth-1:0] din1; |
| 2334 | wire sel; |
| 2335 | reg [dwidth-1:0] dout; |
| 2336 | |
| 2337 | always @ (sel or din0 or din1) |
| 2338 | begin:xMUX_2to1 |
| 2339 | case (sel) // synopsys parallel_case full_case |
| 2340 | 1'b0: dout = din0; |
| 2341 | 1'b1: dout = din1; |
| 2342 | endcase |
| 2343 | end |
| 2344 | |
| 2345 | endmodule // end of xMUX_2to1 |
| 2346 | |
| 2347 | |
| 2348 | |
| 2349 | module xMUX_3to1(dout,sel,din0,din1,din2); |
| 2350 | // variable width row of 3 to 1 muxes; active high output |
| 2351 | parameter dwidth = 2; |
| 2352 | output [dwidth-1:0] dout; |
| 2353 | input [1:0] sel; |
| 2354 | input [dwidth-1:0] din0; |
| 2355 | input [dwidth-1:0] din1; |
| 2356 | input [dwidth-1:0] din2; |
| 2357 | |
| 2358 | |
| 2359 | wire [dwidth-1:0] din0; |
| 2360 | wire [dwidth-1:0] din1; |
| 2361 | wire [dwidth-1:0] din2; |
| 2362 | wire [1:0] sel; |
| 2363 | reg [dwidth-1:0] dout; |
| 2364 | |
| 2365 | always @ (sel or din0 or din1 or din2) |
| 2366 | begin:xMUX_3to1 |
| 2367 | case (sel) // synopsys parallel_case full_case |
| 2368 | 2'b00: dout = din0; |
| 2369 | 2'b01: dout = din1; |
| 2370 | 2'b10: dout = din2; |
| 2371 | 2'b11: dout = din2; |
| 2372 | endcase |
| 2373 | end |
| 2374 | |
| 2375 | endmodule |
| 2376 | |
| 2377 | |
| 2378 | |
| 2379 | module xMUX_4to1 (din0,din1,din2,din3,sel,dout); |
| 2380 | // variable width row of 4 to 1 muxes; active high output |
| 2381 | parameter dwidth = 2; |
| 2382 | output [dwidth-1:0] dout; |
| 2383 | input [1:0] sel; |
| 2384 | input [dwidth-1:0] din0; |
| 2385 | input [dwidth-1:0] din1; |
| 2386 | input [dwidth-1:0] din2; |
| 2387 | input [dwidth-1:0] din3; |
| 2388 | |
| 2389 | |
| 2390 | wire [dwidth-1:0] din0; |
| 2391 | wire [dwidth-1:0] din1; |
| 2392 | wire [dwidth-1:0] din2; |
| 2393 | wire [dwidth-1:0] din3; |
| 2394 | wire [1:0] sel; |
| 2395 | reg [dwidth-1:0] dout; |
| 2396 | |
| 2397 | always @ (sel or din0 or din1 or din2 or din3) |
| 2398 | begin:xMUX_4to1 |
| 2399 | case (sel) // synopsys parallel_case full_case |
| 2400 | 2'b00: dout = din0; |
| 2401 | 2'b01: dout = din1; |
| 2402 | 2'b10: dout = din2; |
| 2403 | 2'b11: dout = din3; |
| 2404 | endcase |
| 2405 | end |
| 2406 | |
| 2407 | |
| 2408 | endmodule // xMUX_4to1 |
| 2409 | |
| 2410 | |
| 2411 | module xMUX_6to1 (dout,sel,din0,din1,din2,din3,din4,din5); |
| 2412 | // variable width row of 6 to 1 muxes; active high output |
| 2413 | parameter dwidth = 2; |
| 2414 | output [dwidth-1:0] dout; |
| 2415 | input [2:0] sel; |
| 2416 | input [dwidth-1:0] din0; |
| 2417 | input [dwidth-1:0] din1; |
| 2418 | input [dwidth-1:0] din2; |
| 2419 | input [dwidth-1:0] din3; |
| 2420 | input [dwidth-1:0] din4; |
| 2421 | input [dwidth-1:0] din5; |
| 2422 | |
| 2423 | |
| 2424 | wire [dwidth-1:0] din0; |
| 2425 | wire [dwidth-1:0] din1; |
| 2426 | wire [dwidth-1:0] din2; |
| 2427 | wire [dwidth-1:0] din3; |
| 2428 | wire [dwidth-1:0] din4; |
| 2429 | wire [dwidth-1:0] din5; |
| 2430 | wire [2:0] sel; |
| 2431 | reg [dwidth-1:0] dout; |
| 2432 | |
| 2433 | always @ (sel or din0 or din1 or din2 or din3 or din4 or din5) |
| 2434 | begin:xMUX_6to1 |
| 2435 | case (sel) // synopsys parallel_case full_case |
| 2436 | 3'h0: dout = din0; |
| 2437 | 3'h1: dout = din1; |
| 2438 | 3'h2: dout = din2; |
| 2439 | 3'h3: dout = din3; |
| 2440 | 3'h4: dout = din4; |
| 2441 | 3'h5: dout = din5; |
| 2442 | default: dout= din0; |
| 2443 | endcase |
| 2444 | end |
| 2445 | |
| 2446 | |
| 2447 | endmodule |
| 2448 | |
| 2449 | |
| 2450 | module func_mux1(dout, select, din1, din0); |
| 2451 | input select; |
| 2452 | input din1, din0; |
| 2453 | output dout; |
| 2454 | |
| 2455 | wire din0; |
| 2456 | wire din1; |
| 2457 | wire select; |
| 2458 | |
| 2459 | |
| 2460 | `ifdef NEPTUNE |
| 2461 | reg dout; |
| 2462 | always @ (select or din1 or din0) |
| 2463 | begin :func_mux |
| 2464 | case (select) // synopsys parallel_case full_case infer_mux |
| 2465 | 1'b0: dout = din0; |
| 2466 | 1'b1: dout = din1; |
| 2467 | endcase |
| 2468 | end |
| 2469 | |
| 2470 | `else // n2 |
| 2471 | wire dout; |
| 2472 | // wire dout = select ? din1 : din0; |
| 2473 | // sel0 is negative signal so the din1 and din0 are swapped. |
| 2474 | cl_a1_clk_mux2_8x n2_FUNC_MUX ( |
| 2475 | .in0(din1), |
| 2476 | .in1(din0), |
| 2477 | .sel0(select), |
| 2478 | .out(dout) |
| 2479 | ); |
| 2480 | |
| 2481 | `endif |
| 2482 | |
| 2483 | endmodule // func_mux1 |
| 2484 | |
| 2485 | |
| 2486 | module lv_mux1(dout, select, din1, din0); |
| 2487 | input select; |
| 2488 | input din1, din0; |
| 2489 | output dout; |
| 2490 | |
| 2491 | wire din0; |
| 2492 | wire din1; |
| 2493 | wire select; |
| 2494 | |
| 2495 | |
| 2496 | `ifdef NEPTUNE |
| 2497 | reg dout; |
| 2498 | always @ (select or din1 or din0) |
| 2499 | begin :lv_mux |
| 2500 | case (select) // synopsys parallel_case full_case infer_mux |
| 2501 | 1'b0: dout = din0; |
| 2502 | 1'b1: dout = din1; |
| 2503 | endcase |
| 2504 | end |
| 2505 | |
| 2506 | `else // n2 |
| 2507 | wire dout; |
| 2508 | // wire dout = select ? din1 : din0; |
| 2509 | // sel0 is negative signal so the din1 and din0 are swapped. |
| 2510 | cl_a1_clk_mux2_8x n2_LV_MUX ( |
| 2511 | .in0(din1), |
| 2512 | .in1(din0), |
| 2513 | .sel0(select), |
| 2514 | .out(dout) |
| 2515 | ); |
| 2516 | |
| 2517 | `endif |
| 2518 | |
| 2519 | endmodule // lv_mux1 |
| 2520 | |
| 2521 | |
| 2522 | module mux_2_1_X1(dout, select, din1, din0); |
| 2523 | input select; |
| 2524 | input din1, din0; |
| 2525 | output dout; |
| 2526 | |
| 2527 | wire din0; |
| 2528 | wire din1; |
| 2529 | wire select; |
| 2530 | reg dout; |
| 2531 | |
| 2532 | always @ (select or din1 or din0) |
| 2533 | begin :mux_2_1_X1 |
| 2534 | case (select) // synopsys parallel_case full_case |
| 2535 | 1'b0: dout = din0; |
| 2536 | 1'b1: dout = din1; |
| 2537 | endcase |
| 2538 | end |
| 2539 | |
| 2540 | endmodule // mux_2_1_X1 |
| 2541 | |
| 2542 | |
| 2543 | // by loj |
| 2544 | module mux_2_1_X2(dout, select, din1, din0); |
| 2545 | input select; |
| 2546 | input [1:0] din1, din0; |
| 2547 | output [1:0] dout; |
| 2548 | |
| 2549 | wire [1:0] din0; |
| 2550 | wire [1:0] din1; |
| 2551 | wire select; |
| 2552 | reg [1:0] dout; |
| 2553 | |
| 2554 | always @ (select or din1 or din0) |
| 2555 | begin :mux_2_1_X2 |
| 2556 | case (select) // synopsys parallel_case full_case |
| 2557 | 1'b0: dout = din0; |
| 2558 | 1'b1: dout = din1; |
| 2559 | endcase |
| 2560 | end |
| 2561 | |
| 2562 | endmodule // mux_2_1_X2 |
| 2563 | |
| 2564 | |
| 2565 | module mux_2_1_X4(dout, select, din1, din0); |
| 2566 | input select; |
| 2567 | input [3:0] din1, din0; |
| 2568 | output [3:0] dout; |
| 2569 | |
| 2570 | wire [3:0] din0; |
| 2571 | wire [3:0] din1; |
| 2572 | wire select; |
| 2573 | reg [3:0] dout; |
| 2574 | |
| 2575 | always @ (select or din1 or din0) |
| 2576 | begin :mux_2_1_X4 |
| 2577 | case (select) // synopsys parallel_case full_case |
| 2578 | 1'b0: dout = din0; |
| 2579 | 1'b1: dout = din1; |
| 2580 | endcase |
| 2581 | end |
| 2582 | |
| 2583 | endmodule // mux_2_1_X4 |
| 2584 | |
| 2585 | module mux_821_X16(din0,din1,din2,din3,din4,din5,din6,din7,select,dout); |
| 2586 | input [2:0] select; |
| 2587 | input [15:0] din0,din1,din2,din3,din4,din5,din6,din7; |
| 2588 | output [15:0] dout; |
| 2589 | |
| 2590 | wire [2:0] select; |
| 2591 | wire [15:0] din0,din1,din2,din3,din4,din5,din6,din7; |
| 2592 | reg [15:0] dout_reg; |
| 2593 | |
| 2594 | always @ (/*AUTOSENSE*/din0 or din1 or din2 or din3 or din4 or din5 |
| 2595 | or din6 or din7 or select) |
| 2596 | begin: mux_821_X16 |
| 2597 | case (select) // synopsys parallel_case full_case |
| 2598 | 3'h0: dout_reg = din0; |
| 2599 | 3'h1: dout_reg = din1; |
| 2600 | 3'h2: dout_reg = din2; |
| 2601 | 3'h3: dout_reg = din3; |
| 2602 | 3'h4: dout_reg = din4; |
| 2603 | 3'h5: dout_reg = din5; |
| 2604 | 3'h6: dout_reg = din6; |
| 2605 | 3'h7: dout_reg = din7; |
| 2606 | endcase |
| 2607 | end |
| 2608 | |
| 2609 | endmodule // mux_821_X16 |
| 2610 | |
| 2611 | module mux_821_X17(din0,din1,din2,din3,din4,din5,din6,din7,select,dout); |
| 2612 | input [2:0] select; |
| 2613 | input [16:0] din0,din1,din2,din3,din4,din5,din6,din7; |
| 2614 | output [16:0] dout; |
| 2615 | |
| 2616 | wire [2:0] select; |
| 2617 | wire [16:0] din0,din1,din2,din3,din4,din5,din6,din7; |
| 2618 | reg [16:0] dout; |
| 2619 | |
| 2620 | always @ (/*AUTOSENSE*/din0 or din1 or din2 or din3 or din4 or din5 |
| 2621 | or din6 or din7 or select) |
| 2622 | begin:mux_821_X17 |
| 2623 | case (select) // synopsys parallel_case full_case |
| 2624 | 3'h0: dout = din0; |
| 2625 | 3'h1: dout = din1; |
| 2626 | 3'h2: dout = din2; |
| 2627 | 3'h3: dout = din3; |
| 2628 | 3'h4: dout = din4; |
| 2629 | 3'h5: dout = din5; |
| 2630 | 3'h6: dout = din6; |
| 2631 | 3'h7: dout = din7; |
| 2632 | endcase |
| 2633 | end |
| 2634 | |
| 2635 | endmodule // mux_821_X17 |
| 2636 | |
| 2637 | module mux_421_X64(din0,din1,din2,din3,select,dout); |
| 2638 | input [1:0] select; |
| 2639 | input [63:0] din0,din1,din2,din3; |
| 2640 | output [63:0] dout; |
| 2641 | |
| 2642 | wire [1:0] select; |
| 2643 | wire [63:0] din0,din1,din2,din3; |
| 2644 | reg [63:0] dout; |
| 2645 | |
| 2646 | always @ (/*AUTOSENSE*/din0 or din1 or din2 or din3 or select) |
| 2647 | begin:mux_421_X64 |
| 2648 | case (select) // synopsys parallel_case full_case |
| 2649 | 2'h0: dout = din0; |
| 2650 | 2'h1: dout = din1; |
| 2651 | 2'h2: dout = din2; |
| 2652 | 2'h3: dout = din3; |
| 2653 | endcase |
| 2654 | end |
| 2655 | |
| 2656 | endmodule // mux_421_X64 |
| 2657 | |
| 2658 | |
| 2659 | module mux_821_X64(din0,din1,din2,din3,din4,din5,din6,din7,select,dout); |
| 2660 | input [2:0] select; |
| 2661 | input [63:0] din0,din1,din2,din3,din4,din5,din6,din7; |
| 2662 | output [63:0] dout; |
| 2663 | |
| 2664 | wire [2:0] select; |
| 2665 | wire [63:0] din0,din1,din2,din3,din4,din5,din6,din7; |
| 2666 | reg [63:0] dout; |
| 2667 | |
| 2668 | always @ (/*AUTOSENSE*/din0 or din1 or din2 or din3 or din4 or din5 |
| 2669 | or din6 or din7 or select) |
| 2670 | begin:mux_821_X64 |
| 2671 | case (select) // synopsys parallel_case full_case |
| 2672 | 3'h0: dout = din0; |
| 2673 | 3'h1: dout = din1; |
| 2674 | 3'h2: dout = din2; |
| 2675 | 3'h3: dout = din3; |
| 2676 | 3'h4: dout = din4; |
| 2677 | 3'h5: dout = din5; |
| 2678 | 3'h6: dout = din6; |
| 2679 | 3'h7: dout = din7; |
| 2680 | endcase |
| 2681 | end |
| 2682 | |
| 2683 | endmodule // mux_821_X64 |
| 2684 | |
| 2685 | |
| 2686 | module mux_1621_X65(din0,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10, |
| 2687 | din11,din12,din13,din14,din15,select,dout); |
| 2688 | input [3:0] select; |
| 2689 | input [64:0] din0,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10,din11, |
| 2690 | din12,din13,din14,din15; |
| 2691 | output [64:0] dout; |
| 2692 | |
| 2693 | wire [3:0] select; |
| 2694 | wire [64:0] din0,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10,din11, |
| 2695 | din12,din13,din14,din15; |
| 2696 | reg [64:0] dout; |
| 2697 | |
| 2698 | always @ (/*AUTOSENSE*/din0 or din1 or din10 or din11 or din12 |
| 2699 | or din13 or din14 or din15 or din2 or din3 or din4 or din5 |
| 2700 | or din6 or din7 or din8 or din9 or select) |
| 2701 | begin:mux_1621_X65 |
| 2702 | case (select) // synopsys parallel_case full_case |
| 2703 | 4'h0: dout = din0; |
| 2704 | 4'h1: dout = din1; |
| 2705 | 4'h2: dout = din2; |
| 2706 | 4'h3: dout = din3; |
| 2707 | 4'h4: dout = din4; |
| 2708 | 4'h5: dout = din5; |
| 2709 | 4'h6: dout = din6; |
| 2710 | 4'h7: dout = din7; |
| 2711 | 4'h8: dout = din8; |
| 2712 | 4'h9: dout = din9; |
| 2713 | 4'hA: dout = din10; |
| 2714 | 4'hB: dout = din11; |
| 2715 | 4'hC: dout = din12; |
| 2716 | 4'hD: dout = din13; |
| 2717 | 4'hE: dout = din14; |
| 2718 | 4'hF: dout = din15; |
| 2719 | endcase |
| 2720 | end |
| 2721 | |
| 2722 | endmodule // mux_1621_X65 |
| 2723 | |
| 2724 | module mux_1621_X66(din0,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10, |
| 2725 | din11,din12,din13,din14,din15,select,dout); |
| 2726 | input [3:0] select; |
| 2727 | input [65:0] din0,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10,din11, |
| 2728 | din12,din13,din14,din15; |
| 2729 | output [65:0] dout; |
| 2730 | |
| 2731 | wire [3:0] select; |
| 2732 | wire [65:0] din0,din1,din2,din3,din4,din5,din6,din7,din8,din9,din10,din11, |
| 2733 | din12,din13,din14,din15; |
| 2734 | reg [65:0] dout; |
| 2735 | |
| 2736 | always @ (/*AUTOSENSE*/din0 or din1 or din10 or din11 or din12 |
| 2737 | or din13 or din14 or din15 or din2 or din3 or din4 or din5 |
| 2738 | or din6 or din7 or din8 or din9 or select) |
| 2739 | begin:mux_1621_X66 |
| 2740 | case (select) // synopsys parallel_case full_case |
| 2741 | 4'h0: dout = din0; |
| 2742 | 4'h1: dout = din1; |
| 2743 | 4'h2: dout = din2; |
| 2744 | 4'h3: dout = din3; |
| 2745 | 4'h4: dout = din4; |
| 2746 | 4'h5: dout = din5; |
| 2747 | 4'h6: dout = din6; |
| 2748 | 4'h7: dout = din7; |
| 2749 | 4'h8: dout = din8; |
| 2750 | 4'h9: dout = din9; |
| 2751 | 4'hA: dout = din10; |
| 2752 | 4'hB: dout = din11; |
| 2753 | 4'hC: dout = din12; |
| 2754 | 4'hD: dout = din13; |
| 2755 | 4'hE: dout = din14; |
| 2756 | 4'hF: dout = din15; |
| 2757 | endcase |
| 2758 | end |
| 2759 | |
| 2760 | endmodule // mux_1621_X65 |
| 2761 | |
| 2762 | |
| 2763 | /* ------ end of big_mac stuff --------------------------------------- */ |
| 2764 | |
| 2765 | module RS_FF (set,rst,clk,reset,qout); |
| 2766 | input set,rst,clk,reset; |
| 2767 | output qout; |
| 2768 | |
| 2769 | reg qout; |
| 2770 | |
| 2771 | always @ (posedge clk) |
| 2772 | if (reset) |
| 2773 | qout <= 0; |
| 2774 | else |
| 2775 | casex({set, rst}) |
| 2776 | 2'b00: qout <= qout;// hold |
| 2777 | 2'bx1: qout <= 0; // rst |
| 2778 | 2'b10: qout <= 1; // set |
| 2779 | endcase |
| 2780 | |
| 2781 | endmodule // RS_FF |
| 2782 | |
| 2783 | module SR_FF (set,rst,clk,reset,qout); |
| 2784 | input set,rst,clk,reset; |
| 2785 | output qout; |
| 2786 | |
| 2787 | reg qout; |
| 2788 | |
| 2789 | always @ (posedge clk) |
| 2790 | if (reset) |
| 2791 | qout <= 0; |
| 2792 | else |
| 2793 | casex({set, rst}) |
| 2794 | 2'b00: qout <= qout;// hold |
| 2795 | 2'b01: qout <= 0; // rst |
| 2796 | 2'b1x: qout <= 1; // set |
| 2797 | endcase |
| 2798 | |
| 2799 | endmodule // SR_FF |
| 2800 | |
| 2801 | |
| 2802 | |
| 2803 | module TFF (toggle,clk,reset,qout); |
| 2804 | input toggle,clk,reset; |
| 2805 | output qout; |
| 2806 | |
| 2807 | reg qout; |
| 2808 | |
| 2809 | always @ (posedge clk) |
| 2810 | if (reset) |
| 2811 | qout <= 0; |
| 2812 | else |
| 2813 | casex(toggle) |
| 2814 | 1'b0: qout <= qout; // hold |
| 2815 | 1'b1: qout <= ~qout;// toggle |
| 2816 | endcase |
| 2817 | |
| 2818 | endmodule // TFF |
| 2819 | |
| 2820 | //***************************** |
| 2821 | //* Leading Edge Digital Pulse Generator |
| 2822 | //***************************** |
| 2823 | |
| 2824 | module pls_gen (clk,in,out); |
| 2825 | input clk; |
| 2826 | input in; |
| 2827 | output out; |
| 2828 | |
| 2829 | wire Qb; |
| 2830 | wire out; |
| 2831 | reg Q; |
| 2832 | |
| 2833 | |
| 2834 | always @ (posedge clk) |
| 2835 | Q <= in; |
| 2836 | |
| 2837 | assign Qb = ~Q; |
| 2838 | assign out = in & Qb; |
| 2839 | |
| 2840 | endmodule // pls_gen |
| 2841 | |
| 2842 | //***************************** |
| 2843 | //* Trailing Edge Digital Pulse Generator |
| 2844 | //***************************** |
| 2845 | |
| 2846 | module pls_gen_trail (clk,in,out); |
| 2847 | input clk; |
| 2848 | input in; |
| 2849 | output out; |
| 2850 | |
| 2851 | wire out; |
| 2852 | reg Q; |
| 2853 | |
| 2854 | |
| 2855 | always @ (posedge clk) |
| 2856 | Q <= in; |
| 2857 | |
| 2858 | assign out = ~in & Q; |
| 2859 | |
| 2860 | endmodule // pls_gen |
| 2861 | |
| 2862 | |
| 2863 | /*********************************** |
| 2864 | * RegDff |
| 2865 | * *********************************/ |
| 2866 | module RegDff (din,clk,qout); |
| 2867 | |
| 2868 | parameter dwidth = 10; |
| 2869 | input clk; |
| 2870 | input [dwidth-1:0] din; |
| 2871 | output [dwidth-1:0] qout; |
| 2872 | |
| 2873 | reg [dwidth-1:0] qout; |
| 2874 | |
| 2875 | always @ (posedge clk) |
| 2876 | qout <= din; |
| 2877 | |
| 2878 | |
| 2879 | endmodule // RegDff |
| 2880 | |
| 2881 | /*********************************** |
| 2882 | * RegDffWithMux |
| 2883 | * *********************************/ |
| 2884 | module RegDffWithMux (din0,din1,sel,clk,qout); |
| 2885 | |
| 2886 | parameter dwidth = 10; |
| 2887 | input clk; |
| 2888 | input [dwidth-1:0] din0; |
| 2889 | input [dwidth-1:0] din1; |
| 2890 | input sel; |
| 2891 | output [dwidth-1:0] qout; |
| 2892 | |
| 2893 | wire [dwidth-1:0] din0; |
| 2894 | wire [dwidth-1:0] din1; |
| 2895 | wire [dwidth-1:0] dout; |
| 2896 | wire [dwidth-1:0] qout; |
| 2897 | wire sel; |
| 2898 | wire clk; |
| 2899 | |
| 2900 | xMUX_2to1 #(dwidth) dout_xMUX_2to1(.din0(din0), |
| 2901 | .din1(din1), |
| 2902 | .sel(sel), |
| 2903 | .dout(dout)); |
| 2904 | |
| 2905 | RegDff #(dwidth) qout_RegDff(.din(dout),.clk(clk),.qout(qout)); |
| 2906 | |
| 2907 | //always @ (posedge clk) |
| 2908 | // qout <= dout; |
| 2909 | |
| 2910 | |
| 2911 | endmodule // RegDffWithMux |
| 2912 | |
| 2913 | |
| 2914 | /***************************** |
| 2915 | * RegRst |
| 2916 | *****************************/ |
| 2917 | module RegRst (clk,reset,din,qout); |
| 2918 | |
| 2919 | parameter dwidth = 10; |
| 2920 | input clk, reset; |
| 2921 | input [dwidth-1:0] din; |
| 2922 | output [dwidth-1:0] qout; |
| 2923 | |
| 2924 | reg [dwidth-1:0] qout; |
| 2925 | |
| 2926 | always @ (posedge clk) |
| 2927 | if (reset) |
| 2928 | qout <= 0; |
| 2929 | else |
| 2930 | qout <= din; |
| 2931 | |
| 2932 | endmodule // RegRst |
| 2933 | |
| 2934 | /***************************** |
| 2935 | * RegRst2 |
| 2936 | *****************************/ |
| 2937 | module RegRst2 (clk,reset,reset_value,din,qout); |
| 2938 | |
| 2939 | parameter dwidth = 10; |
| 2940 | input clk, reset; |
| 2941 | input [dwidth-1:0] reset_value; |
| 2942 | input [dwidth-1:0] din; |
| 2943 | output [dwidth-1:0] qout; |
| 2944 | |
| 2945 | reg [dwidth-1:0] qout; |
| 2946 | |
| 2947 | always @ (posedge clk) |
| 2948 | if (reset) |
| 2949 | qout <= reset_value; |
| 2950 | else |
| 2951 | qout <= din; |
| 2952 | |
| 2953 | endmodule // RegRst2 |
| 2954 | |
| 2955 | |
| 2956 | |
| 2957 | // PlsGen2 2/24/00 |
| 2958 | module PlsGen2 (sig_in,clk,lead,trail); |
| 2959 | input sig_in, clk; |
| 2960 | output lead,trail; |
| 2961 | |
| 2962 | wire sig_in, sig_out,lead,trail; |
| 2963 | FD1 sig_out_FD1(.D(sig_in),.CP(clk),.Q(sig_out)); |
| 2964 | assign lead = sig_in & ~sig_out; |
| 2965 | assign trail= ~sig_in & sig_out; |
| 2966 | |
| 2967 | endmodule // PlsGen2 |
| 2968 | |
| 2969 | |
| 2970 | /* ---------- start of 5bit domain ----------------------------------- */ |
| 2971 | |
| 2972 | module g_cntr_5bit (reset,clk,ce,g_cnt); |
| 2973 | input reset; |
| 2974 | input clk; |
| 2975 | input ce; |
| 2976 | output [4:0] g_cnt; |
| 2977 | /* 0in gray_code |
| 2978 | -var g_cnt |
| 2979 | -clock clk |
| 2980 | -reset reset |
| 2981 | -message "(* 0in test 5bit gray_code counter *)" |
| 2982 | */ |
| 2983 | |
| 2984 | wire [4:0] g_cnt; // current state |
| 2985 | reg [4:0] nx_g_cnt; // next state |
| 2986 | |
| 2987 | parameter g_ZERO = 5'b0_0000, |
| 2988 | g_ONE = 5'b0_0001, |
| 2989 | g_TWO = 5'b0_0011, |
| 2990 | g_THREE = 5'b0_0010, |
| 2991 | g_FOUR = 5'b0_0110, |
| 2992 | g_FIVE = 5'b0_0111, |
| 2993 | g_SIX = 5'b0_0101, |
| 2994 | g_SEVEN = 5'b0_0100, |
| 2995 | g_EIGHT = 5'b0_1100, |
| 2996 | g_NINE = 5'b0_1101, |
| 2997 | g_TEN = 5'b0_1111, |
| 2998 | g_ELEVEN = 5'b0_1110, |
| 2999 | g_TWELVE = 5'b0_1010, |
| 3000 | g_THIRTEEN = 5'b0_1011, |
| 3001 | g_FORTEEN = 5'b0_1001, |
| 3002 | g_FIFTEEN = 5'b0_1000, // reflection |
| 3003 | g_SIXTEEN = 5'b1_1000, // reflection |
| 3004 | g_SEVENTEEN = 5'b1_1001, |
| 3005 | g_EIGHTEEN = 5'b1_1011, |
| 3006 | g_NINETEEN = 5'b1_1010, |
| 3007 | g_TWENTY = 5'b1_1110, |
| 3008 | g_TWENTY_ONE = 5'b1_1111, |
| 3009 | g_TWENTY_TWO = 5'b1_1101, |
| 3010 | g_TWENTY_THREE = 5'b1_1100, |
| 3011 | g_TWENTY_FOUR = 5'b1_0100, |
| 3012 | g_TWENTY_FIVE = 5'b1_0101, |
| 3013 | g_TWENTY_SIX = 5'b1_0111, |
| 3014 | g_TWENTY_SEVEN = 5'b1_0110, |
| 3015 | g_TWENTY_EIGHT = 5'b1_0010, |
| 3016 | g_TWENTY_NINE = 5'b1_0011, |
| 3017 | g_THIRTY = 5'b1_0001, |
| 3018 | g_THIRTY_ONE = 5'b1_0000; |
| 3019 | |
| 3020 | |
| 3021 | // com part |
| 3022 | always @ (ce or g_cnt) |
| 3023 | begin |
| 3024 | nx_g_cnt = g_ZERO; |
| 3025 | if (ce) |
| 3026 | case(g_cnt) // synopsys parallel_case full_case |
| 3027 | g_ZERO : nx_g_cnt = g_ONE; |
| 3028 | g_ONE : nx_g_cnt = g_TWO; |
| 3029 | g_TWO : nx_g_cnt = g_THREE; |
| 3030 | g_THREE : nx_g_cnt = g_FOUR; |
| 3031 | g_FOUR : nx_g_cnt = g_FIVE; |
| 3032 | g_FIVE : nx_g_cnt = g_SIX; |
| 3033 | g_SIX : nx_g_cnt = g_SEVEN; |
| 3034 | g_SEVEN : nx_g_cnt = g_EIGHT; |
| 3035 | g_EIGHT : nx_g_cnt = g_NINE; |
| 3036 | g_NINE : nx_g_cnt = g_TEN; |
| 3037 | g_TEN : nx_g_cnt = g_ELEVEN; |
| 3038 | g_ELEVEN : nx_g_cnt = g_TWELVE; |
| 3039 | g_TWELVE : nx_g_cnt = g_THIRTEEN; |
| 3040 | g_THIRTEEN : nx_g_cnt = g_FORTEEN; |
| 3041 | g_FORTEEN : nx_g_cnt = g_FIFTEEN; |
| 3042 | g_FIFTEEN : nx_g_cnt = g_SIXTEEN; |
| 3043 | g_SIXTEEN : nx_g_cnt = g_SEVENTEEN; |
| 3044 | g_SEVENTEEN : nx_g_cnt = g_EIGHTEEN; |
| 3045 | g_EIGHTEEN : nx_g_cnt = g_NINETEEN; |
| 3046 | g_NINETEEN : nx_g_cnt = g_TWENTY; |
| 3047 | g_TWENTY : nx_g_cnt = g_TWENTY_ONE; |
| 3048 | g_TWENTY_ONE : nx_g_cnt = g_TWENTY_TWO; |
| 3049 | g_TWENTY_TWO : nx_g_cnt = g_TWENTY_THREE; |
| 3050 | g_TWENTY_THREE : nx_g_cnt = g_TWENTY_FOUR; |
| 3051 | g_TWENTY_FOUR : nx_g_cnt = g_TWENTY_FIVE; |
| 3052 | g_TWENTY_FIVE : nx_g_cnt = g_TWENTY_SIX; |
| 3053 | g_TWENTY_SIX : nx_g_cnt = g_TWENTY_SEVEN; |
| 3054 | g_TWENTY_SEVEN : nx_g_cnt = g_TWENTY_EIGHT; |
| 3055 | g_TWENTY_EIGHT : nx_g_cnt = g_TWENTY_NINE; |
| 3056 | g_TWENTY_NINE : nx_g_cnt = g_THIRTY; |
| 3057 | g_THIRTY : nx_g_cnt = g_THIRTY_ONE; |
| 3058 | g_THIRTY_ONE : nx_g_cnt = g_ZERO; |
| 3059 | default : nx_g_cnt = g_ZERO; |
| 3060 | endcase // case(g_cnt) |
| 3061 | else nx_g_cnt = g_cnt; // hold the value |
| 3062 | end // always @ (ce or g_cnt) |
| 3063 | |
| 3064 | // seq part |
| 3065 | RegRst #(5) gb5_cntr_RegRst (.clk(clk), |
| 3066 | .reset(reset), |
| 3067 | .din(nx_g_cnt), |
| 3068 | .qout(g_cnt)); |
| 3069 | |
| 3070 | endmodule // g_cntr_5bit |
| 3071 | |
| 3072 | |
| 3073 | module g2b_5bit (g_cnt,b_cnt); |
| 3074 | input [4:0] g_cnt; |
| 3075 | output [4:0] b_cnt; |
| 3076 | |
| 3077 | reg [4:0] b_cnt; |
| 3078 | |
| 3079 | parameter g_ZERO = 5'b0_0000, |
| 3080 | g_ONE = 5'b0_0001, |
| 3081 | g_TWO = 5'b0_0011, |
| 3082 | g_THREE = 5'b0_0010, |
| 3083 | g_FOUR = 5'b0_0110, |
| 3084 | g_FIVE = 5'b0_0111, |
| 3085 | g_SIX = 5'b0_0101, |
| 3086 | g_SEVEN = 5'b0_0100, |
| 3087 | g_EIGHT = 5'b0_1100, |
| 3088 | g_NINE = 5'b0_1101, |
| 3089 | g_TEN = 5'b0_1111, |
| 3090 | g_ELEVEN = 5'b0_1110, |
| 3091 | g_TWELVE = 5'b0_1010, |
| 3092 | g_THIRTEEN = 5'b0_1011, |
| 3093 | g_FORTEEN = 5'b0_1001, |
| 3094 | g_FIFTEEN = 5'b0_1000, // reflection |
| 3095 | g_SIXTEEN = 5'b1_1000, // reflection |
| 3096 | g_SEVENTEEN = 5'b1_1001, |
| 3097 | g_EIGHTEEN = 5'b1_1011, |
| 3098 | g_NINETEEN = 5'b1_1010, |
| 3099 | g_TWENTY = 5'b1_1110, |
| 3100 | g_TWENTY_ONE = 5'b1_1111, |
| 3101 | g_TWENTY_TWO = 5'b1_1101, |
| 3102 | g_TWENTY_THREE = 5'b1_1100, |
| 3103 | g_TWENTY_FOUR = 5'b1_0100, |
| 3104 | g_TWENTY_FIVE = 5'b1_0101, |
| 3105 | g_TWENTY_SIX = 5'b1_0111, |
| 3106 | g_TWENTY_SEVEN = 5'b1_0110, |
| 3107 | g_TWENTY_EIGHT = 5'b1_0010, |
| 3108 | g_TWENTY_NINE = 5'b1_0011, |
| 3109 | g_THIRTY = 5'b1_0001, |
| 3110 | g_THIRTY_ONE = 5'b1_0000; |
| 3111 | |
| 3112 | |
| 3113 | parameter ZERO = 5'b0_0000, |
| 3114 | ONE = 5'b0_0001, |
| 3115 | TWO = 5'b0_0010, |
| 3116 | THREE = 5'b0_0011, |
| 3117 | FOUR = 5'b0_0100, |
| 3118 | FIVE = 5'b0_0101, |
| 3119 | SIX = 5'b0_0110, |
| 3120 | SEVEN = 5'b0_0111, |
| 3121 | EIGHT = 5'b0_1000, |
| 3122 | NINE = 5'b0_1001, |
| 3123 | TEN = 5'b0_1010, |
| 3124 | ELEVEN = 5'b0_1011, |
| 3125 | TWELVE = 5'b0_1100, |
| 3126 | THIRTEEN = 5'b0_1101, |
| 3127 | FORTEEN = 5'b0_1110, |
| 3128 | FIFTEEN = 5'b0_1111, |
| 3129 | SIXTEEN = 5'b1_0000, |
| 3130 | SEVENTEEN = 5'b1_0001, |
| 3131 | EIGHTEEN = 5'b1_0010, |
| 3132 | NINETEEN = 5'b1_0011, |
| 3133 | TWENTY = 5'b1_0100, |
| 3134 | TWENTY_ONE = 5'b1_0101, |
| 3135 | TWENTY_TWO = 5'b1_0110, |
| 3136 | TWENTY_THREE = 5'b1_0111, |
| 3137 | TWENTY_FOUR = 5'b1_1000, |
| 3138 | TWENTY_FIVE = 5'b1_1001, |
| 3139 | TWENTY_SIX = 5'b1_1010, |
| 3140 | TWENTY_SEVEN = 5'b1_1011, |
| 3141 | TWENTY_EIGHT = 5'b1_1100, |
| 3142 | TWENTY_NINE = 5'b1_1101, |
| 3143 | THIRTY = 5'b1_1110, |
| 3144 | THIRTY_ONE = 5'b1_1111; |
| 3145 | |
| 3146 | // g to b decoder |
| 3147 | always @ (g_cnt) |
| 3148 | begin |
| 3149 | b_cnt = ZERO; |
| 3150 | case(g_cnt) // synopsys parallel_case full_case |
| 3151 | g_ZERO : b_cnt = ZERO; |
| 3152 | g_ONE : b_cnt = ONE; |
| 3153 | g_TWO : b_cnt = TWO; |
| 3154 | g_THREE : b_cnt = THREE; |
| 3155 | g_FOUR : b_cnt = FOUR; |
| 3156 | g_FIVE : b_cnt = FIVE; |
| 3157 | g_SIX : b_cnt = SIX; |
| 3158 | g_SEVEN : b_cnt = SEVEN; |
| 3159 | g_EIGHT : b_cnt = EIGHT; |
| 3160 | g_NINE : b_cnt = NINE; |
| 3161 | g_TEN : b_cnt = TEN; |
| 3162 | g_ELEVEN : b_cnt = ELEVEN; |
| 3163 | g_TWELVE : b_cnt = TWELVE; |
| 3164 | g_THIRTEEN : b_cnt = THIRTEEN; |
| 3165 | g_FORTEEN : b_cnt = FORTEEN; |
| 3166 | g_FIFTEEN : b_cnt = FIFTEEN; |
| 3167 | g_SIXTEEN : b_cnt = SIXTEEN; |
| 3168 | g_SEVENTEEN : b_cnt = SEVENTEEN; |
| 3169 | g_EIGHTEEN : b_cnt = EIGHTEEN; |
| 3170 | g_NINETEEN : b_cnt = NINETEEN; |
| 3171 | g_TWENTY : b_cnt = TWENTY; |
| 3172 | g_TWENTY_ONE : b_cnt = TWENTY_ONE; |
| 3173 | g_TWENTY_TWO : b_cnt = TWENTY_TWO; |
| 3174 | g_TWENTY_THREE : b_cnt = TWENTY_THREE; |
| 3175 | g_TWENTY_FOUR : b_cnt = TWENTY_FOUR; |
| 3176 | g_TWENTY_FIVE : b_cnt = TWENTY_FIVE; |
| 3177 | g_TWENTY_SIX : b_cnt = TWENTY_SIX; |
| 3178 | g_TWENTY_SEVEN : b_cnt = TWENTY_SEVEN; |
| 3179 | g_TWENTY_EIGHT : b_cnt = TWENTY_EIGHT; |
| 3180 | g_TWENTY_NINE : b_cnt = TWENTY_NINE; |
| 3181 | g_THIRTY : b_cnt = THIRTY; |
| 3182 | g_THIRTY_ONE : b_cnt = THIRTY_ONE; |
| 3183 | default : b_cnt = ZERO; |
| 3184 | endcase |
| 3185 | end // always @ (g_cnt) |
| 3186 | |
| 3187 | endmodule // g2b_5bit |
| 3188 | |
| 3189 | |
| 3190 | /* ---------- end of 5bit domain ------------------------------------- */ |
| 3191 | |
| 3192 | |
| 3193 | /* ---------- start of 4bit domain ----------------------------------- */ |
| 3194 | module g_cntr_4bit (reset,clk,ce,g_cnt); |
| 3195 | input reset; |
| 3196 | input clk; |
| 3197 | input ce; |
| 3198 | output [3:0] g_cnt; |
| 3199 | /* 0in gray_code |
| 3200 | -var g_cnt |
| 3201 | -clock clk |
| 3202 | -reset reset |
| 3203 | -message "(* 0in test 4bit gray_code counter *)" |
| 3204 | */ |
| 3205 | |
| 3206 | wire [3:0] g_cnt; // current state |
| 3207 | reg [3:0] nx_g_cnt; // next state |
| 3208 | |
| 3209 | parameter g_ZERO = 4'b0000, |
| 3210 | g_ONE = 4'b0001, |
| 3211 | g_TWO = 4'b0011, |
| 3212 | g_THREE = 4'b0010, |
| 3213 | g_FOUR = 4'b0110, |
| 3214 | g_FIVE = 4'b0111, |
| 3215 | g_SIX = 4'b0101, |
| 3216 | g_SEVEN = 4'b0100, |
| 3217 | g_EIGHT = 4'b1100, |
| 3218 | g_NINE = 4'b1101, |
| 3219 | g_TEN = 4'b1111, |
| 3220 | g_ELEVEN = 4'b1110, |
| 3221 | g_TWELVE = 4'b1010, |
| 3222 | g_THIRTEEN = 4'b1011, |
| 3223 | g_FORTEEN = 4'b1001, |
| 3224 | g_FIFTEEN = 4'b1000; // reflection |
| 3225 | |
| 3226 | |
| 3227 | // com part |
| 3228 | always @ (ce or g_cnt) |
| 3229 | begin |
| 3230 | nx_g_cnt = g_ZERO; |
| 3231 | if (ce) |
| 3232 | case(g_cnt) // synopsys parallel_case full_case |
| 3233 | g_ZERO : nx_g_cnt = g_ONE; |
| 3234 | g_ONE : nx_g_cnt = g_TWO; |
| 3235 | g_TWO : nx_g_cnt = g_THREE; |
| 3236 | g_THREE : nx_g_cnt = g_FOUR; |
| 3237 | g_FOUR : nx_g_cnt = g_FIVE; |
| 3238 | g_FIVE : nx_g_cnt = g_SIX; |
| 3239 | g_SIX : nx_g_cnt = g_SEVEN; |
| 3240 | g_SEVEN : nx_g_cnt = g_EIGHT; |
| 3241 | g_EIGHT : nx_g_cnt = g_NINE; |
| 3242 | g_NINE : nx_g_cnt = g_TEN; |
| 3243 | g_TEN : nx_g_cnt = g_ELEVEN; |
| 3244 | g_ELEVEN : nx_g_cnt = g_TWELVE; |
| 3245 | g_TWELVE : nx_g_cnt = g_THIRTEEN; |
| 3246 | g_THIRTEEN : nx_g_cnt = g_FORTEEN; |
| 3247 | g_FORTEEN : nx_g_cnt = g_FIFTEEN; |
| 3248 | g_FIFTEEN : nx_g_cnt = g_ZERO; |
| 3249 | default : nx_g_cnt = g_ZERO; |
| 3250 | endcase // case(g_cnt) |
| 3251 | else nx_g_cnt = g_cnt; // hold the value |
| 3252 | end // always @ (ce or g_cnt) |
| 3253 | |
| 3254 | // seq part |
| 3255 | RegRst #(4) g_cnt_RegRst (.clk(clk), |
| 3256 | .reset(reset), |
| 3257 | .din(nx_g_cnt), |
| 3258 | .qout(g_cnt)); |
| 3259 | |
| 3260 | endmodule // g_cntr_4bit |
| 3261 | |
| 3262 | |
| 3263 | module g2b_4bit (g_cnt,b_cnt); |
| 3264 | input [3:0] g_cnt; |
| 3265 | output [3:0] b_cnt; |
| 3266 | |
| 3267 | reg [3:0] b_cnt; |
| 3268 | |
| 3269 | parameter g_ZERO = 4'b0000, |
| 3270 | g_ONE = 4'b0001, |
| 3271 | g_TWO = 4'b0011, |
| 3272 | g_THREE = 4'b0010, |
| 3273 | g_FOUR = 4'b0110, |
| 3274 | g_FIVE = 4'b0111, |
| 3275 | g_SIX = 4'b0101, |
| 3276 | g_SEVEN = 4'b0100, |
| 3277 | g_EIGHT = 4'b1100, |
| 3278 | g_NINE = 4'b1101, |
| 3279 | g_TEN = 4'b1111, |
| 3280 | g_ELEVEN = 4'b1110, |
| 3281 | g_TWELVE = 4'b1010, |
| 3282 | g_THIRTEEN = 4'b1011, |
| 3283 | g_FORTEEN = 4'b1001, |
| 3284 | g_FIFTEEN = 4'b1000; // reflection |
| 3285 | |
| 3286 | parameter ZERO = 4'b0000, |
| 3287 | ONE = 4'b0001, |
| 3288 | TWO = 4'b0010, |
| 3289 | THREE = 4'b0011, |
| 3290 | FOUR = 4'b0100, |
| 3291 | FIVE = 4'b0101, |
| 3292 | SIX = 4'b0110, |
| 3293 | SEVEN = 4'b0111, |
| 3294 | EIGHT = 4'b1000, |
| 3295 | NINE = 4'b1001, |
| 3296 | TEN = 4'b1010, |
| 3297 | ELEVEN = 4'b1011, |
| 3298 | TWELVE = 4'b1100, |
| 3299 | THIRTEEN = 4'b1101, |
| 3300 | FORTEEN = 4'b1110, |
| 3301 | FIFTEEN = 4'b1111; |
| 3302 | |
| 3303 | |
| 3304 | |
| 3305 | // g to b decoder |
| 3306 | always @ (g_cnt) |
| 3307 | begin |
| 3308 | b_cnt = ZERO; |
| 3309 | case(g_cnt) // synopsys parallel_case full_case |
| 3310 | g_ZERO : b_cnt = ZERO; |
| 3311 | g_ONE : b_cnt = ONE; |
| 3312 | g_TWO : b_cnt = TWO; |
| 3313 | g_THREE : b_cnt = THREE; |
| 3314 | g_FOUR : b_cnt = FOUR; |
| 3315 | g_FIVE : b_cnt = FIVE; |
| 3316 | g_SIX : b_cnt = SIX; |
| 3317 | g_SEVEN : b_cnt = SEVEN; |
| 3318 | g_EIGHT : b_cnt = EIGHT; |
| 3319 | g_NINE : b_cnt = NINE; |
| 3320 | g_TEN : b_cnt = TEN; |
| 3321 | g_ELEVEN : b_cnt = ELEVEN; |
| 3322 | g_TWELVE : b_cnt = TWELVE; |
| 3323 | g_THIRTEEN : b_cnt = THIRTEEN; |
| 3324 | g_FORTEEN : b_cnt = FORTEEN; |
| 3325 | g_FIFTEEN : b_cnt = FIFTEEN; |
| 3326 | default : b_cnt = ZERO; |
| 3327 | endcase |
| 3328 | end // always @ (g_cnt) |
| 3329 | |
| 3330 | endmodule // g2b_4bit |
| 3331 | |
| 3332 | /* ---------- end of 4bit domain ------------------------------------- */ |
| 3333 | |
| 3334 | |
| 3335 | |
| 3336 | /* ---------- start of 3bit domain ----------------------------------- */ |
| 3337 | |
| 3338 | module g_cntr_3bit (reset,clk,ce,g_cnt); |
| 3339 | input reset; |
| 3340 | input clk; |
| 3341 | input ce; |
| 3342 | output [2:0] g_cnt; |
| 3343 | /* 0in gray_code |
| 3344 | -var g_cnt |
| 3345 | -clock clk |
| 3346 | -reset reset |
| 3347 | -message "(* 0in test 3bit gray_code counter *)" |
| 3348 | */ |
| 3349 | |
| 3350 | wire [2:0] g_cnt; // current state |
| 3351 | reg [2:0] nx_g_cnt; // next state |
| 3352 | |
| 3353 | parameter g_ZERO = 3'b000, |
| 3354 | g_ONE = 3'b001, |
| 3355 | g_TWO = 3'b011, |
| 3356 | g_THREE = 3'b010, |
| 3357 | g_FOUR = 3'b110, |
| 3358 | g_FIVE = 3'b111, |
| 3359 | g_SIX = 3'b101, |
| 3360 | g_SEVEN = 3'b100; // reflection |
| 3361 | |
| 3362 | |
| 3363 | // com part |
| 3364 | always @ (ce or g_cnt) |
| 3365 | begin |
| 3366 | nx_g_cnt = g_ZERO; |
| 3367 | if (ce) |
| 3368 | case(g_cnt) // synopsys parallel_case full_case |
| 3369 | g_ZERO : nx_g_cnt = g_ONE; |
| 3370 | g_ONE : nx_g_cnt = g_TWO; |
| 3371 | g_TWO : nx_g_cnt = g_THREE; |
| 3372 | g_THREE : nx_g_cnt = g_FOUR; |
| 3373 | g_FOUR : nx_g_cnt = g_FIVE; |
| 3374 | g_FIVE : nx_g_cnt = g_SIX; |
| 3375 | g_SIX : nx_g_cnt = g_SEVEN; |
| 3376 | g_SEVEN : nx_g_cnt = g_ZERO; |
| 3377 | default : nx_g_cnt = g_ZERO; |
| 3378 | endcase // case(g_cnt) |
| 3379 | else nx_g_cnt = g_cnt; // hold the value |
| 3380 | end // always @ (ce or g_cnt) |
| 3381 | |
| 3382 | // seq part |
| 3383 | RegRst #(3) g_cnt_RegRst (.clk(clk), |
| 3384 | .reset(reset), |
| 3385 | .din(nx_g_cnt), |
| 3386 | .qout(g_cnt)); |
| 3387 | |
| 3388 | endmodule // g_cntr_3bit |
| 3389 | |
| 3390 | |
| 3391 | module g2b_3bit (g_cnt,b_cnt); |
| 3392 | input [2:0] g_cnt; |
| 3393 | output [2:0] b_cnt; |
| 3394 | |
| 3395 | reg [2:0] b_cnt; |
| 3396 | |
| 3397 | parameter g_ZERO = 3'b000, |
| 3398 | g_ONE = 3'b001, |
| 3399 | g_TWO = 3'b011, |
| 3400 | g_THREE = 3'b010, |
| 3401 | g_FOUR = 3'b110, |
| 3402 | g_FIVE = 3'b111, |
| 3403 | g_SIX = 3'b101, |
| 3404 | g_SEVEN = 3'b100; // reflection |
| 3405 | |
| 3406 | parameter ZERO = 3'b000, |
| 3407 | ONE = 3'b001, |
| 3408 | TWO = 3'b010, |
| 3409 | THREE = 3'b011, |
| 3410 | FOUR = 3'b100, |
| 3411 | FIVE = 3'b101, |
| 3412 | SIX = 3'b110, |
| 3413 | SEVEN = 3'b111; |
| 3414 | |
| 3415 | |
| 3416 | // g to b decoder |
| 3417 | always @ (g_cnt) |
| 3418 | begin |
| 3419 | b_cnt = ZERO; |
| 3420 | case(g_cnt) // synopsys parallel_case full_case |
| 3421 | g_ZERO : b_cnt = ZERO; |
| 3422 | g_ONE : b_cnt = ONE; |
| 3423 | g_TWO : b_cnt = TWO; |
| 3424 | g_THREE : b_cnt = THREE; |
| 3425 | g_FOUR : b_cnt = FOUR; |
| 3426 | g_FIVE : b_cnt = FIVE; |
| 3427 | g_SIX : b_cnt = SIX; |
| 3428 | g_SEVEN : b_cnt = SEVEN; |
| 3429 | default : b_cnt = ZERO; |
| 3430 | endcase |
| 3431 | end // always @ (g_cnt) |
| 3432 | |
| 3433 | endmodule // g2b_3bit |
| 3434 | |
| 3435 | /* ---------- end of 3bit domain ------------------------------------- */ |
| 3436 | |
| 3437 | |
| 3438 | module SYNC_FAST_5bit (din,clk,qout); |
| 3439 | input [4:0] din; |
| 3440 | input clk; |
| 3441 | output [4:0] qout; |
| 3442 | |
| 3443 | FAST_SYNC_CELL bit_0_FAST_SYNC_CELL (.D(din[0]), |
| 3444 | .CP(clk), |
| 3445 | .Q(qout[0])); |
| 3446 | |
| 3447 | FAST_SYNC_CELL bit_1_FAST_SYNC_CELL (.D(din[1]), |
| 3448 | .CP(clk), |
| 3449 | .Q(qout[1])); |
| 3450 | |
| 3451 | FAST_SYNC_CELL bit_2_FAST_SYNC_CELL (.D(din[2]), |
| 3452 | .CP(clk), |
| 3453 | .Q(qout[2])); |
| 3454 | |
| 3455 | FAST_SYNC_CELL bit_3_FAST_SYNC_CELL (.D(din[3]), |
| 3456 | .CP(clk), |
| 3457 | .Q(qout[3])); |
| 3458 | FAST_SYNC_CELL bit_4_FAST_SYNC_CELL (.D(din[4]), |
| 3459 | .CP(clk), |
| 3460 | .Q(qout[4])); |
| 3461 | |
| 3462 | |
| 3463 | endmodule // SYNC_FAST_5bit |
| 3464 | |
| 3465 | module SYNC_5bit (din,clk,qout); |
| 3466 | input [4:0] din; |
| 3467 | input clk; |
| 3468 | output [4:0] qout; |
| 3469 | |
| 3470 | SYNC_CELL bit_0_SYNC_CELL (.D(din[0]), |
| 3471 | .CP(clk), |
| 3472 | .Q(qout[0])); |
| 3473 | |
| 3474 | SYNC_CELL bit_1_SYNC_CELL (.D(din[1]), |
| 3475 | .CP(clk), |
| 3476 | .Q(qout[1])); |
| 3477 | |
| 3478 | SYNC_CELL bit_2_SYNC_CELL (.D(din[2]), |
| 3479 | .CP(clk), |
| 3480 | .Q(qout[2])); |
| 3481 | |
| 3482 | SYNC_CELL bit_3_SYNC_CELL (.D(din[3]), |
| 3483 | .CP(clk), |
| 3484 | .Q(qout[3])); |
| 3485 | SYNC_CELL bit_4_SYNC_CELL (.D(din[4]), |
| 3486 | .CP(clk), |
| 3487 | .Q(qout[4])); |
| 3488 | |
| 3489 | |
| 3490 | endmodule // SYNC_5bit |
| 3491 | |
| 3492 | |
| 3493 | module SYNC_4bit (din,clk,qout); |
| 3494 | input [3:0] din; |
| 3495 | input clk; |
| 3496 | output [3:0] qout; |
| 3497 | |
| 3498 | SYNC_CELL bit_0_SYNC_CELL (.D(din[0]), |
| 3499 | .CP(clk), |
| 3500 | .Q(qout[0])); |
| 3501 | |
| 3502 | SYNC_CELL bit_1_SYNC_CELL (.D(din[1]), |
| 3503 | .CP(clk), |
| 3504 | .Q(qout[1])); |
| 3505 | |
| 3506 | SYNC_CELL bit_2_SYNC_CELL (.D(din[2]), |
| 3507 | .CP(clk), |
| 3508 | .Q(qout[2])); |
| 3509 | |
| 3510 | SYNC_CELL bit_3_SYNC_CELL (.D(din[3]), |
| 3511 | .CP(clk), |
| 3512 | .Q(qout[3])); |
| 3513 | |
| 3514 | endmodule // SYNC_4bit |
| 3515 | |
| 3516 | |
| 3517 | module SYNC_3bit (din,clk,qout); |
| 3518 | input [2:0] din; |
| 3519 | input clk; |
| 3520 | output [2:0] qout; |
| 3521 | |
| 3522 | SYNC_CELL bit_0_SYNC_CELL (.D(din[0]), |
| 3523 | .CP(clk), |
| 3524 | .Q(qout[0])); |
| 3525 | |
| 3526 | SYNC_CELL bit_1_SYNC_CELL (.D(din[1]), |
| 3527 | .CP(clk), |
| 3528 | .Q(qout[1])); |
| 3529 | |
| 3530 | SYNC_CELL bit_2_SYNC_CELL (.D(din[2]), |
| 3531 | .CP(clk), |
| 3532 | .Q(qout[2])); |
| 3533 | |
| 3534 | endmodule // SYNC_3bit |
| 3535 | |
| 3536 | |
| 3537 | module byte_counter ( |
| 3538 | clk, |
| 3539 | reset, |
| 3540 | byte_count_en, |
| 3541 | dv_en_8bit, // data valid enable |
| 3542 | // outputs |
| 3543 | byte_count, |
| 3544 | nx_byte_count |
| 3545 | ); |
| 3546 | input clk; |
| 3547 | input reset; |
| 3548 | input byte_count_en; |
| 3549 | input [7:0] dv_en_8bit; |
| 3550 | // outputs |
| 3551 | output [13:0] byte_count; |
| 3552 | output [13:0] nx_byte_count; |
| 3553 | |
| 3554 | wire [13:0] nx_byte_count; |
| 3555 | wire [13:0] byte_count; |
| 3556 | reg [13:0] addend; |
| 3557 | |
| 3558 | |
| 3559 | /***** byte_count * ****/ |
| 3560 | always @ (byte_count_en or dv_en_8bit) |
| 3561 | if (byte_count_en) |
| 3562 | casex (dv_en_8bit) // synopsys parallel_case full_case |
| 3563 | 8'b1xxxxxxx: addend = 14'd8; |
| 3564 | 8'b01xxxxxx: addend = 14'd7; |
| 3565 | 8'b001xxxxx: addend = 14'd6; |
| 3566 | 8'b0001xxxx: addend = 14'd5; |
| 3567 | 8'b00001xxx: addend = 14'd4; |
| 3568 | 8'b000001xx: addend = 14'd3; |
| 3569 | 8'b0000001x: addend = 14'd2; |
| 3570 | 8'b00000001: addend = 14'd1; |
| 3571 | 8'b00000000: addend = 14'd0; // hold |
| 3572 | default: addend = 14'd0; // hold |
| 3573 | endcase // casex(dv_en_8bit) |
| 3574 | else addend = 14'd0; // hold |
| 3575 | |
| 3576 | assign nx_byte_count = byte_count + addend; |
| 3577 | |
| 3578 | // original total cell: 396 |
| 3579 | // improved total cell: 269 + very fast compilation time |
| 3580 | |
| 3581 | |
| 3582 | // We can only support 16k jumbo packet |
| 3583 | RegRst #(14) byte_count_RegRst (.clk(clk), |
| 3584 | .reset(reset), |
| 3585 | .din(nx_byte_count), |
| 3586 | .qout(byte_count)); |
| 3587 | |
| 3588 | endmodule // byte_counter |
| 3589 | |
| 3590 | |
| 3591 | |
| 3592 | module ones_comp_16bit_adder ( |
| 3593 | addend1, |
| 3594 | addend2, |
| 3595 | sum_big // in big endian format |
| 3596 | ); |
| 3597 | input [15:0] addend1; |
| 3598 | input [15:0] addend2; |
| 3599 | output [15:0] sum_big; // in big endian format |
| 3600 | |
| 3601 | /************************************************************************** |
| 3602 | * the look_ahead_adder: to save one adder for just adding "1", a technique |
| 3603 | * is used. By adding one more bit to look_ahead_adder LSB on both addends |
| 3604 | * and make them '1' then effectively the result is 2'b10. Discard the |
| 3605 | * LSB position to get the effective 1 |
| 3606 | * ************************************************************************/ |
| 3607 | |
| 3608 | wire [17:0] look_ahead_adder = {1'b0, addend1, 1'b1} + {1'b0, addend2, 1'b1}; |
| 3609 | wire [17:0] twos_comp_16bit_adder = {1'b0, addend1, 1'b0} + {1'b0, addend2, 1'b0}; |
| 3610 | wire [15:0] sum_big; |
| 3611 | |
| 3612 | assign sum_big [15:0]= twos_comp_16bit_adder[17] ? look_ahead_adder[16:1]: |
| 3613 | twos_comp_16bit_adder[16:1]; |
| 3614 | |
| 3615 | endmodule // ones_comp_16bit_adder |
| 3616 | |
| 3617 | |
| 3618 | |
| 3619 | module delay_cell (Z,A); |
| 3620 | input A; |
| 3621 | output Z; |
| 3622 | |
| 3623 | wire Z,b; |
| 3624 | assign b = ~A; |
| 3625 | assign Z = ~b; |
| 3626 | |
| 3627 | endmodule // delay_cell |
| 3628 | |
| 3629 | |
| 3630 | module clock_doubler_model(rbc0,rbc1,rbcx2); |
| 3631 | |
| 3632 | input rbc0; // input from external SERDES, clocks odd bytes |
| 3633 | input rbc1; // input from external SERDES, clocks even bytes |
| 3634 | output rbcx2; // doubled version of clocks |
| 3635 | |
| 3636 | wire rbc0_del4ns; // rbc0 delayed 4 ns |
| 3637 | wire rbc1_del4ns; // rbc1 delayed 4 ns |
| 3638 | |
| 3639 | // The following two lines should be replaced with ASIC vendor's delay cell. |
| 3640 | //DEL4ns d_rbc0_del4ns (.A(rbc0),.Z(rbc0_del4ns)); |
| 3641 | //DEL4ns d_rbc1_del4ns (.A(rbc1),.Z(rbc1_del4ns)); |
| 3642 | // vlint flag_unsynthesizable_delay_control off |
| 3643 | assign #4 rbc0_del4ns = rbc0; |
| 3644 | assign #4 rbc1_del4ns = rbc1; |
| 3645 | // vlint flag_unsynthesizable_delay_control on |
| 3646 | |
| 3647 | assign rbcx2 = (~rbc0_del4ns & rbc0) | (~rbc1_del4ns & rbc1); |
| 3648 | |
| 3649 | endmodule |
| 3650 | |
| 3651 | module inv_buffer (z,a); |
| 3652 | input a; |
| 3653 | output z; |
| 3654 | wire z = ~a; |
| 3655 | endmodule // inv_buffer |
| 3656 | |
| 3657 | |
| 3658 | |
| 3659 | module my_buffers (z,a); |
| 3660 | parameter dwidth = 8; |
| 3661 | input [dwidth-1:0] a; |
| 3662 | output [dwidth-1:0] z; |
| 3663 | |
| 3664 | wire [dwidth-1:0] b = ~a; |
| 3665 | wire [dwidth-1:0] z = ~b; |
| 3666 | |
| 3667 | endmodule |
| 3668 | |
| 3669 | |
| 3670 | // 1ns delay |
| 3671 | module DEL1ns(A,Z); |
| 3672 | input A; |
| 3673 | output Z; |
| 3674 | |
| 3675 | wire A,Z; |
| 3676 | // vlint flag_unsynthesizable_delay_control off |
| 3677 | assign #1 Z = A; |
| 3678 | // vlint flag_unsynthesizable_delay_control on |
| 3679 | |
| 3680 | |
| 3681 | endmodule |
| 3682 | |
| 3683 | // ----------------------------------------------------------- |
| 3684 | // NEC relatively balanced (rise/fall) output delay cell spec. |
| 3685 | // ----------------------------------------------------------- |
| 3686 | // Tpd Tpd Tdp of delay circuit |
| 3687 | // cell name Min case Max case Typ (info only) |
| 3688 | // --------- -------- -------- ------ ----------------- |
| 3689 | // TCDLY1VX2 ~200ps ~400ps 300ps 2 levels |
| 3690 | // TCDLY2VX2 ~350ps ~700ps 500ps 4 levels |
| 3691 | // TCDLY3VX2 ~500ps ~1000ps 750ps 6 levels |
| 3692 | |
| 3693 | |
| 3694 | // 2ns delay |
| 3695 | module DEL2ns(A,Z); |
| 3696 | input A; |
| 3697 | output Z; |
| 3698 | |
| 3699 | wire A,Z; |
| 3700 | // vlint flag_unsynthesizable_delay_control off |
| 3701 | assign #2 Z = A; |
| 3702 | // vlint flag_unsynthesizable_delay_control on |
| 3703 | |
| 3704 | |
| 3705 | endmodule |
| 3706 | |
| 3707 | |
| 3708 | module DEL4ns (Z,A); |
| 3709 | input A; |
| 3710 | output Z; |
| 3711 | |
| 3712 | wire A,Z; |
| 3713 | // vlint flag_unsynthesizable_delay_control off |
| 3714 | assign #4 Z = A; |
| 3715 | // vlint flag_unsynthesizable_delay_control on |
| 3716 | |
| 3717 | endmodule |
| 3718 | |
| 3719 | // 5ns delay |
| 3720 | module DEL5ns(A,Z); |
| 3721 | input A; |
| 3722 | output Z; |
| 3723 | |
| 3724 | wire A,Z; |
| 3725 | // vlint flag_unsynthesizable_delay_control off |
| 3726 | assign #5 Z = A; |
| 3727 | // vlint flag_unsynthesizable_delay_control on |
| 3728 | |
| 3729 | endmodule |
| 3730 | |
| 3731 | |
| 3732 | |
| 3733 | /**********************************************************************/ |
| 3734 | /* Project Name : GEM */ |
| 3735 | /* Module Name : DEL_PAT */ |
| 3736 | /* Description : Delay element to aid in meeting hold requirement */ |
| 3737 | /* to lfsr. */ |
| 3738 | /* Assumptions : none */ |
| 3739 | /* */ |
| 3740 | /* */ |
| 3741 | /* Parent module : pcs_lfsr.v */ |
| 3742 | /* Child modules : none */ |
| 3743 | /* Author Name : Linda Cheng */ |
| 3744 | /* Date Created : 11/7/97 */ |
| 3745 | /* */ |
| 3746 | /* Copyright (c) 1994, Sun Microsystems, Inc. */ |
| 3747 | /* Sun Proprietary and Confidential */ |
| 3748 | /* */ |
| 3749 | /* Modifications : none yet */ |
| 3750 | /* Synthesis Notes : none yet */ |
| 3751 | /************************************************************************/ |
| 3752 | |
| 3753 | module DEL2ns_PAT (Z,A); |
| 3754 | input [17:0] A; |
| 3755 | output [17:0] Z; |
| 3756 | |
| 3757 | DEL2ns PAT0_DEL2ns (.Z(Z[0]), .A(A[0])); |
| 3758 | DEL2ns PAT1_DEL2ns (.Z(Z[1]), .A(A[1])); |
| 3759 | DEL2ns PAT2_DEL2ns (.Z(Z[2]), .A(A[2])); |
| 3760 | DEL2ns PAT3_DEL2ns (.Z(Z[3]), .A(A[3])); |
| 3761 | DEL2ns PAT4_DEL2ns (.Z(Z[4]), .A(A[4])); |
| 3762 | DEL2ns PAT5_DEL2ns (.Z(Z[5]), .A(A[5])); |
| 3763 | DEL2ns PAT6_DEL2ns (.Z(Z[6]), .A(A[6])); |
| 3764 | DEL2ns PAT7_DEL2ns (.Z(Z[7]), .A(A[7])); |
| 3765 | DEL2ns PAT8_DEL2ns (.Z(Z[8]), .A(A[8])); |
| 3766 | DEL2ns PAT9_DEL2ns (.Z(Z[9]), .A(A[9])); |
| 3767 | DEL2ns PAT10_DEL2ns (.Z(Z[10]), .A(A[10])); |
| 3768 | DEL2ns PAT11_DEL2ns (.Z(Z[11]), .A(A[11])); |
| 3769 | DEL2ns PAT12_DEL2ns (.Z(Z[12]), .A(A[12])); |
| 3770 | DEL2ns PAT13_DEL2ns (.Z(Z[13]), .A(A[13])); |
| 3771 | DEL2ns PAT14_DEL2ns (.Z(Z[14]), .A(A[14])); |
| 3772 | DEL2ns PAT15_DEL2ns (.Z(Z[15]), .A(A[15])); |
| 3773 | DEL2ns PAT16_DEL2ns (.Z(Z[16]), .A(A[16])); |
| 3774 | DEL2ns PAT17_DEL2ns (.Z(Z[17]), .A(A[17])); |
| 3775 | |
| 3776 | endmodule |
| 3777 | |
| 3778 | |
| 3779 | |
| 3780 | /**************************************************** |
| 3781 | * copy from: /import/cassini/central/asic/LIB/ |
| 3782 | * Used by pcs |
| 3783 | ****************************************************/ |
| 3784 | |
| 3785 | module MUX2TO1 (dout, sel, data0, data1); |
| 3786 | parameter dwidth = 2; |
| 3787 | output [dwidth-1:0] dout; |
| 3788 | input sel; |
| 3789 | input [dwidth-1:0] data0; |
| 3790 | input [dwidth-1:0] data1; |
| 3791 | |
| 3792 | wire [dwidth-1:0] data0; |
| 3793 | wire [dwidth-1:0] data1; |
| 3794 | wire sel; |
| 3795 | reg [dwidth-1:0] dout; |
| 3796 | |
| 3797 | always @ (sel or data0 or data1) |
| 3798 | begin:MUX2TO1 |
| 3799 | case (sel) // synopsys parallel_case full_case |
| 3800 | 1'b0: dout = data0; |
| 3801 | 1'b1: dout = data1; |
| 3802 | endcase |
| 3803 | end |
| 3804 | |
| 3805 | |
| 3806 | endmodule |
| 3807 | |
| 3808 | // but from /vobs/vega_asic/mac/phy/rtl/ |
| 3809 | module MUX3TO1(dout,sel,data0,data1,data2); |
| 3810 | parameter dwidth = 2; |
| 3811 | output [dwidth-1:0] dout; |
| 3812 | input [1:0] sel; |
| 3813 | input [dwidth-1:0] data0; |
| 3814 | input [dwidth-1:0] data1; |
| 3815 | input [dwidth-1:0] data2; |
| 3816 | |
| 3817 | |
| 3818 | wire [dwidth-1:0] data0; |
| 3819 | wire [dwidth-1:0] data1; |
| 3820 | wire [dwidth-1:0] data2; |
| 3821 | wire [1:0] sel; |
| 3822 | reg [dwidth-1:0] dout; |
| 3823 | |
| 3824 | always @ (sel or data0 or data1 or data2) |
| 3825 | begin:MUX3TO1 |
| 3826 | case (sel) // synopsys parallel_case full_case |
| 3827 | 2'b00: dout = data0; |
| 3828 | 2'b01: dout = data1; |
| 3829 | 2'b10: dout = data2; |
| 3830 | 2'b11: dout = data2; |
| 3831 | endcase |
| 3832 | end |
| 3833 | |
| 3834 | endmodule |
| 3835 | |
| 3836 | |
| 3837 | |
| 3838 | module MUX4TO1 (dout, sel, data0, data1, data2, data3); |
| 3839 | parameter dwidth = 2; |
| 3840 | output [dwidth-1:0] dout; |
| 3841 | input [1:0] sel; |
| 3842 | input [dwidth-1:0] data0; |
| 3843 | input [dwidth-1:0] data1; |
| 3844 | input [dwidth-1:0] data2; |
| 3845 | input [dwidth-1:0] data3; |
| 3846 | |
| 3847 | |
| 3848 | wire [dwidth-1:0] data0; |
| 3849 | wire [dwidth-1:0] data1; |
| 3850 | wire [dwidth-1:0] data2; |
| 3851 | wire [dwidth-1:0] data3; |
| 3852 | wire [1:0] sel; |
| 3853 | reg [dwidth-1:0] dout; |
| 3854 | |
| 3855 | always @ (sel or data0 or data1 or data2 or data3) |
| 3856 | begin:MUX4TO1 |
| 3857 | case (sel) // synopsys parallel_case full_case |
| 3858 | 2'b00: dout = data0; |
| 3859 | 2'b01: dout = data1; |
| 3860 | 2'b10: dout = data2; |
| 3861 | 2'b11: dout = data3; |
| 3862 | endcase |
| 3863 | end |
| 3864 | |
| 3865 | endmodule |
| 3866 | |
| 3867 | |
| 3868 | |
| 3869 | module MUX6TO1 (dout,sel,D0,D1,D2,D3,D4,D5); |
| 3870 | parameter dwidth = 2; |
| 3871 | output [dwidth-1:0] dout; |
| 3872 | input [2:0] sel; |
| 3873 | input [dwidth-1:0] D0; |
| 3874 | input [dwidth-1:0] D1; |
| 3875 | input [dwidth-1:0] D2; |
| 3876 | input [dwidth-1:0] D3; |
| 3877 | input [dwidth-1:0] D4; |
| 3878 | input [dwidth-1:0] D5; |
| 3879 | |
| 3880 | |
| 3881 | wire [dwidth-1:0] D0; |
| 3882 | wire [dwidth-1:0] D1; |
| 3883 | wire [dwidth-1:0] D2; |
| 3884 | wire [dwidth-1:0] D3; |
| 3885 | wire [dwidth-1:0] D4; |
| 3886 | wire [dwidth-1:0] D5; |
| 3887 | wire [2:0] sel; |
| 3888 | reg [dwidth-1:0] dout; |
| 3889 | |
| 3890 | always @ (sel or D0 or D1 or D2 or D3 or D4 or D5) |
| 3891 | begin:MUX6TO1 |
| 3892 | case (sel) // synopsys parallel_case full_case |
| 3893 | 3'h0: dout = D0; |
| 3894 | 3'h1: dout = D1; |
| 3895 | 3'h2: dout = D2; |
| 3896 | 3'h3: dout = D3; |
| 3897 | 3'h4: dout = D4; |
| 3898 | 3'h5: dout = D5; |
| 3899 | default: dout= D0; |
| 3900 | endcase |
| 3901 | end |
| 3902 | |
| 3903 | |
| 3904 | endmodule |
| 3905 | |
| 3906 | |
| 3907 | |
| 3908 | module REG (qout, clk, din); |
| 3909 | //non-resettable variable width register |
| 3910 | //only one Q output |
| 3911 | //if used as flop, just instantiate with #1 |
| 3912 | |
| 3913 | parameter dwidth = 2; |
| 3914 | output [dwidth-1:0] qout; |
| 3915 | input clk; |
| 3916 | input [dwidth-1:0] din; |
| 3917 | |
| 3918 | reg [dwidth-1:0] qout; |
| 3919 | |
| 3920 | always @ (posedge clk) |
| 3921 | qout <= din; |
| 3922 | endmodule |
| 3923 | |
| 3924 | |
| 3925 | |
| 3926 | module RREG (qout, clk, rst, din); |
| 3927 | //synchronous reset variable width register |
| 3928 | //active hi reset (rst); |
| 3929 | //only one Q output |
| 3930 | //if used as flop, just instantiate with #1 |
| 3931 | |
| 3932 | parameter dwidth = 2; |
| 3933 | output [dwidth-1:0] qout; |
| 3934 | input clk, rst; |
| 3935 | input [dwidth-1:0] din; |
| 3936 | |
| 3937 | reg [dwidth-1:0] qout; |
| 3938 | |
| 3939 | always @ (posedge clk) |
| 3940 | if (rst) |
| 3941 | qout <= 0; |
| 3942 | else |
| 3943 | qout <= din; |
| 3944 | endmodule |
| 3945 | |
| 3946 | |
| 3947 | |
| 3948 | module SRREG (qout, clk, en, rst, din); |
| 3949 | //synchronous reset variable width register with active hi enable |
| 3950 | //active hi reset (rst); |
| 3951 | //only one Q output |
| 3952 | //if used as flop, just instantiate with #1 |
| 3953 | |
| 3954 | parameter dwidth = 2; |
| 3955 | output [dwidth-1:0] qout; |
| 3956 | input clk, en, rst; |
| 3957 | input [dwidth-1:0] din; |
| 3958 | |
| 3959 | reg [dwidth-1:0] qout; |
| 3960 | |
| 3961 | always @ (posedge clk) |
| 3962 | if (rst) |
| 3963 | qout <= 0; |
| 3964 | else if (en) |
| 3965 | qout <= din; |
| 3966 | else |
| 3967 | qout <= qout; |
| 3968 | endmodule |
| 3969 | |
| 3970 | |
| 3971 | |
| 3972 | module EREG (qout, clk, en, din); |
| 3973 | //synchronous variable width register with active hi enable |
| 3974 | //only one Q output |
| 3975 | //if used as flop, just instantiate with #1 |
| 3976 | |
| 3977 | parameter dwidth = 2; |
| 3978 | output [dwidth-1:0] qout; |
| 3979 | input clk, en; |
| 3980 | input [dwidth-1:0] din; |
| 3981 | |
| 3982 | reg [dwidth-1:0] qout; |
| 3983 | |
| 3984 | always @ (posedge clk) |
| 3985 | if (en) |
| 3986 | qout <= din; |
| 3987 | else |
| 3988 | qout <= qout; |
| 3989 | endmodule |
| 3990 | |
| 3991 | |
| 3992 | |
| 3993 | |
| 3994 | /********************************************************* |
| 3995 | |
| 3996 | Project : Niu |
| 3997 | |
| 3998 | Date : Oct. 2005 |
| 3999 | |
| 4000 | Description : 4 sets of {nand3, nor2, inv, mux2, reg} |
| 4001 | |
| 4002 | Synthesis Notes: |
| 4003 | |
| 4004 | Modification History: |
| 4005 | |
| 4006 | Date Description |
| 4007 | ---- ----------- |
| 4008 | |
| 4009 | ***********************************************************/ |
| 4010 | |
| 4011 | `ifdef NEPTUNE |
| 4012 | module mac_spare_gates ( |
| 4013 | di_nd3, |
| 4014 | di_nd2, |
| 4015 | di_nd1, |
| 4016 | di_nd0, |
| 4017 | di_nr3, |
| 4018 | di_nr2, |
| 4019 | di_nr1, |
| 4020 | di_nr0, |
| 4021 | di_inv, |
| 4022 | di_mx3, |
| 4023 | di_mx2, |
| 4024 | di_mx1, |
| 4025 | di_mx0, |
| 4026 | mx_sel, |
| 4027 | di_reg, |
| 4028 | wt_ena, |
| 4029 | rst, |
| 4030 | si, |
| 4031 | se, |
| 4032 | clk, |
| 4033 | do_nad, |
| 4034 | do_nor, |
| 4035 | do_inv, |
| 4036 | do_mux, |
| 4037 | do_q, |
| 4038 | so |
| 4039 | ); |
| 4040 | |
| 4041 | input [2:0] di_nd3; |
| 4042 | input [2:0] di_nd2; |
| 4043 | input [2:0] di_nd1; |
| 4044 | input [2:0] di_nd0; |
| 4045 | |
| 4046 | input [1:0] di_nr3; |
| 4047 | input [1:0] di_nr2; |
| 4048 | input [1:0] di_nr1; |
| 4049 | input [1:0] di_nr0; |
| 4050 | |
| 4051 | input [3:0] di_inv; |
| 4052 | |
| 4053 | input [1:0] di_mx3; |
| 4054 | input [1:0] di_mx2; |
| 4055 | input [1:0] di_mx1; |
| 4056 | input [1:0] di_mx0; |
| 4057 | input [3:0] mx_sel; |
| 4058 | |
| 4059 | input [3:0] di_reg; |
| 4060 | input [3:0] wt_ena; |
| 4061 | input [3:0] rst; |
| 4062 | |
| 4063 | input si; |
| 4064 | input se; |
| 4065 | input clk; |
| 4066 | |
| 4067 | output [3:0] do_nad; |
| 4068 | output [3:0] do_nor; |
| 4069 | output [3:0] do_inv; |
| 4070 | output [3:0] do_mux; |
| 4071 | output [3:0] do_q; |
| 4072 | output so; |
| 4073 | |
| 4074 | wire [3:0] do_nad; |
| 4075 | wire [3:0] do_nor; |
| 4076 | wire [3:0] do_inv; |
| 4077 | wire [3:0] do_mux; |
| 4078 | wire [3:0] do_q; |
| 4079 | wire so = do_q[3]; |
| 4080 | |
| 4081 | wire [3:0] rst_l; |
| 4082 | |
| 4083 | ND3M1P nand3_3 ( .Z(do_nad[3]), .A(di_nd3[0]), .B(di_nd3[1]), .C(di_nd3[2]) ); |
| 4084 | ND3M1P nand3_2 ( .Z(do_nad[2]), .A(di_nd2[0]), .B(di_nd2[1]), .C(di_nd2[2]) ); |
| 4085 | ND3M1P nand3_1 ( .Z(do_nad[1]), .A(di_nd1[0]), .B(di_nd1[1]), .C(di_nd1[2]) ); |
| 4086 | ND3M1P nand3_0 ( .Z(do_nad[0]), .A(di_nd0[0]), .B(di_nd0[1]), .C(di_nd0[2]) ); |
| 4087 | |
| 4088 | NR2M1P nor_3 ( .Z(do_nor[3]), .A(di_nr3[0]), .B(di_nr3[1]) ); |
| 4089 | NR2M1P nor_2 ( .Z(do_nor[2]), .A(di_nr2[0]), .B(di_nr2[1]) ); |
| 4090 | NR2M1P nor_1 ( .Z(do_nor[1]), .A(di_nr1[0]), .B(di_nr1[1]) ); |
| 4091 | NR2M1P nor_0 ( .Z(do_nor[0]), .A(di_nr0[0]), .B(di_nr0[1]) ); |
| 4092 | |
| 4093 | N1M1P inv_3 ( .Z(do_inv[3]), .A(di_inv[3]) ); |
| 4094 | N1M1P inv_2 ( .Z(do_inv[2]), .A(di_inv[2]) ); |
| 4095 | N1M1P inv_1 ( .Z(do_inv[1]), .A(di_inv[1]) ); |
| 4096 | N1M1P inv_0 ( .Z(do_inv[0]), .A(di_inv[0]) ); |
| 4097 | |
| 4098 | MUX21HM1P mux21_3 ( .Z(do_mux[3]), .A(di_mx3[0]), .B(di_mx3[1]), .S(mx_sel[3]) ); |
| 4099 | MUX21HM1P mux21_2 ( .Z(do_mux[2]), .A(di_mx2[0]), .B(di_mx2[1]), .S(mx_sel[2]) ); |
| 4100 | MUX21HM1P mux21_1 ( .Z(do_mux[1]), .A(di_mx1[0]), .B(di_mx1[1]), .S(mx_sel[1]) ); |
| 4101 | MUX21HM1P mux21_0 ( .Z(do_mux[0]), .A(di_mx0[0]), .B(di_mx0[1]), .S(mx_sel[0]) ); |
| 4102 | |
| 4103 | FD2SL2QM1P regtre_3 ( .Q(do_q[3]), .D(di_reg[3]), .CP(clk), .CD(rst_l[3]), .TI(do_q[2]), .TE(se), .LD(wt_ena[3]) ); |
| 4104 | FD2SL2QM1P regtre_2 ( .Q(do_q[2]), .D(di_reg[2]), .CP(clk), .CD(rst_l[2]), .TI(do_q[1]), .TE(se), .LD(wt_ena[2]) ); |
| 4105 | FD2SL2QM1P regtre_1 ( .Q(do_q[1]), .D(di_reg[1]), .CP(clk), .CD(rst_l[1]), .TI(do_q[0]), .TE(se), .LD(wt_ena[1]) ); |
| 4106 | FD2SL2QM1P regtre_0 ( .Q(do_q[0]), .D(di_reg[0]), .CP(clk), .CD(rst_l[0]), .TI(si), .TE(se), .LD(wt_ena[0]) ); |
| 4107 | |
| 4108 | N1M1P inv_rst_3( .Z(rst_l[3]), .A(rst[3]) ); |
| 4109 | N1M1P inv_rst_2( .Z(rst_l[2]), .A(rst[2]) ); |
| 4110 | N1M1P inv_rst_1( .Z(rst_l[1]), .A(rst[1]) ); |
| 4111 | N1M1P inv_rst_0( .Z(rst_l[0]), .A(rst[0]) ); |
| 4112 | |
| 4113 | endmodule |
| 4114 | |
| 4115 | |
| 4116 | `else // !ifdef NEPTUNE |
| 4117 | `endif |
| 4118 | |
| 4119 | |
| 4120 | |