| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_ipp_sum_lib.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | `timescale 1ns/10ps |
| 37 | |
| 38 | /********************************************************** |
| 39 | *********************************************************** |
| 40 | |
| 41 | Project : Niu |
| 42 | |
| 43 | File name : niu_ipp_sum_lib.v |
| 44 | |
| 45 | Module(s) name : |
| 46 | |
| 47 | Parent modules : niu_ipp_sum.v |
| 48 | |
| 49 | Child modules : |
| 50 | |
| 51 | |
| 52 | Author's name : George Chu |
| 53 | |
| 54 | Date : March. 2004 |
| 55 | |
| 56 | Description : Library cells of the ipp checksum. |
| 57 | |
| 58 | Synthesis Notes: |
| 59 | |
| 60 | Modification History: |
| 61 | |
| 62 | Date Description |
| 63 | ---- ----------- |
| 64 | |
| 65 | ************************************************************ |
| 66 | ***********************************************************/ |
| 67 | |
| 68 | module ipp_sum_reg_r_1 (di, rs, ck, qo); |
| 69 | input di; |
| 70 | input rs; |
| 71 | input ck; |
| 72 | output qo; |
| 73 | |
| 74 | reg qo; |
| 75 | |
| 76 | always @(posedge ck) |
| 77 | qo <= #1 (!rs & di); |
| 78 | |
| 79 | endmodule |
| 80 | |
| 81 | |
| 82 | module ipp_sum_reg_r_2 (di, rs, ck, qo); |
| 83 | input [1:0] di; |
| 84 | input rs; |
| 85 | input ck; |
| 86 | output [1:0] qo; |
| 87 | |
| 88 | reg [1:0] qo; |
| 89 | |
| 90 | always @(posedge ck) |
| 91 | begin |
| 92 | if (rs) |
| 93 | qo <= #1 2'h0; |
| 94 | else |
| 95 | qo <= #1 di[1:0]; |
| 96 | end |
| 97 | |
| 98 | endmodule |
| 99 | |
| 100 | |
| 101 | module ipp_sum_reg_r_4 (di, rs, ck, qo); |
| 102 | input [3:0] di; |
| 103 | input rs; |
| 104 | input ck; |
| 105 | output [3:0] qo; |
| 106 | |
| 107 | reg [3:0] qo; |
| 108 | |
| 109 | always @(posedge ck) |
| 110 | begin |
| 111 | if (rs) |
| 112 | qo <= #1 4'h0; |
| 113 | else |
| 114 | qo <= #1 di[3:0]; |
| 115 | end |
| 116 | |
| 117 | endmodule |
| 118 | |
| 119 | |
| 120 | module ipp_sum_reg_r_8 (di, rs, ck, qo); |
| 121 | input [7:0] di; |
| 122 | input rs; |
| 123 | input ck; |
| 124 | output [7:0] qo; |
| 125 | |
| 126 | reg [7:0] qo; |
| 127 | |
| 128 | always @(posedge ck) |
| 129 | begin |
| 130 | if (rs) |
| 131 | qo <= #1 8'h0; |
| 132 | else |
| 133 | qo <= #1 di[7:0]; |
| 134 | end |
| 135 | |
| 136 | endmodule |
| 137 | |
| 138 | |
| 139 | module ipp_sum_reg_r_9_s0 (di, rs, ck, qo); |
| 140 | input [8:0] di; |
| 141 | input rs; |
| 142 | input ck; |
| 143 | output [8:0] qo; |
| 144 | |
| 145 | reg [8:0] qo; |
| 146 | |
| 147 | always @(posedge ck) |
| 148 | begin |
| 149 | if (rs) |
| 150 | qo <= #1 9'h1; |
| 151 | else |
| 152 | qo <= #1 di[8:0]; |
| 153 | end |
| 154 | |
| 155 | endmodule |
| 156 | |
| 157 | |
| 158 | module ipp_sum_reg_r_16 (di, rs, ck, qo); |
| 159 | input [15:0] di; |
| 160 | input rs; |
| 161 | input ck; |
| 162 | output [15:0] qo; |
| 163 | |
| 164 | reg [15:0] qo; |
| 165 | |
| 166 | always @(posedge ck) |
| 167 | begin |
| 168 | if (rs) |
| 169 | qo <= #1 16'h0; |
| 170 | else |
| 171 | qo <= #1 di[15:0]; |
| 172 | end |
| 173 | |
| 174 | endmodule |
| 175 | |
| 176 | |
| 177 | module ipp_sum_reg_r_128 (di, rs, ck, qo); |
| 178 | input [127:0] di; |
| 179 | input rs; |
| 180 | input ck; |
| 181 | output [127:0] qo; |
| 182 | |
| 183 | reg [127:0] qo; |
| 184 | |
| 185 | always @(posedge ck) |
| 186 | begin |
| 187 | if (rs) |
| 188 | qo <= #1 128'h0; |
| 189 | else |
| 190 | qo <= #1 di[127:0]; |
| 191 | end |
| 192 | |
| 193 | endmodule |
| 194 | |
| 195 | |
| 196 | module ipp_sum_reg_w_r_1 (di, wr, rs, ck, qo); |
| 197 | input di; |
| 198 | input wr; |
| 199 | input rs; |
| 200 | input ck; |
| 201 | output qo; |
| 202 | |
| 203 | reg n_qo; |
| 204 | reg qo; |
| 205 | |
| 206 | always @(di or wr or rs or qo) |
| 207 | case ({rs,wr}) // synopsys parallel_case |
| 208 | (2'h1): n_qo = di; |
| 209 | (2'h2): n_qo = 1'b0; |
| 210 | (2'h3): n_qo = 1'b0; |
| 211 | default: n_qo = qo; |
| 212 | endcase |
| 213 | |
| 214 | always @(posedge ck) |
| 215 | begin |
| 216 | qo <= #1 n_qo; |
| 217 | end |
| 218 | |
| 219 | endmodule |
| 220 | |
| 221 | |
| 222 | module ipp_sum_reg_w_r_2 (di, wr, rs, ck, qo); |
| 223 | input [1:0] di; |
| 224 | input wr; |
| 225 | input rs; |
| 226 | input ck; |
| 227 | output [1:0] qo; |
| 228 | |
| 229 | reg [1:0] n_qo; |
| 230 | reg [1:0] qo; |
| 231 | |
| 232 | always @(di or wr or rs or qo) |
| 233 | case ({rs,wr}) // synopsys parallel_case |
| 234 | (2'h1): n_qo = di[1:0]; |
| 235 | (2'h2): n_qo = 2'b0; |
| 236 | (2'h3): n_qo = 2'b0; |
| 237 | default: n_qo = qo[1:0]; |
| 238 | endcase |
| 239 | |
| 240 | always @(posedge ck) |
| 241 | begin |
| 242 | qo <= #1 n_qo[1:0]; |
| 243 | end |
| 244 | |
| 245 | endmodule |
| 246 | |
| 247 | |
| 248 | module ipp_sum_reg_w_r_4 (di, wr, rs, ck, qo); |
| 249 | input [3:0] di; |
| 250 | input wr; |
| 251 | input rs; |
| 252 | input ck; |
| 253 | output [3:0] qo; |
| 254 | |
| 255 | reg [3:0] n_qo; |
| 256 | reg [3:0] qo; |
| 257 | |
| 258 | always @(di or wr or rs or qo) |
| 259 | case ({rs,wr}) // synopsys parallel_case |
| 260 | (2'h1): n_qo = di[3:0]; |
| 261 | (2'h2): n_qo = 4'b0; |
| 262 | (2'h3): n_qo = 4'b0; |
| 263 | default: n_qo = qo[3:0]; |
| 264 | endcase |
| 265 | |
| 266 | always @(posedge ck) |
| 267 | begin |
| 268 | qo <= #1 n_qo[3:0]; |
| 269 | end |
| 270 | |
| 271 | endmodule |
| 272 | |
| 273 | |
| 274 | module ipp_sum_reg_w_r_13 (di, wr, rs, ck, qo); |
| 275 | input [12:0] di; |
| 276 | input wr; |
| 277 | input rs; |
| 278 | input ck; |
| 279 | output [12:0] qo; |
| 280 | |
| 281 | reg [12:0] n_qo; |
| 282 | reg [12:0] qo; |
| 283 | |
| 284 | always @(di or wr or rs or qo) |
| 285 | case ({rs,wr}) // synopsys parallel_case |
| 286 | (2'h1): n_qo = di[12:0]; |
| 287 | (2'h2): n_qo = 13'b0; |
| 288 | (2'h3): n_qo = 13'b0; |
| 289 | default: n_qo = qo[12:0]; |
| 290 | endcase |
| 291 | |
| 292 | always @(posedge ck) |
| 293 | begin |
| 294 | qo <= #1 n_qo[12:0]; |
| 295 | end |
| 296 | |
| 297 | endmodule |
| 298 | |
| 299 | |
| 300 | module ipp_sum_reg_w_r_16 (di, wr, rs, ck, qo); |
| 301 | input [15:0] di; |
| 302 | input wr; |
| 303 | input rs; |
| 304 | input ck; |
| 305 | output [15:0] qo; |
| 306 | |
| 307 | reg [15:0] n_qo; |
| 308 | reg [15:0] qo; |
| 309 | |
| 310 | always @(di or wr or rs or qo) |
| 311 | case ({rs,wr}) // synopsys parallel_case |
| 312 | (2'h1): n_qo = di[15:0]; |
| 313 | (2'h2): n_qo = 16'b0; |
| 314 | (2'h3): n_qo = 16'b0; |
| 315 | default: n_qo = qo[15:0]; |
| 316 | endcase |
| 317 | |
| 318 | always @(posedge ck) |
| 319 | begin |
| 320 | qo <= #1 n_qo[15:0]; |
| 321 | end |
| 322 | |
| 323 | endmodule |
| 324 | |
| 325 | |
| 326 | module ipp_sum_reg_w_r_17 (di, wr, rs, ck, qo); |
| 327 | input [16:0] di; |
| 328 | input wr; |
| 329 | input rs; |
| 330 | input ck; |
| 331 | output [16:0] qo; |
| 332 | |
| 333 | reg [16:0] n_qo; |
| 334 | reg [16:0] qo; |
| 335 | |
| 336 | always @(di or wr or rs or qo) |
| 337 | case ({rs,wr}) // synopsys parallel_case |
| 338 | (2'h1): n_qo = di[16:0]; |
| 339 | (2'h2): n_qo = 17'b0; |
| 340 | (2'h3): n_qo = 17'b0; |
| 341 | default: n_qo = qo[16:0]; |
| 342 | endcase |
| 343 | |
| 344 | always @(posedge ck) |
| 345 | begin |
| 346 | qo <= #1 n_qo[16:0]; |
| 347 | end |
| 348 | |
| 349 | endmodule |
| 350 | |
| 351 | |
| 352 | module ipp_sum_reg_w_r_23 (di, wr, rs, ck, qo); |
| 353 | input [22:0] di; |
| 354 | input wr; |
| 355 | input rs; |
| 356 | input ck; |
| 357 | output [22:0] qo; |
| 358 | |
| 359 | reg [22:0] n_qo; |
| 360 | reg [22:0] qo; |
| 361 | |
| 362 | always @(di or wr or rs or qo) |
| 363 | case ({rs,wr}) // synopsys parallel_case |
| 364 | (2'h1): n_qo = di[22:0]; |
| 365 | (2'h2): n_qo = 23'b0; |
| 366 | (2'h3): n_qo = 23'b0; |
| 367 | default: n_qo = qo[22:0]; |
| 368 | endcase |
| 369 | |
| 370 | always @(posedge ck) |
| 371 | begin |
| 372 | qo <= #1 n_qo[22:0]; |
| 373 | end |
| 374 | |
| 375 | endmodule |
| 376 | |
| 377 | |
| 378 | module ipp_sum_cnt_i_r_8 ( incr, rs, ck, qo); |
| 379 | input incr; |
| 380 | input rs; |
| 381 | input ck; |
| 382 | output [7:0] qo; |
| 383 | |
| 384 | reg [7:0] qo; |
| 385 | |
| 386 | always @(posedge ck) |
| 387 | begin |
| 388 | if (rs) |
| 389 | qo <= #1 8'h0; |
| 390 | else if (incr) |
| 391 | qo <= #1 (qo[7:0] + 8'h1); |
| 392 | else |
| 393 | qo <= #1 qo[7:0]; |
| 394 | end |
| 395 | |
| 396 | endmodule |
| 397 | |
| 398 | |
| 399 | module ipp_sum_dev_00_00(in1, in2, out); |
| 400 | input [15:0] in1; |
| 401 | input [15:0] in2; |
| 402 | output [16:0] out; |
| 403 | |
| 404 | wire [16:0] out; |
| 405 | |
| 406 | assign out = {1'b0,in1[15:0]} + {1'b0,in2[15:0]}; |
| 407 | |
| 408 | endmodule |
| 409 | |
| 410 | |
| 411 | module ipp_sum_dev_00_01(in1, in2, out); |
| 412 | input [15:0] in1; |
| 413 | input [15:0] in2; |
| 414 | output [15:0] out; |
| 415 | |
| 416 | wire [15:0] out; |
| 417 | |
| 418 | assign out = in1[15:0] + in2[15:0] + 16'h1; |
| 419 | |
| 420 | endmodule |
| 421 | |
| 422 | |
| 423 | module ipp_sum_dev_01_0q (inp_wd3, inp_wd2, inp_wd1, inp_wrd, |
| 424 | byt_ena, sel_awd, sel_add, |
| 425 | clr, clk, |
| 426 | prt_cksum, cksum_fail); |
| 427 | input [15:0] inp_wd3; |
| 428 | input [15:0] inp_wd2; |
| 429 | input [15:0] inp_wd1; |
| 430 | input [15:0] inp_wrd; |
| 431 | input [1:0] byt_ena; |
| 432 | input [1:0] sel_awd; |
| 433 | input sel_add; |
| 434 | input clr; |
| 435 | input clk; |
| 436 | output [15:0] prt_cksum; |
| 437 | output cksum_fail; |
| 438 | |
| 439 | reg [15:0] sum_wrd; |
| 440 | wire [15:0] prt_cksum = ~sum_wrd[15:0]; |
| 441 | |
| 442 | wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]}; |
| 443 | reg [15:0] out2; |
| 444 | wire [16:0] out3a; |
| 445 | wire [15:0] out3b; |
| 446 | wire [15:0] out4; |
| 447 | wire [15:0] out5; |
| 448 | |
| 449 | wire cksum_fail = |(~out5[15:0]); |
| 450 | |
| 451 | always @(sel_awd or |
| 452 | out1 or inp_wd1 or inp_wd2 or inp_wd3) |
| 453 | case (sel_awd) // synopsys parallel_case |
| 454 | (2'h0): out2 = out1[15:0]; |
| 455 | (2'h1): out2 = inp_wd1[15:0]; |
| 456 | (2'h2): out2 = inp_wd2[15:0]; |
| 457 | (2'h3): out2 = inp_wd3[15:0]; |
| 458 | default: out2 = out1[15:0]; |
| 459 | endcase |
| 460 | |
| 461 | ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3a[16:0])); |
| 462 | ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3b[15:0])); |
| 463 | |
| 464 | assign out4 = out3a[16] ? out3b[15:0] : out3a[15:0]; |
| 465 | assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0]; |
| 466 | |
| 467 | always @(posedge clk) begin |
| 468 | sum_wrd <= #1 ({16{!clr}} & out5[15:0]); |
| 469 | end |
| 470 | |
| 471 | endmodule |
| 472 | |
| 473 | |
| 474 | module ipp_sum_dev_01_0r ( inp_wd2, inp_wd1, inp_wrd, hdr_off, |
| 475 | byt_ena, sel_awd, sel_bwd, sel_add, |
| 476 | clr, clk, |
| 477 | sum_wrd); |
| 478 | input [15:0] inp_wd2; |
| 479 | input [15:0] inp_wd1; |
| 480 | input [15:0] inp_wrd; |
| 481 | input [3:0] hdr_off; |
| 482 | input [1:0] byt_ena; |
| 483 | input [1:0] sel_awd; |
| 484 | input sel_bwd; |
| 485 | input sel_add; |
| 486 | input clr; |
| 487 | input clk; |
| 488 | output [15:0] sum_wrd; |
| 489 | |
| 490 | reg [15:0] sum_wrd; |
| 491 | |
| 492 | wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]}; |
| 493 | reg [15:0] out2; |
| 494 | reg [15:0] out1b; |
| 495 | wire [16:0] out3a; |
| 496 | wire [15:0] out3b; |
| 497 | wire [15:0] out4; |
| 498 | wire [15:0] out5; |
| 499 | |
| 500 | always @(sel_awd or |
| 501 | out1 or inp_wd1 or inp_wd2) |
| 502 | case (sel_awd) // synopsys parallel_case |
| 503 | (2'h0): out2 = out1[15:0]; |
| 504 | (2'h1): out2 = inp_wd1[15:0]; |
| 505 | (2'h2): out2 = inp_wd2[15:0]; |
| 506 | (2'h3): out2 = inp_wd2[15:0]; |
| 507 | default: out2 = out1[15:0]; |
| 508 | endcase |
| 509 | |
| 510 | always @(sel_bwd or hdr_off or |
| 511 | sum_wrd) |
| 512 | case (sel_bwd) // synopsys parallel_case |
| 513 | (1'h0): out1b = sum_wrd[15:0]; |
| 514 | (1'h1): out1b = {10'h3ff,hdr_off[3:0],2'h0}; |
| 515 | default: out1b = sum_wrd[15:0]; |
| 516 | endcase |
| 517 | |
| 518 | ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3a[16:0])); |
| 519 | ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3b[15:0])); |
| 520 | |
| 521 | assign out4 = out3a[16] && !sel_bwd ? out3b[15:0] : out3a[15:0]; |
| 522 | assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0]; |
| 523 | |
| 524 | always @(posedge clk) begin |
| 525 | sum_wrd <= #1 ({16{!clr}} & out5[15:0]); |
| 526 | end |
| 527 | |
| 528 | endmodule |
| 529 | |
| 530 | |
| 531 | module ipp_sum_dev_01_0s ( inp_wd1, inp_wrd, |
| 532 | byt_ena, sel_awd, sel_asw, sel_add, |
| 533 | clr, clk, |
| 534 | sum_wrd); |
| 535 | input [15:0] inp_wd1; |
| 536 | input [15:0] inp_wrd; |
| 537 | input [1:0] byt_ena; |
| 538 | input sel_awd; |
| 539 | input sel_asw; |
| 540 | input sel_add; |
| 541 | input clr; |
| 542 | input clk; |
| 543 | output [15:0] sum_wrd; |
| 544 | |
| 545 | reg [15:0] sum_wrd; |
| 546 | |
| 547 | wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]}; |
| 548 | wire [15:0] out1a= sel_asw ? {out1[7:0],out1[15:8]} : out1[15:0]; |
| 549 | reg [15:0] out2; |
| 550 | wire [16:0] out3a; |
| 551 | wire [15:0] out3b; |
| 552 | wire [15:0] out4; |
| 553 | wire [15:0] out5; |
| 554 | |
| 555 | always @(sel_awd or |
| 556 | out1a or inp_wd1) |
| 557 | case (sel_awd) // synopsys parallel_case |
| 558 | (1'h0): out2 = out1a[15:0]; |
| 559 | (1'h1): out2 = inp_wd1[15:0]; |
| 560 | default: out2 = out1a[15:0]; |
| 561 | endcase |
| 562 | |
| 563 | ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3a[16:0])); |
| 564 | ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3b[15:0])); |
| 565 | |
| 566 | assign out4 = out3a[16] ? out3b[15:0] : out3a[15:0]; |
| 567 | assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0]; |
| 568 | |
| 569 | always @(posedge clk) begin |
| 570 | sum_wrd <= #1 ({16{!clr}} & out5[15:0]); |
| 571 | end |
| 572 | |
| 573 | endmodule |
| 574 | |
| 575 | |
| 576 | module ipp_sum_dev_01_0t ( inp_wrd, hdr_off, |
| 577 | byt_ena, sel_asw, sel_bwd, sel_add, |
| 578 | clr, clk, |
| 579 | sum_wrd); |
| 580 | input [15:0] inp_wrd; |
| 581 | input [3:0] hdr_off; |
| 582 | input [1:0] byt_ena; |
| 583 | input sel_asw; |
| 584 | input sel_bwd; |
| 585 | input sel_add; |
| 586 | input clr; |
| 587 | input clk; |
| 588 | output [15:0] sum_wrd; |
| 589 | |
| 590 | reg [15:0] sum_wrd; |
| 591 | |
| 592 | wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]}; |
| 593 | wire [15:0] out2 = sel_asw ? {out1[7:0],out1[15:8]} : out1[15:0]; |
| 594 | reg [15:0] out1b; |
| 595 | wire [16:0] out3a; |
| 596 | wire [15:0] out3b; |
| 597 | wire [15:0] out4; |
| 598 | wire [15:0] out5; |
| 599 | |
| 600 | always @(sel_bwd or hdr_off or |
| 601 | sum_wrd) |
| 602 | case (sel_bwd) // synopsys parallel_case |
| 603 | (1'h0): out1b = sum_wrd[15:0]; |
| 604 | (1'h1): out1b = {10'h3ff,hdr_off[3:0],2'h0}; |
| 605 | default: out1b = sum_wrd[15:0]; |
| 606 | endcase |
| 607 | |
| 608 | ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3a[16:0])); |
| 609 | ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3b[15:0])); |
| 610 | |
| 611 | assign out4 = out3a[16] && !sel_bwd ? out3b[15:0] : out3a[15:0]; |
| 612 | assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0]; |
| 613 | |
| 614 | always @(posedge clk) begin |
| 615 | sum_wrd <= #1 ({16{!clr}} & out5[15:0]); |
| 616 | end |
| 617 | |
| 618 | endmodule |
| 619 | |
| 620 | |
| 621 | module ipp_sum_dev_01_ut (inp_uln, inp_wrd, hdr_off, |
| 622 | byt_ena, sel_asw, sel_bwd, sel_add, get_uln, |
| 623 | clr, clk, |
| 624 | sum_wrd); |
| 625 | input [15:0] inp_uln; |
| 626 | input [15:0] inp_wrd; |
| 627 | input [3:0] hdr_off; |
| 628 | input [1:0] byt_ena; |
| 629 | input sel_asw; |
| 630 | input sel_bwd; |
| 631 | input sel_add; |
| 632 | input get_uln; |
| 633 | input clr; |
| 634 | input clk; |
| 635 | output [15:0] sum_wrd; |
| 636 | |
| 637 | reg [15:0] sum_wrd; |
| 638 | |
| 639 | wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]}; |
| 640 | wire [15:0] out2 = sel_asw ? {out1[7:0],out1[15:8]} : out1[15:0]; |
| 641 | reg [15:0] out2a; |
| 642 | reg [15:0] out1b; |
| 643 | wire [16:0] out3a; |
| 644 | wire [15:0] out3b; |
| 645 | wire [15:0] out4; |
| 646 | wire [15:0] out5; |
| 647 | |
| 648 | always @(get_uln or |
| 649 | out2 or inp_uln) |
| 650 | case (get_uln) // synopsys parallel_case |
| 651 | (1'h0): out2a = out2[15:0]; |
| 652 | (1'h1): out2a = inp_uln[15:0]; |
| 653 | default: out2a = out2[15:0]; |
| 654 | endcase |
| 655 | |
| 656 | always @(sel_bwd or hdr_off or get_uln or |
| 657 | sum_wrd) |
| 658 | case ({get_uln,sel_bwd}) // synopsys parallel_case |
| 659 | (2'h0): out1b = sum_wrd[15:0]; |
| 660 | (2'h1): out1b = {10'h3ff,hdr_off[3:0],2'h0}; |
| 661 | (2'h2): out1b = 16'h0; |
| 662 | (2'h3): out1b = 16'h0; |
| 663 | default: out1b = sum_wrd[15:0]; |
| 664 | endcase |
| 665 | |
| 666 | ipp_sum_dev_00_00 dev_00_00_a (.in1(out2a[15:0]), .in2(out1b[15:0]), .out(out3a[16:0])); |
| 667 | ipp_sum_dev_00_01 dev_00_01_b (.in1(out2a[15:0]), .in2(out1b[15:0]), .out(out3b[15:0])); |
| 668 | |
| 669 | assign out4 = out3a[16] && !sel_bwd ? out3b[15:0] : out3a[15:0]; |
| 670 | assign out5 = (sel_add || get_uln) ? out4[15:0] : sum_wrd[15:0]; |
| 671 | |
| 672 | always @(posedge clk) begin |
| 673 | sum_wrd <= #1 ({16{!clr}} & out5[15:0]); |
| 674 | end |
| 675 | |
| 676 | endmodule |
| 677 | |
| 678 | |