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// OpenSPARC T2 Processor File: niu_ipp_sum_lib.v
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/**********************************************************
***********************************************************
File name : niu_ipp_sum_lib.v
Parent modules : niu_ipp_sum.v
Author's name : George Chu
Description : Library cells of the ipp checksum.
************************************************************
***********************************************************/
module ipp_sum_reg_r_1 (di, rs, ck, qo);
module ipp_sum_reg_r_2 (di, rs, ck, qo);
module ipp_sum_reg_r_4 (di, rs, ck, qo);
module ipp_sum_reg_r_8 (di, rs, ck, qo);
module ipp_sum_reg_r_9_s0 (di, rs, ck, qo);
module ipp_sum_reg_r_16 (di, rs, ck, qo);
module ipp_sum_reg_r_128 (di, rs, ck, qo);
module ipp_sum_reg_w_r_1 (di, wr, rs, ck, qo);
always @(di or wr or rs or qo)
case ({rs,wr}) // synopsys parallel_case
module ipp_sum_reg_w_r_2 (di, wr, rs, ck, qo);
always @(di or wr or rs or qo)
case ({rs,wr}) // synopsys parallel_case
module ipp_sum_reg_w_r_4 (di, wr, rs, ck, qo);
always @(di or wr or rs or qo)
case ({rs,wr}) // synopsys parallel_case
module ipp_sum_reg_w_r_13 (di, wr, rs, ck, qo);
always @(di or wr or rs or qo)
case ({rs,wr}) // synopsys parallel_case
default: n_qo = qo[12:0];
module ipp_sum_reg_w_r_16 (di, wr, rs, ck, qo);
always @(di or wr or rs or qo)
case ({rs,wr}) // synopsys parallel_case
default: n_qo = qo[15:0];
module ipp_sum_reg_w_r_17 (di, wr, rs, ck, qo);
always @(di or wr or rs or qo)
case ({rs,wr}) // synopsys parallel_case
default: n_qo = qo[16:0];
module ipp_sum_reg_w_r_23 (di, wr, rs, ck, qo);
always @(di or wr or rs or qo)
case ({rs,wr}) // synopsys parallel_case
default: n_qo = qo[22:0];
module ipp_sum_cnt_i_r_8 ( incr, rs, ck, qo);
qo <= #1 (qo[7:0] + 8'h1);
module ipp_sum_dev_00_00(in1, in2, out);
assign out = {1'b0,in1[15:0]} + {1'b0,in2[15:0]};
module ipp_sum_dev_00_01(in1, in2, out);
assign out = in1[15:0] + in2[15:0] + 16'h1;
module ipp_sum_dev_01_0q (inp_wd3, inp_wd2, inp_wd1, inp_wrd,
byt_ena, sel_awd, sel_add,
wire [15:0] prt_cksum = ~sum_wrd[15:0];
wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]};
wire cksum_fail = |(~out5[15:0]);
out1 or inp_wd1 or inp_wd2 or inp_wd3)
case (sel_awd) // synopsys parallel_case
(2'h0): out2 = out1[15:0];
(2'h1): out2 = inp_wd1[15:0];
(2'h2): out2 = inp_wd2[15:0];
(2'h3): out2 = inp_wd3[15:0];
default: out2 = out1[15:0];
ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3a[16:0]));
ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3b[15:0]));
assign out4 = out3a[16] ? out3b[15:0] : out3a[15:0];
assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0];
always @(posedge clk) begin
sum_wrd <= #1 ({16{!clr}} & out5[15:0]);
module ipp_sum_dev_01_0r ( inp_wd2, inp_wd1, inp_wrd, hdr_off,
byt_ena, sel_awd, sel_bwd, sel_add,
wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]};
out1 or inp_wd1 or inp_wd2)
case (sel_awd) // synopsys parallel_case
(2'h0): out2 = out1[15:0];
(2'h1): out2 = inp_wd1[15:0];
(2'h2): out2 = inp_wd2[15:0];
(2'h3): out2 = inp_wd2[15:0];
default: out2 = out1[15:0];
always @(sel_bwd or hdr_off or
case (sel_bwd) // synopsys parallel_case
(1'h0): out1b = sum_wrd[15:0];
(1'h1): out1b = {10'h3ff,hdr_off[3:0],2'h0};
default: out1b = sum_wrd[15:0];
ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3a[16:0]));
ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3b[15:0]));
assign out4 = out3a[16] && !sel_bwd ? out3b[15:0] : out3a[15:0];
assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0];
always @(posedge clk) begin
sum_wrd <= #1 ({16{!clr}} & out5[15:0]);
module ipp_sum_dev_01_0s ( inp_wd1, inp_wrd,
byt_ena, sel_awd, sel_asw, sel_add,
wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]};
wire [15:0] out1a= sel_asw ? {out1[7:0],out1[15:8]} : out1[15:0];
case (sel_awd) // synopsys parallel_case
(1'h0): out2 = out1a[15:0];
(1'h1): out2 = inp_wd1[15:0];
default: out2 = out1a[15:0];
ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3a[16:0]));
ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(sum_wrd[15:0]), .out(out3b[15:0]));
assign out4 = out3a[16] ? out3b[15:0] : out3a[15:0];
assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0];
always @(posedge clk) begin
sum_wrd <= #1 ({16{!clr}} & out5[15:0]);
module ipp_sum_dev_01_0t ( inp_wrd, hdr_off,
byt_ena, sel_asw, sel_bwd, sel_add,
wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]};
wire [15:0] out2 = sel_asw ? {out1[7:0],out1[15:8]} : out1[15:0];
always @(sel_bwd or hdr_off or
case (sel_bwd) // synopsys parallel_case
(1'h0): out1b = sum_wrd[15:0];
(1'h1): out1b = {10'h3ff,hdr_off[3:0],2'h0};
default: out1b = sum_wrd[15:0];
ipp_sum_dev_00_00 dev_00_00_a (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3a[16:0]));
ipp_sum_dev_00_01 dev_00_01_b (.in1(out2[15:0]), .in2(out1b[15:0]), .out(out3b[15:0]));
assign out4 = out3a[16] && !sel_bwd ? out3b[15:0] : out3a[15:0];
assign out5 = sel_add ? out4[15:0] : sum_wrd[15:0];
always @(posedge clk) begin
sum_wrd <= #1 ({16{!clr}} & out5[15:0]);
module ipp_sum_dev_01_ut (inp_uln, inp_wrd, hdr_off,
byt_ena, sel_asw, sel_bwd, sel_add, get_uln,
wire [15:0] out1 = {{8{byt_ena[1]}}&inp_wrd[15:8],{8{byt_ena[0]}}&inp_wrd[7:0]};
wire [15:0] out2 = sel_asw ? {out1[7:0],out1[15:8]} : out1[15:0];
case (get_uln) // synopsys parallel_case
(1'h0): out2a = out2[15:0];
(1'h1): out2a = inp_uln[15:0];
default: out2a = out2[15:0];
always @(sel_bwd or hdr_off or get_uln or
case ({get_uln,sel_bwd}) // synopsys parallel_case
(2'h0): out1b = sum_wrd[15:0];
(2'h1): out1b = {10'h3ff,hdr_off[3:0],2'h0};
default: out1b = sum_wrd[15:0];
ipp_sum_dev_00_00 dev_00_00_a (.in1(out2a[15:0]), .in2(out1b[15:0]), .out(out3a[16:0]));
ipp_sum_dev_00_01 dev_00_01_b (.in1(out2a[15:0]), .in2(out1b[15:0]), .out(out3b[15:0]));
assign out4 = out3a[16] && !sel_bwd ? out3b[15:0] : out3a[15:0];
assign out5 = (sel_add || get_uln) ? out4[15:0] : sum_wrd[15:0];
always @(posedge clk) begin
sum_wrd <= #1 ({16{!clr}} & out5[15:0]);