| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_ram_128_42.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | |
| 36 | /********************************************************** |
| 37 | *********************************************************** |
| 38 | |
| 39 | Project : Niu |
| 40 | |
| 41 | File name : niu_ram_128_42.v |
| 42 | |
| 43 | Module(s) name : niu_ram_128_42 |
| 44 | |
| 45 | Parent modules : |
| 46 | |
| 47 | Child modules : |
| 48 | |
| 49 | Author's name : George Chu |
| 50 | |
| 51 | Date : April. 2004 |
| 52 | |
| 53 | Description : |
| 54 | |
| 55 | Synthesis Notes: |
| 56 | |
| 57 | Modification History: |
| 58 | Date Description |
| 59 | ---- ----------- |
| 60 | |
| 61 | ************************************************************ |
| 62 | ***********************************************************/ |
| 63 | |
| 64 | `timescale 1ns/10ps |
| 65 | |
| 66 | module niu_ram_128_42 ( |
| 67 | tcu_aclk, |
| 68 | tcu_bclk, |
| 69 | tcu_se_scancollar_in, |
| 70 | tcu_array_wr_inhibit, |
| 71 | scan_in, |
| 72 | scan_out, |
| 73 | mbi_wdata, |
| 74 | mbi_rd_adr, |
| 75 | mbi_wr_adr, |
| 76 | mbi_wr_en, |
| 77 | mbi_rd_en, |
| 78 | mbi_run, |
| 79 | data_inp, |
| 80 | addr_rd, |
| 81 | addr_wt, |
| 82 | wt_enable, |
| 83 | cs_rd, |
| 84 | clk, |
| 85 | data_out |
| 86 | ); |
| 87 | |
| 88 | parameter DATA_WIDTH_MINUS1 = 41; |
| 89 | parameter ADDR_WIDTH_MINUS1 = 6; |
| 90 | |
| 91 | input tcu_aclk; |
| 92 | input tcu_bclk; |
| 93 | input tcu_se_scancollar_in; |
| 94 | input tcu_array_wr_inhibit; |
| 95 | input scan_in; |
| 96 | output scan_out; |
| 97 | |
| 98 | input [DATA_WIDTH_MINUS1:0] mbi_wdata; |
| 99 | input [ADDR_WIDTH_MINUS1:0] mbi_rd_adr; |
| 100 | input [ADDR_WIDTH_MINUS1:0] mbi_wr_adr; |
| 101 | input mbi_wr_en; |
| 102 | input mbi_rd_en; |
| 103 | input mbi_run; |
| 104 | |
| 105 | input [DATA_WIDTH_MINUS1:0] data_inp; // data_input, via port_B |
| 106 | input [ADDR_WIDTH_MINUS1:0] addr_rd; // read_address, via port_A |
| 107 | input [ADDR_WIDTH_MINUS1:0] addr_wt; // write_address, via port_B |
| 108 | input wt_enable; // write_enable, via port_B |
| 109 | input cs_rd; // chip_selet_rd_port, i.e., port_A |
| 110 | input clk; |
| 111 | output [DATA_WIDTH_MINUS1:0] data_out; // data read out, via port_A |
| 112 | |
| 113 | wire [DATA_WIDTH_MINUS1:0] data_out; |
| 114 | wire scan_out; |
| 115 | |
| 116 | wire [ADDR_WIDTH_MINUS1:0] mux_wr_adr; |
| 117 | wire mux_wr_en; |
| 118 | wire [ADDR_WIDTH_MINUS1:0] mux_rd_adr; |
| 119 | wire mux_rd_en; |
| 120 | wire [DATA_WIDTH_MINUS1:0] mux_wdata; |
| 121 | |
| 122 | assign mux_wdata = mbi_run ? mbi_wdata : data_inp; |
| 123 | assign mux_rd_adr = mbi_run ? mbi_rd_adr : addr_rd; |
| 124 | assign mux_wr_adr = mbi_run ? mbi_wr_adr : addr_wt; |
| 125 | assign mux_wr_en = mbi_run ? mbi_wr_en : wt_enable; |
| 126 | assign mux_rd_en = mbi_run ? mbi_rd_en : cs_rd; |
| 127 | |
| 128 | n2_com_dp_128x42s_cust ram_128_42_0 ( |
| 129 | .tcu_pce_ov (1'h1), |
| 130 | .tcu_aclk (tcu_aclk), |
| 131 | .tcu_bclk (tcu_bclk), |
| 132 | .tcu_se_scancollar_in (tcu_se_scancollar_in), |
| 133 | .rd_pce (1'h1), |
| 134 | .wr_pce (1'h1), |
| 135 | .bist_clk_mux_sel (1'h0), |
| 136 | .tcu_array_wr_inhibit (tcu_array_wr_inhibit), |
| 137 | .scan_in (scan_in), |
| 138 | .scan_out (scan_out), |
| 139 | .wr_adr (mux_wr_adr[6:0]), |
| 140 | .wr_en (mux_wr_en), |
| 141 | .rd_adr (mux_rd_adr[6:0]), |
| 142 | .rd_en (mux_rd_en), |
| 143 | .din (mux_wdata[41:0]), |
| 144 | .dout (data_out[41:0]), |
| 145 | .rdclk (clk), |
| 146 | .wrclk (clk) |
| 147 | ); |
| 148 | |
| 149 | endmodule |