| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: ifu_ftu_itc_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module ifu_ftu_itc_ctl ( |
| 36 | tcu_scan_en, |
| 37 | l2clk, |
| 38 | scan_in, |
| 39 | tcu_pce_ov, |
| 40 | spc_aclk, |
| 41 | spc_bclk, |
| 42 | tlu_itlb_reload, |
| 43 | tlu_trap_pc_0, |
| 44 | tlu_trap_pc_1, |
| 45 | itd_index_valid_in, |
| 46 | ftp_itt_rd_req_bf, |
| 47 | ftp_itd_rd_req_bf, |
| 48 | mbi_wdata_6, |
| 49 | mbi_wdata_0, |
| 50 | tlu_trap_pc_0_45_43, |
| 51 | tlu_trap_pc_1_45_43, |
| 52 | lsu_asi_error_inject_b31, |
| 53 | lsu_asi_error_inject_b29, |
| 54 | lsu_asi_error_inject_b28, |
| 55 | tlu_itlb_bypass, |
| 56 | lsu_immu_enable, |
| 57 | ftp_itb_fetch_thr_bf, |
| 58 | asi_real_bf, |
| 59 | ftp_ith_det_req_bf, |
| 60 | mbi_run, |
| 61 | lbist_run, |
| 62 | mbi_cambist_run, |
| 63 | mbi_itb_demap_en, |
| 64 | mbi_demap_type, |
| 65 | mbi_dis_clr_ubit, |
| 66 | mbi_repl_write, |
| 67 | mbi_itb_cam_en_pre, |
| 68 | mbi_itb_write_en, |
| 69 | mbi_itb_read_en, |
| 70 | itb_tte_data_v_27_22, |
| 71 | itb_tte_data_v_21_16, |
| 72 | scan_out, |
| 73 | itc_wr_u_en, |
| 74 | itc_rw_index_vld, |
| 75 | itc_demap, |
| 76 | itc_demap_context, |
| 77 | itc_demap_all, |
| 78 | itc_demap_real, |
| 79 | itc_tte_ubit, |
| 80 | itc_sel_trap_pc_0, |
| 81 | itc_sel_trap_pc_1, |
| 82 | itc_sel_demap_tag_d, |
| 83 | itc_sel_demap_tag_c0, |
| 84 | itc_sel_demap_tag_c1, |
| 85 | itc_sel_write_tag, |
| 86 | itc_sel_write_tag_indexed, |
| 87 | itc_sel_default, |
| 88 | itc_itlb_rd_vld_bf, |
| 89 | itc_bypass_bf, |
| 90 | itc_ra_to_pa_bf, |
| 91 | itc_tag_error_inj, |
| 92 | itc_data_error_inj, |
| 93 | itc_dis_clr_ubit, |
| 94 | itc_write_next, |
| 95 | itc_demap_next, |
| 96 | itc_sel_mbist, |
| 97 | itc_mbi_itb_read_en, |
| 98 | itc_thr_to_write, |
| 99 | itc_itb_data_sz_1); |
| 100 | wire pce_ov; |
| 101 | wire stop; |
| 102 | wire siclk; |
| 103 | wire soclk; |
| 104 | wire l1clk; |
| 105 | wire lsu_err_inj_sig_reg_scanin; |
| 106 | wire lsu_err_inj_sig_reg_scanout; |
| 107 | wire asi_error_inject_b31_ff; |
| 108 | wire asi_error_inject_b29_ff; |
| 109 | wire asi_error_inject_b28_ff; |
| 110 | wire tag_error_inj; |
| 111 | wire wr_vld_in; |
| 112 | wire data_error_inj; |
| 113 | wire error_inj_latch_scanin; |
| 114 | wire error_inj_latch_scanout; |
| 115 | wire [1:0] reload; |
| 116 | wire demap_next_in; |
| 117 | wire reload0_latch_scanin; |
| 118 | wire reload0_latch_scanout; |
| 119 | wire reload0; |
| 120 | wire [37:35] tlu_tte; |
| 121 | wire [2:0] tlu_tte_45_43; |
| 122 | wire tte0_lat_scanin; |
| 123 | wire tte0_lat_scanout; |
| 124 | wire [37:35] tte0; |
| 125 | wire [7:0] tte0_tid_dec; |
| 126 | wire tte1_lat_scanin; |
| 127 | wire tte1_lat_scanout; |
| 128 | wire [7:0] tte1_tid_dec; |
| 129 | wire [7:0] thr_to_write_in; |
| 130 | wire demap_c0_reg_scanin; |
| 131 | wire demap_c0_reg_scanout; |
| 132 | wire [2:0] demap_c0; |
| 133 | wire demap_c1_reg_scanin; |
| 134 | wire demap_c1_reg_scanout; |
| 135 | wire [2:0] demap_c1; |
| 136 | wire reload1_latch_scanin; |
| 137 | wire reload1_latch_scanout; |
| 138 | wire reload1; |
| 139 | wire wr_vld_latch_scanin; |
| 140 | wire wr_vld_latch_scanout; |
| 141 | wire itc_cam_vld_1; |
| 142 | wire wr_vld; |
| 143 | wire mbist_dis_clr_ubit_ff; |
| 144 | wire itc_repl_wrire; |
| 145 | wire itc_cam_vld_2; |
| 146 | wire itc_cam_vld_2_unused; |
| 147 | wire bist_run_reg_scanin; |
| 148 | wire bist_run_reg_scanout; |
| 149 | wire itc_mbist_run; |
| 150 | wire itc_cambist_run; |
| 151 | wire itc_itb_demap_en; |
| 152 | wire [1:0] itc_demap_type; |
| 153 | wire itc_mbi_itb_write_en; |
| 154 | wire itc_mbi_wdata_6; |
| 155 | wire itc_mbi_wdata_0; |
| 156 | wire itc_tte_ubit_old; |
| 157 | wire demap_page; |
| 158 | wire demap_context; |
| 159 | wire demap_all; |
| 160 | wire demap_real; |
| 161 | wire itc_sel_demap_tag_d_in; |
| 162 | wire itc_sel_demap_tag_c0_in; |
| 163 | wire itc_sel_demap_tag_c1_in; |
| 164 | wire itc_sel_demap_reg_scanin; |
| 165 | wire itc_sel_demap_reg_scanout; |
| 166 | wire itc_sel_write_tag_in; |
| 167 | wire itc_sel_write_tag_indexed_in; |
| 168 | wire itc_sel_default_in; |
| 169 | wire index_valid; |
| 170 | wire itc_demap_page; |
| 171 | wire itc_demap_page_unused; |
| 172 | wire itlb_bypass_lat_scanin; |
| 173 | wire itlb_bypass_lat_scanout; |
| 174 | wire [7:0] itlb_bypass; |
| 175 | wire immu_enable_lat_scanin; |
| 176 | wire immu_enable_lat_scanout; |
| 177 | wire [7:0] immu_enable; |
| 178 | wire [7:0] pre_bypass_bf; |
| 179 | wire [7:0] pre_ra_to_pa; |
| 180 | wire spares_scanin; |
| 181 | wire spares_scanout; |
| 182 | wire se; |
| 183 | |
| 184 | |
| 185 | |
| 186 | |
| 187 | input tcu_scan_en; |
| 188 | input l2clk; |
| 189 | input scan_in; |
| 190 | input tcu_pce_ov; |
| 191 | input spc_aclk; |
| 192 | input spc_bclk; |
| 193 | // The following signals indicate the |
| 194 | // first cycle of TTE transfer as well |
| 195 | // as the operation (write or demap) |
| 196 | input [1:0] tlu_itlb_reload; |
| 197 | input [37:35] tlu_trap_pc_0; // |
| 198 | input [37:35] tlu_trap_pc_1; // |
| 199 | input itd_index_valid_in; // Write with index |
| 200 | |
| 201 | input ftp_itt_rd_req_bf; |
| 202 | input ftp_itd_rd_req_bf; |
| 203 | input mbi_wdata_6; |
| 204 | input mbi_wdata_0; |
| 205 | input [2:0] tlu_trap_pc_0_45_43; |
| 206 | input [2:0] tlu_trap_pc_1_45_43; |
| 207 | |
| 208 | input lsu_asi_error_inject_b31; |
| 209 | input lsu_asi_error_inject_b29; |
| 210 | input lsu_asi_error_inject_b28; |
| 211 | |
| 212 | input [7:0] tlu_itlb_bypass; |
| 213 | input [7:0] lsu_immu_enable; |
| 214 | input [7:0] ftp_itb_fetch_thr_bf; |
| 215 | input asi_real_bf; |
| 216 | input ftp_ith_det_req_bf; |
| 217 | |
| 218 | input mbi_run; |
| 219 | input lbist_run; |
| 220 | input mbi_cambist_run ; |
| 221 | input mbi_itb_demap_en ; |
| 222 | input [1:0] mbi_demap_type ; |
| 223 | input mbi_dis_clr_ubit ; |
| 224 | input mbi_repl_write ; |
| 225 | input mbi_itb_cam_en_pre ; |
| 226 | |
| 227 | input mbi_itb_write_en; |
| 228 | input mbi_itb_read_en; |
| 229 | input itb_tte_data_v_27_22 ; |
| 230 | input itb_tte_data_v_21_16 ; |
| 231 | |
| 232 | output scan_out; |
| 233 | output itc_wr_u_en; // Write enable |
| 234 | output itc_rw_index_vld; // Use index for read or write |
| 235 | output itc_demap; // Any demap |
| 236 | output itc_demap_context; // Demap context |
| 237 | output itc_demap_all; // Demap all |
| 238 | output itc_demap_real; // Demap real |
| 239 | output itc_tte_ubit ; // tte_ubit |
| 240 | |
| 241 | output itc_sel_trap_pc_0; // Datapath controls |
| 242 | output itc_sel_trap_pc_1; |
| 243 | output itc_sel_demap_tag_d; |
| 244 | output itc_sel_demap_tag_c0; |
| 245 | output itc_sel_demap_tag_c1; |
| 246 | output itc_sel_write_tag; |
| 247 | output itc_sel_write_tag_indexed; |
| 248 | output itc_sel_default; |
| 249 | |
| 250 | output itc_itlb_rd_vld_bf ; |
| 251 | output itc_bypass_bf; |
| 252 | |
| 253 | output itc_ra_to_pa_bf; |
| 254 | output itc_tag_error_inj; |
| 255 | output itc_data_error_inj; |
| 256 | |
| 257 | output itc_dis_clr_ubit ; |
| 258 | |
| 259 | output itc_write_next; |
| 260 | output itc_demap_next; |
| 261 | output itc_sel_mbist; |
| 262 | output itc_mbi_itb_read_en; |
| 263 | output [7:0] itc_thr_to_write; |
| 264 | output itc_itb_data_sz_1; |
| 265 | |
| 266 | |
| 267 | ////////////////////////////////////////////////////////////////////////////// |
| 268 | |
| 269 | assign pce_ov = tcu_pce_ov; |
| 270 | assign stop = 1'b0; |
| 271 | assign siclk = spc_aclk; |
| 272 | assign soclk = spc_bclk; |
| 273 | |
| 274 | // Clock header |
| 275 | ifu_ftu_itc_ctl_l1clkhdr_ctl_macro clkgen ( |
| 276 | .l2clk (l2clk ), |
| 277 | .l1en (1'b1 ), |
| 278 | .l1clk (l1clk ), |
| 279 | .pce_ov(pce_ov), |
| 280 | .stop(stop), |
| 281 | .se(se) |
| 282 | ); |
| 283 | |
| 284 | |
| 285 | |
| 286 | |
| 287 | |
| 288 | //////////////////////////////////////////////////////////////////////////////// |
| 289 | // |
| 290 | // |
| 291 | // |
| 292 | |
| 293 | |
| 294 | ifu_ftu_itc_ctl_msff_ctl_macro__width_3 lsu_err_inj_sig_reg ( |
| 295 | .scan_in(lsu_err_inj_sig_reg_scanin), |
| 296 | .scan_out(lsu_err_inj_sig_reg_scanout), |
| 297 | .din ({lsu_asi_error_inject_b31, |
| 298 | lsu_asi_error_inject_b29, |
| 299 | lsu_asi_error_inject_b28} ), |
| 300 | .dout ({asi_error_inject_b31_ff, |
| 301 | asi_error_inject_b29_ff, |
| 302 | asi_error_inject_b28_ff} ), |
| 303 | .l1clk(l1clk), |
| 304 | .siclk(siclk), |
| 305 | .soclk(soclk) |
| 306 | ); |
| 307 | |
| 308 | assign tag_error_inj = asi_error_inject_b31_ff & asi_error_inject_b28_ff & wr_vld_in; |
| 309 | assign data_error_inj = asi_error_inject_b31_ff & asi_error_inject_b29_ff & wr_vld_in; |
| 310 | |
| 311 | ifu_ftu_itc_ctl_msff_ctl_macro__width_2 error_inj_latch ( |
| 312 | .scan_in(error_inj_latch_scanin), |
| 313 | .scan_out(error_inj_latch_scanout), |
| 314 | .din ({ tag_error_inj, data_error_inj }), |
| 315 | .dout ({itc_tag_error_inj,itc_data_error_inj }), |
| 316 | .l1clk(l1clk), |
| 317 | .siclk(siclk), |
| 318 | .soclk(soclk) |
| 319 | ); |
| 320 | |
| 321 | //flop tlb_reload |
| 322 | |
| 323 | assign itc_sel_trap_pc_0 = |
| 324 | tlu_itlb_reload[0] | reload[0]; |
| 325 | |
| 326 | assign itc_sel_trap_pc_1 = |
| 327 | tlu_itlb_reload[1] | reload[1]; |
| 328 | |
| 329 | assign demap_next_in = (| tlu_itlb_reload[1:0] ); |
| 330 | ifu_ftu_itc_ctl_msff_ctl_macro__width_3 reload0_latch ( |
| 331 | .scan_in(reload0_latch_scanin), |
| 332 | .scan_out(reload0_latch_scanout), |
| 333 | .din ({tlu_itlb_reload[1:0], demap_next_in} ), |
| 334 | .dout ({reload[1:0],itc_demap_next} ), |
| 335 | .l1clk(l1clk), |
| 336 | .siclk(siclk), |
| 337 | .soclk(soclk) |
| 338 | ); |
| 339 | |
| 340 | assign reload0 = |
| 341 | (| reload[1:0]); |
| 342 | |
| 343 | |
| 344 | //////////////////////////////////////////////////// |
| 345 | // TID logic // |
| 346 | // Add logic here for timing reasons. // |
| 347 | //////////////////////////////////////////////////// |
| 348 | |
| 349 | assign tlu_tte[37:35] = itc_sel_trap_pc_0 ? tlu_trap_pc_0[37:35] : tlu_trap_pc_1[37:35] ; |
| 350 | assign tlu_tte_45_43[2:0] = itc_sel_trap_pc_0 ? tlu_trap_pc_0_45_43[2:0] : tlu_trap_pc_1_45_43[2:0] ; |
| 351 | |
| 352 | |
| 353 | |
| 354 | ifu_ftu_itc_ctl_msff_ctl_macro__width_3 tte0_lat ( |
| 355 | .scan_in(tte0_lat_scanin), |
| 356 | .scan_out(tte0_lat_scanout), |
| 357 | .din (tlu_tte [37:35] ), |
| 358 | .dout (tte0 [37:35] ), |
| 359 | .l1clk(l1clk), |
| 360 | .siclk(siclk), |
| 361 | .soclk(soclk) |
| 362 | ); |
| 363 | |
| 364 | assign tte0_tid_dec[0] = ~tte0[37] & ~tte0[36] & ~tte0[35] ; |
| 365 | assign tte0_tid_dec[1] = ~tte0[37] & ~tte0[36] & tte0[35] ; |
| 366 | assign tte0_tid_dec[2] = ~tte0[37] & tte0[36] & ~tte0[35] ; |
| 367 | assign tte0_tid_dec[3] = ~tte0[37] & tte0[36] & tte0[35] ; |
| 368 | assign tte0_tid_dec[4] = tte0[37] & ~tte0[36] & ~tte0[35] ; |
| 369 | assign tte0_tid_dec[5] = tte0[37] & ~tte0[36] & tte0[35] ; |
| 370 | assign tte0_tid_dec[6] = tte0[37] & tte0[36] & ~tte0[35] ; |
| 371 | assign tte0_tid_dec[7] = tte0[37] & tte0[36] & tte0[35] ; |
| 372 | |
| 373 | ifu_ftu_itc_ctl_msff_ctl_macro__width_8 tte1_lat ( |
| 374 | .scan_in(tte1_lat_scanin), |
| 375 | .scan_out(tte1_lat_scanout), |
| 376 | .din (tte0_tid_dec[7:0]), |
| 377 | .dout (tte1_tid_dec[7:0]), |
| 378 | .l1clk(l1clk), |
| 379 | .siclk(siclk), |
| 380 | .soclk(soclk) |
| 381 | ); |
| 382 | |
| 383 | assign itc_thr_to_write[7:0] = thr_to_write_in[7:0] ; |
| 384 | |
| 385 | |
| 386 | |
| 387 | assign thr_to_write_in[7:0] = ({8{ reload0}} & tte0_tid_dec[7:0]) | |
| 388 | ({8{~reload0}} & tte1_tid_dec[7:0]) ; |
| 389 | |
| 390 | |
| 391 | //////////////////////////////////////////////////// |
| 392 | //////////////////////////////////////////////////// |
| 393 | //////////////////////////////////////////////////// |
| 394 | //////////////////////////////////////////////////// |
| 395 | |
| 396 | |
| 397 | |
| 398 | ifu_ftu_itc_ctl_msff_ctl_macro__width_3 demap_c0_reg ( |
| 399 | .scan_in(demap_c0_reg_scanin), |
| 400 | .scan_out(demap_c0_reg_scanout), |
| 401 | .din (tlu_tte_45_43[2:0] ), |
| 402 | .dout (demap_c0[2:0] ), |
| 403 | .l1clk(l1clk), |
| 404 | .siclk(siclk), |
| 405 | .soclk(soclk) |
| 406 | ); |
| 407 | |
| 408 | ifu_ftu_itc_ctl_msff_ctl_macro__width_3 demap_c1_reg ( |
| 409 | .scan_in(demap_c1_reg_scanin), |
| 410 | .scan_out(demap_c1_reg_scanout), |
| 411 | .din (demap_c0[2:0] ), |
| 412 | .dout (demap_c1[2:0] ), |
| 413 | .l1clk(l1clk), |
| 414 | .siclk(siclk), |
| 415 | .soclk(soclk) |
| 416 | ); |
| 417 | |
| 418 | ifu_ftu_itc_ctl_msff_ctl_macro__width_1 reload1_latch ( |
| 419 | .scan_in(reload1_latch_scanin), |
| 420 | .scan_out(reload1_latch_scanout), |
| 421 | .din (reload0 ), |
| 422 | .dout (reload1 ), |
| 423 | .l1clk(l1clk), |
| 424 | .siclk(siclk), |
| 425 | .soclk(soclk) |
| 426 | ); |
| 427 | |
| 428 | |
| 429 | // demap_control[2]: 1 means demap, 0 means write |
| 430 | // demap_control[1:0] (if demap_control[2] is 1) |
| 431 | // 00 Demap page |
| 432 | // 01 Demap context |
| 433 | // 10 Demap all |
| 434 | // 11 Demap real |
| 435 | // demap_control[1:0] (if demap_control[2] is 0) |
| 436 | // 00 Demap and write with supplied context |
| 437 | // 01 Demap and write with context_0 |
| 438 | // 10 Demap and write with context_1 |
| 439 | // 11 Illegal (but demap and write with context_0) |
| 440 | |
| 441 | assign wr_vld_in = |
| 442 | reload1 & ~demap_c1[2]; |
| 443 | |
| 444 | ifu_ftu_itc_ctl_msff_ctl_macro__width_5 wr_vld_latch ( |
| 445 | .scan_in(wr_vld_latch_scanin), |
| 446 | .scan_out(wr_vld_latch_scanout), |
| 447 | .din ({wr_vld_in, mbi_dis_clr_ubit , mbi_repl_write, mbi_itb_cam_en_pre, itc_cam_vld_1} ), |
| 448 | .dout ({wr_vld , mbist_dis_clr_ubit_ff, itc_repl_wrire ,itc_cam_vld_1, itc_cam_vld_2} ), |
| 449 | .l1clk(l1clk), |
| 450 | .siclk(siclk), |
| 451 | .soclk(soclk)); |
| 452 | |
| 453 | assign itc_cam_vld_2_unused = itc_cam_vld_2 ; |
| 454 | |
| 455 | ifu_ftu_itc_ctl_msff_ctl_macro__width_9 bist_run_reg ( |
| 456 | .scan_in(bist_run_reg_scanin), |
| 457 | .scan_out(bist_run_reg_scanout), |
| 458 | .din ({mbi_run,mbi_cambist_run, mbi_itb_demap_en,mbi_demap_type[1:0], |
| 459 | mbi_itb_read_en,mbi_itb_write_en,mbi_wdata_6,mbi_wdata_0}), |
| 460 | .dout ({itc_mbist_run,itc_cambist_run,itc_itb_demap_en,itc_demap_type[1:0], |
| 461 | itc_mbi_itb_read_en,itc_mbi_itb_write_en,itc_mbi_wdata_6,itc_mbi_wdata_0} ), |
| 462 | .l1clk(l1clk), |
| 463 | .siclk(siclk), |
| 464 | .soclk(soclk)); |
| 465 | |
| 466 | assign itc_tte_ubit_old = (itc_mbist_run & ~itc_cambist_run) ? itc_mbi_wdata_0 : itc_mbi_wdata_6 ; |
| 467 | assign itc_tte_ubit = itc_tte_ubit_old | (~itc_cambist_run & ~itc_mbist_run) ; |
| 468 | |
| 469 | assign demap_page = |
| 470 | (reload1 & demap_c1[2] & ~demap_c1[1] & ~demap_c1[0]) | |
| 471 | (reload1 & ~demap_c1[2]); |
| 472 | |
| 473 | assign demap_context = |
| 474 | reload1 & demap_c1[2] & ~demap_c1[1] & demap_c1[0]; |
| 475 | |
| 476 | assign demap_all = |
| 477 | reload1 & demap_c1[2] & demap_c1[1] & ~demap_c1[0]; |
| 478 | |
| 479 | assign demap_real = |
| 480 | reload1 & demap_c1[2] & demap_c1[1] & demap_c1[0]; |
| 481 | |
| 482 | assign itc_sel_demap_tag_d_in = (reload0 & demap_c0[2] & ~mbi_run) | |
| 483 | (reload0 & ~demap_c0[2] & ~demap_c0[1] & ~mbi_run) ; |
| 484 | |
| 485 | assign itc_sel_demap_tag_c0_in = (reload0 & ~demap_c0[2] & demap_c0[0] & ~mbi_run) ; |
| 486 | |
| 487 | assign itc_sel_demap_tag_c1_in = |
| 488 | (reload0 & ~demap_c0[2] & demap_c0[1] & ~demap_c0[0] & ~mbi_run) ; |
| 489 | |
| 490 | ifu_ftu_itc_ctl_msff_ctl_macro__width_7 itc_sel_demap_reg ( |
| 491 | .scan_in(itc_sel_demap_reg_scanin), |
| 492 | .scan_out(itc_sel_demap_reg_scanout), |
| 493 | .din ({itc_sel_demap_tag_d_in, |
| 494 | itc_sel_demap_tag_c0_in, |
| 495 | itc_sel_demap_tag_c1_in, |
| 496 | itc_sel_write_tag_in, |
| 497 | itc_sel_write_tag_indexed_in, |
| 498 | itc_sel_default_in, |
| 499 | itd_index_valid_in} ), |
| 500 | .dout ({itc_sel_demap_tag_d, |
| 501 | itc_sel_demap_tag_c0, |
| 502 | itc_sel_demap_tag_c1, |
| 503 | itc_sel_write_tag, |
| 504 | itc_sel_write_tag_indexed, |
| 505 | itc_sel_default, |
| 506 | index_valid} ), |
| 507 | .l1clk(l1clk), |
| 508 | .siclk(siclk), |
| 509 | .soclk(soclk) |
| 510 | ); |
| 511 | |
| 512 | assign itc_sel_write_tag_in = wr_vld_in & ~itd_index_valid_in & ~mbi_run; |
| 513 | |
| 514 | assign itc_sel_write_tag_indexed_in = wr_vld_in & itd_index_valid_in & ~mbi_run; |
| 515 | |
| 516 | assign itc_sel_mbist = itc_mbist_run ; |
| 517 | assign itc_sel_default_in = ~reload0 & ~wr_vld_in & ~mbi_run; |
| 518 | |
| 519 | assign itc_write_next = wr_vld_in ; |
| 520 | |
| 521 | |
| 522 | |
| 523 | ///outputs |
| 524 | |
| 525 | assign itc_demap = (itc_mbist_run & itc_cambist_run) ? itc_itb_demap_en : (!itc_mbist_run & reload1); |
| 526 | assign itc_demap_page = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b00)) : |
| 527 | (!itc_mbist_run & demap_page); |
| 528 | assign itc_demap_context = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b10)) : |
| 529 | (!itc_mbist_run & demap_context); |
| 530 | assign itc_demap_all = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b11)) : |
| 531 | (!itc_mbist_run & demap_all); |
| 532 | assign itc_demap_real = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b01)) : |
| 533 | (!itc_mbist_run & demap_real); |
| 534 | |
| 535 | |
| 536 | assign itc_wr_u_en = (wr_vld & ~itc_mbist_run) | |
| 537 | (itc_mbi_itb_write_en & itc_mbist_run); |
| 538 | |
| 539 | assign itc_rw_index_vld = (wr_vld & index_valid & ~itc_mbist_run) | |
| 540 | (ftp_itt_rd_req_bf & ~itc_mbist_run) | |
| 541 | (ftp_itd_rd_req_bf & ~itc_mbist_run) | |
| 542 | (itc_mbist_run & ~itc_repl_wrire) | |
| 543 | lbist_run ; |
| 544 | |
| 545 | assign itc_demap_page_unused = itc_demap_page ; |
| 546 | |
| 547 | |
| 548 | ////////////////////////////////////////////////////////////////////// |
| 549 | // ITLB bypass control |
| 550 | |
| 551 | ifu_ftu_itc_ctl_msff_ctl_macro__width_8 itlb_bypass_lat ( |
| 552 | .scan_in(itlb_bypass_lat_scanin), |
| 553 | .scan_out(itlb_bypass_lat_scanout), |
| 554 | .din (tlu_itlb_bypass [7:0] ), |
| 555 | .dout (itlb_bypass [7:0] ), |
| 556 | .l1clk(l1clk), |
| 557 | .siclk(siclk), |
| 558 | .soclk(soclk) |
| 559 | ); |
| 560 | |
| 561 | ifu_ftu_itc_ctl_msff_ctl_macro__width_8 immu_enable_lat ( |
| 562 | .scan_in(immu_enable_lat_scanin), |
| 563 | .scan_out(immu_enable_lat_scanout), |
| 564 | .din (lsu_immu_enable [7:0] ), |
| 565 | .dout (immu_enable [7:0] ), |
| 566 | .l1clk(l1clk), |
| 567 | .siclk(siclk), |
| 568 | .soclk(soclk) |
| 569 | ); |
| 570 | |
| 571 | |
| 572 | assign pre_bypass_bf[7:0] = ftp_ith_det_req_bf ? 8'h00 : |
| 573 | itlb_bypass[7:0]; |
| 574 | |
| 575 | assign pre_ra_to_pa[7:0] = ftp_ith_det_req_bf ? {8{asi_real_bf}} : |
| 576 | ~itlb_bypass[7:0] &~immu_enable[7:0]; |
| 577 | |
| 578 | assign itc_ra_to_pa_bf = |
| 579 | (| (ftp_itb_fetch_thr_bf[7:0] & pre_ra_to_pa[7:0])); |
| 580 | |
| 581 | assign itc_bypass_bf = |
| 582 | (| (ftp_itb_fetch_thr_bf[7:0] & pre_bypass_bf[7:0])) & ~itc_mbist_run; |
| 583 | |
| 584 | |
| 585 | assign itc_itlb_rd_vld_bf = (ftp_itt_rd_req_bf & ~itc_mbist_run) | |
| 586 | (ftp_itd_rd_req_bf & ~itc_mbist_run) | |
| 587 | (itc_mbi_itb_read_en & itc_mbist_run) ; |
| 588 | |
| 589 | assign itc_itb_data_sz_1 = ~itb_tte_data_v_27_22 & itb_tte_data_v_21_16 ; |
| 590 | |
| 591 | |
| 592 | /////////////////////////////////////////////////////////////////////// |
| 593 | // Spare circuits // |
| 594 | /////////////////////////////////////////////////////////////////////// |
| 595 | ifu_ftu_itc_ctl_spare_ctl_macro__num_1 spares ( |
| 596 | .scan_in(spares_scanin), |
| 597 | .scan_out(spares_scanout), |
| 598 | .l1clk (l1clk), |
| 599 | .siclk(siclk), |
| 600 | .soclk(soclk) |
| 601 | ); |
| 602 | |
| 603 | |
| 604 | assign itc_dis_clr_ubit = itc_mbist_run & mbist_dis_clr_ubit_ff; |
| 605 | |
| 606 | |
| 607 | |
| 608 | assign se = tcu_scan_en ; |
| 609 | // fixscan start: |
| 610 | assign lsu_err_inj_sig_reg_scanin = scan_in ; |
| 611 | assign error_inj_latch_scanin = lsu_err_inj_sig_reg_scanout; |
| 612 | assign reload0_latch_scanin = error_inj_latch_scanout ; |
| 613 | assign tte0_lat_scanin = reload0_latch_scanout ; |
| 614 | assign tte1_lat_scanin = tte0_lat_scanout ; |
| 615 | assign demap_c0_reg_scanin = tte1_lat_scanout ; |
| 616 | assign demap_c1_reg_scanin = demap_c0_reg_scanout ; |
| 617 | assign reload1_latch_scanin = demap_c1_reg_scanout ; |
| 618 | assign wr_vld_latch_scanin = reload1_latch_scanout ; |
| 619 | assign bist_run_reg_scanin = wr_vld_latch_scanout ; |
| 620 | assign itc_sel_demap_reg_scanin = bist_run_reg_scanout ; |
| 621 | assign itlb_bypass_lat_scanin = itc_sel_demap_reg_scanout; |
| 622 | assign immu_enable_lat_scanin = itlb_bypass_lat_scanout ; |
| 623 | assign spares_scanin = immu_enable_lat_scanout ; |
| 624 | assign scan_out = spares_scanout ; |
| 625 | // fixscan end: |
| 626 | endmodule |
| 627 | |
| 628 | |
| 629 | |
| 630 | |
| 631 | |
| 632 | |
| 633 | |
| 634 | |
| 635 | // any PARAMS parms go into naming of macro |
| 636 | |
| 637 | module ifu_ftu_itc_ctl_l1clkhdr_ctl_macro ( |
| 638 | l2clk, |
| 639 | l1en, |
| 640 | pce_ov, |
| 641 | stop, |
| 642 | se, |
| 643 | l1clk); |
| 644 | |
| 645 | |
| 646 | input l2clk; |
| 647 | input l1en; |
| 648 | input pce_ov; |
| 649 | input stop; |
| 650 | input se; |
| 651 | output l1clk; |
| 652 | |
| 653 | |
| 654 | |
| 655 | |
| 656 | |
| 657 | cl_sc1_l1hdr_8x c_0 ( |
| 658 | |
| 659 | |
| 660 | .l2clk(l2clk), |
| 661 | .pce(l1en), |
| 662 | .l1clk(l1clk), |
| 663 | .se(se), |
| 664 | .pce_ov(pce_ov), |
| 665 | .stop(stop) |
| 666 | ); |
| 667 | |
| 668 | |
| 669 | |
| 670 | endmodule |
| 671 | |
| 672 | |
| 673 | |
| 674 | |
| 675 | |
| 676 | |
| 677 | |
| 678 | |
| 679 | |
| 680 | |
| 681 | |
| 682 | |
| 683 | |
| 684 | // any PARAMS parms go into naming of macro |
| 685 | |
| 686 | module ifu_ftu_itc_ctl_msff_ctl_macro__width_3 ( |
| 687 | din, |
| 688 | l1clk, |
| 689 | scan_in, |
| 690 | siclk, |
| 691 | soclk, |
| 692 | dout, |
| 693 | scan_out); |
| 694 | wire [2:0] fdin; |
| 695 | wire [1:0] so; |
| 696 | |
| 697 | input [2:0] din; |
| 698 | input l1clk; |
| 699 | input scan_in; |
| 700 | |
| 701 | |
| 702 | input siclk; |
| 703 | input soclk; |
| 704 | |
| 705 | output [2:0] dout; |
| 706 | output scan_out; |
| 707 | assign fdin[2:0] = din[2:0]; |
| 708 | |
| 709 | |
| 710 | |
| 711 | |
| 712 | |
| 713 | |
| 714 | dff #(3) d0_0 ( |
| 715 | .l1clk(l1clk), |
| 716 | .siclk(siclk), |
| 717 | .soclk(soclk), |
| 718 | .d(fdin[2:0]), |
| 719 | .si({scan_in,so[1:0]}), |
| 720 | .so({so[1:0],scan_out}), |
| 721 | .q(dout[2:0]) |
| 722 | ); |
| 723 | |
| 724 | |
| 725 | |
| 726 | |
| 727 | |
| 728 | |
| 729 | |
| 730 | |
| 731 | |
| 732 | |
| 733 | |
| 734 | |
| 735 | endmodule |
| 736 | |
| 737 | |
| 738 | |
| 739 | |
| 740 | |
| 741 | |
| 742 | |
| 743 | |
| 744 | |
| 745 | |
| 746 | |
| 747 | |
| 748 | |
| 749 | // any PARAMS parms go into naming of macro |
| 750 | |
| 751 | module ifu_ftu_itc_ctl_msff_ctl_macro__width_2 ( |
| 752 | din, |
| 753 | l1clk, |
| 754 | scan_in, |
| 755 | siclk, |
| 756 | soclk, |
| 757 | dout, |
| 758 | scan_out); |
| 759 | wire [1:0] fdin; |
| 760 | wire [0:0] so; |
| 761 | |
| 762 | input [1:0] din; |
| 763 | input l1clk; |
| 764 | input scan_in; |
| 765 | |
| 766 | |
| 767 | input siclk; |
| 768 | input soclk; |
| 769 | |
| 770 | output [1:0] dout; |
| 771 | output scan_out; |
| 772 | assign fdin[1:0] = din[1:0]; |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | |
| 778 | |
| 779 | dff #(2) d0_0 ( |
| 780 | .l1clk(l1clk), |
| 781 | .siclk(siclk), |
| 782 | .soclk(soclk), |
| 783 | .d(fdin[1:0]), |
| 784 | .si({scan_in,so[0:0]}), |
| 785 | .so({so[0:0],scan_out}), |
| 786 | .q(dout[1:0]) |
| 787 | ); |
| 788 | |
| 789 | |
| 790 | |
| 791 | |
| 792 | |
| 793 | |
| 794 | |
| 795 | |
| 796 | |
| 797 | |
| 798 | |
| 799 | |
| 800 | endmodule |
| 801 | |
| 802 | |
| 803 | |
| 804 | |
| 805 | |
| 806 | |
| 807 | |
| 808 | |
| 809 | |
| 810 | |
| 811 | |
| 812 | |
| 813 | |
| 814 | // any PARAMS parms go into naming of macro |
| 815 | |
| 816 | module ifu_ftu_itc_ctl_msff_ctl_macro__width_8 ( |
| 817 | din, |
| 818 | l1clk, |
| 819 | scan_in, |
| 820 | siclk, |
| 821 | soclk, |
| 822 | dout, |
| 823 | scan_out); |
| 824 | wire [7:0] fdin; |
| 825 | wire [6:0] so; |
| 826 | |
| 827 | input [7:0] din; |
| 828 | input l1clk; |
| 829 | input scan_in; |
| 830 | |
| 831 | |
| 832 | input siclk; |
| 833 | input soclk; |
| 834 | |
| 835 | output [7:0] dout; |
| 836 | output scan_out; |
| 837 | assign fdin[7:0] = din[7:0]; |
| 838 | |
| 839 | |
| 840 | |
| 841 | |
| 842 | |
| 843 | |
| 844 | dff #(8) d0_0 ( |
| 845 | .l1clk(l1clk), |
| 846 | .siclk(siclk), |
| 847 | .soclk(soclk), |
| 848 | .d(fdin[7:0]), |
| 849 | .si({scan_in,so[6:0]}), |
| 850 | .so({so[6:0],scan_out}), |
| 851 | .q(dout[7:0]) |
| 852 | ); |
| 853 | |
| 854 | |
| 855 | |
| 856 | |
| 857 | |
| 858 | |
| 859 | |
| 860 | |
| 861 | |
| 862 | |
| 863 | |
| 864 | |
| 865 | endmodule |
| 866 | |
| 867 | |
| 868 | |
| 869 | |
| 870 | |
| 871 | |
| 872 | |
| 873 | |
| 874 | |
| 875 | |
| 876 | |
| 877 | |
| 878 | |
| 879 | // any PARAMS parms go into naming of macro |
| 880 | |
| 881 | module ifu_ftu_itc_ctl_msff_ctl_macro__width_1 ( |
| 882 | din, |
| 883 | l1clk, |
| 884 | scan_in, |
| 885 | siclk, |
| 886 | soclk, |
| 887 | dout, |
| 888 | scan_out); |
| 889 | wire [0:0] fdin; |
| 890 | |
| 891 | input [0:0] din; |
| 892 | input l1clk; |
| 893 | input scan_in; |
| 894 | |
| 895 | |
| 896 | input siclk; |
| 897 | input soclk; |
| 898 | |
| 899 | output [0:0] dout; |
| 900 | output scan_out; |
| 901 | assign fdin[0:0] = din[0:0]; |
| 902 | |
| 903 | |
| 904 | |
| 905 | |
| 906 | |
| 907 | |
| 908 | dff #(1) d0_0 ( |
| 909 | .l1clk(l1clk), |
| 910 | .siclk(siclk), |
| 911 | .soclk(soclk), |
| 912 | .d(fdin[0:0]), |
| 913 | .si(scan_in), |
| 914 | .so(scan_out), |
| 915 | .q(dout[0:0]) |
| 916 | ); |
| 917 | |
| 918 | |
| 919 | |
| 920 | |
| 921 | |
| 922 | |
| 923 | |
| 924 | |
| 925 | |
| 926 | |
| 927 | |
| 928 | |
| 929 | endmodule |
| 930 | |
| 931 | |
| 932 | |
| 933 | |
| 934 | |
| 935 | |
| 936 | |
| 937 | |
| 938 | |
| 939 | |
| 940 | |
| 941 | |
| 942 | |
| 943 | // any PARAMS parms go into naming of macro |
| 944 | |
| 945 | module ifu_ftu_itc_ctl_msff_ctl_macro__width_5 ( |
| 946 | din, |
| 947 | l1clk, |
| 948 | scan_in, |
| 949 | siclk, |
| 950 | soclk, |
| 951 | dout, |
| 952 | scan_out); |
| 953 | wire [4:0] fdin; |
| 954 | wire [3:0] so; |
| 955 | |
| 956 | input [4:0] din; |
| 957 | input l1clk; |
| 958 | input scan_in; |
| 959 | |
| 960 | |
| 961 | input siclk; |
| 962 | input soclk; |
| 963 | |
| 964 | output [4:0] dout; |
| 965 | output scan_out; |
| 966 | assign fdin[4:0] = din[4:0]; |
| 967 | |
| 968 | |
| 969 | |
| 970 | |
| 971 | |
| 972 | |
| 973 | dff #(5) d0_0 ( |
| 974 | .l1clk(l1clk), |
| 975 | .siclk(siclk), |
| 976 | .soclk(soclk), |
| 977 | .d(fdin[4:0]), |
| 978 | .si({scan_in,so[3:0]}), |
| 979 | .so({so[3:0],scan_out}), |
| 980 | .q(dout[4:0]) |
| 981 | ); |
| 982 | |
| 983 | |
| 984 | |
| 985 | |
| 986 | |
| 987 | |
| 988 | |
| 989 | |
| 990 | |
| 991 | |
| 992 | |
| 993 | |
| 994 | endmodule |
| 995 | |
| 996 | |
| 997 | |
| 998 | |
| 999 | |
| 1000 | |
| 1001 | |
| 1002 | |
| 1003 | |
| 1004 | |
| 1005 | |
| 1006 | |
| 1007 | |
| 1008 | // any PARAMS parms go into naming of macro |
| 1009 | |
| 1010 | module ifu_ftu_itc_ctl_msff_ctl_macro__width_9 ( |
| 1011 | din, |
| 1012 | l1clk, |
| 1013 | scan_in, |
| 1014 | siclk, |
| 1015 | soclk, |
| 1016 | dout, |
| 1017 | scan_out); |
| 1018 | wire [8:0] fdin; |
| 1019 | wire [7:0] so; |
| 1020 | |
| 1021 | input [8:0] din; |
| 1022 | input l1clk; |
| 1023 | input scan_in; |
| 1024 | |
| 1025 | |
| 1026 | input siclk; |
| 1027 | input soclk; |
| 1028 | |
| 1029 | output [8:0] dout; |
| 1030 | output scan_out; |
| 1031 | assign fdin[8:0] = din[8:0]; |
| 1032 | |
| 1033 | |
| 1034 | |
| 1035 | |
| 1036 | |
| 1037 | |
| 1038 | dff #(9) d0_0 ( |
| 1039 | .l1clk(l1clk), |
| 1040 | .siclk(siclk), |
| 1041 | .soclk(soclk), |
| 1042 | .d(fdin[8:0]), |
| 1043 | .si({scan_in,so[7:0]}), |
| 1044 | .so({so[7:0],scan_out}), |
| 1045 | .q(dout[8:0]) |
| 1046 | ); |
| 1047 | |
| 1048 | |
| 1049 | |
| 1050 | |
| 1051 | |
| 1052 | |
| 1053 | |
| 1054 | |
| 1055 | |
| 1056 | |
| 1057 | |
| 1058 | |
| 1059 | endmodule |
| 1060 | |
| 1061 | |
| 1062 | |
| 1063 | |
| 1064 | |
| 1065 | |
| 1066 | |
| 1067 | |
| 1068 | |
| 1069 | |
| 1070 | |
| 1071 | |
| 1072 | |
| 1073 | // any PARAMS parms go into naming of macro |
| 1074 | |
| 1075 | module ifu_ftu_itc_ctl_msff_ctl_macro__width_7 ( |
| 1076 | din, |
| 1077 | l1clk, |
| 1078 | scan_in, |
| 1079 | siclk, |
| 1080 | soclk, |
| 1081 | dout, |
| 1082 | scan_out); |
| 1083 | wire [6:0] fdin; |
| 1084 | wire [5:0] so; |
| 1085 | |
| 1086 | input [6:0] din; |
| 1087 | input l1clk; |
| 1088 | input scan_in; |
| 1089 | |
| 1090 | |
| 1091 | input siclk; |
| 1092 | input soclk; |
| 1093 | |
| 1094 | output [6:0] dout; |
| 1095 | output scan_out; |
| 1096 | assign fdin[6:0] = din[6:0]; |
| 1097 | |
| 1098 | |
| 1099 | |
| 1100 | |
| 1101 | |
| 1102 | |
| 1103 | dff #(7) d0_0 ( |
| 1104 | .l1clk(l1clk), |
| 1105 | .siclk(siclk), |
| 1106 | .soclk(soclk), |
| 1107 | .d(fdin[6:0]), |
| 1108 | .si({scan_in,so[5:0]}), |
| 1109 | .so({so[5:0],scan_out}), |
| 1110 | .q(dout[6:0]) |
| 1111 | ); |
| 1112 | |
| 1113 | |
| 1114 | |
| 1115 | |
| 1116 | |
| 1117 | |
| 1118 | |
| 1119 | |
| 1120 | |
| 1121 | |
| 1122 | |
| 1123 | |
| 1124 | endmodule |
| 1125 | |
| 1126 | |
| 1127 | |
| 1128 | |
| 1129 | |
| 1130 | |
| 1131 | |
| 1132 | |
| 1133 | |
| 1134 | // Description: Spare gate macro for control blocks |
| 1135 | // |
| 1136 | // Param num controls the number of times the macro is added |
| 1137 | // flops=0 can be used to use only combination spare logic |
| 1138 | |
| 1139 | |
| 1140 | module ifu_ftu_itc_ctl_spare_ctl_macro__num_1 ( |
| 1141 | l1clk, |
| 1142 | scan_in, |
| 1143 | siclk, |
| 1144 | soclk, |
| 1145 | scan_out); |
| 1146 | wire si_0; |
| 1147 | wire so_0; |
| 1148 | wire spare0_flop_unused; |
| 1149 | wire spare0_buf_32x_unused; |
| 1150 | wire spare0_nand3_8x_unused; |
| 1151 | wire spare0_inv_8x_unused; |
| 1152 | wire spare0_aoi22_4x_unused; |
| 1153 | wire spare0_buf_8x_unused; |
| 1154 | wire spare0_oai22_4x_unused; |
| 1155 | wire spare0_inv_16x_unused; |
| 1156 | wire spare0_nand2_16x_unused; |
| 1157 | wire spare0_nor3_4x_unused; |
| 1158 | wire spare0_nand2_8x_unused; |
| 1159 | wire spare0_buf_16x_unused; |
| 1160 | wire spare0_nor2_16x_unused; |
| 1161 | wire spare0_inv_32x_unused; |
| 1162 | |
| 1163 | |
| 1164 | input l1clk; |
| 1165 | input scan_in; |
| 1166 | input siclk; |
| 1167 | input soclk; |
| 1168 | output scan_out; |
| 1169 | |
| 1170 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 1171 | .siclk(siclk), |
| 1172 | .soclk(soclk), |
| 1173 | .si(si_0), |
| 1174 | .so(so_0), |
| 1175 | .d(1'b0), |
| 1176 | .q(spare0_flop_unused)); |
| 1177 | assign si_0 = scan_in; |
| 1178 | |
| 1179 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 1180 | .out(spare0_buf_32x_unused)); |
| 1181 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 1182 | .in1(1'b1), |
| 1183 | .in2(1'b1), |
| 1184 | .out(spare0_nand3_8x_unused)); |
| 1185 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 1186 | .out(spare0_inv_8x_unused)); |
| 1187 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 1188 | .in01(1'b1), |
| 1189 | .in10(1'b1), |
| 1190 | .in11(1'b1), |
| 1191 | .out(spare0_aoi22_4x_unused)); |
| 1192 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 1193 | .out(spare0_buf_8x_unused)); |
| 1194 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 1195 | .in01(1'b1), |
| 1196 | .in10(1'b1), |
| 1197 | .in11(1'b1), |
| 1198 | .out(spare0_oai22_4x_unused)); |
| 1199 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 1200 | .out(spare0_inv_16x_unused)); |
| 1201 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 1202 | .in1(1'b1), |
| 1203 | .out(spare0_nand2_16x_unused)); |
| 1204 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 1205 | .in1(1'b0), |
| 1206 | .in2(1'b0), |
| 1207 | .out(spare0_nor3_4x_unused)); |
| 1208 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 1209 | .in1(1'b1), |
| 1210 | .out(spare0_nand2_8x_unused)); |
| 1211 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 1212 | .out(spare0_buf_16x_unused)); |
| 1213 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 1214 | .in1(1'b0), |
| 1215 | .out(spare0_nor2_16x_unused)); |
| 1216 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 1217 | .out(spare0_inv_32x_unused)); |
| 1218 | assign scan_out = so_0; |
| 1219 | |
| 1220 | |
| 1221 | |
| 1222 | endmodule |
| 1223 | |