// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: ifu_ftu_itc_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
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// ========== Copyright Header End ============================================
lsu_asi_error_inject_b31,
lsu_asi_error_inject_b29,
lsu_asi_error_inject_b28,
itc_sel_write_tag_indexed,
wire lsu_err_inj_sig_reg_scanin;
wire lsu_err_inj_sig_reg_scanout;
wire asi_error_inject_b31_ff;
wire asi_error_inject_b29_ff;
wire asi_error_inject_b28_ff;
wire error_inj_latch_scanin;
wire error_inj_latch_scanout;
wire reload0_latch_scanin;
wire reload0_latch_scanout;
wire [2:0] tlu_tte_45_43;
wire [7:0] thr_to_write_in;
wire demap_c0_reg_scanin;
wire demap_c0_reg_scanout;
wire demap_c1_reg_scanin;
wire demap_c1_reg_scanout;
wire reload1_latch_scanin;
wire reload1_latch_scanout;
wire wr_vld_latch_scanin;
wire wr_vld_latch_scanout;
wire mbist_dis_clr_ubit_ff;
wire itc_cam_vld_2_unused;
wire bist_run_reg_scanin;
wire bist_run_reg_scanout;
wire [1:0] itc_demap_type;
wire itc_mbi_itb_write_en;
wire itc_sel_demap_tag_d_in;
wire itc_sel_demap_tag_c0_in;
wire itc_sel_demap_tag_c1_in;
wire itc_sel_demap_reg_scanin;
wire itc_sel_demap_reg_scanout;
wire itc_sel_write_tag_in;
wire itc_sel_write_tag_indexed_in;
wire itc_demap_page_unused;
wire itlb_bypass_lat_scanin;
wire itlb_bypass_lat_scanout;
wire immu_enable_lat_scanin;
wire immu_enable_lat_scanout;
wire [7:0] pre_bypass_bf;
// The following signals indicate the
// first cycle of TTE transfer as well
// as the operation (write or demap)
input [1:0] tlu_itlb_reload;
input [37:35] tlu_trap_pc_0; //
input [37:35] tlu_trap_pc_1; //
input itd_index_valid_in; // Write with index
input [2:0] tlu_trap_pc_0_45_43;
input [2:0] tlu_trap_pc_1_45_43;
input lsu_asi_error_inject_b31;
input lsu_asi_error_inject_b29;
input lsu_asi_error_inject_b28;
input [7:0] tlu_itlb_bypass;
input [7:0] lsu_immu_enable;
input [7:0] ftp_itb_fetch_thr_bf;
input ftp_ith_det_req_bf;
input [1:0] mbi_demap_type ;
input mbi_itb_cam_en_pre ;
input itb_tte_data_v_27_22 ;
input itb_tte_data_v_21_16 ;
output itc_wr_u_en; // Write enable
output itc_rw_index_vld; // Use index for read or write
output itc_demap; // Any demap
output itc_demap_context; // Demap context
output itc_demap_all; // Demap all
output itc_demap_real; // Demap real
output itc_tte_ubit ; // tte_ubit
output itc_sel_trap_pc_0; // Datapath controls
output itc_sel_trap_pc_1;
output itc_sel_demap_tag_d;
output itc_sel_demap_tag_c0;
output itc_sel_demap_tag_c1;
output itc_sel_write_tag;
output itc_sel_write_tag_indexed;
output itc_itlb_rd_vld_bf ;
output itc_tag_error_inj;
output itc_data_error_inj;
output itc_dis_clr_ubit ;
output itc_mbi_itb_read_en;
output [7:0] itc_thr_to_write;
output itc_itb_data_sz_1;
//////////////////////////////////////////////////////////////////////////////
assign pce_ov = tcu_pce_ov;
ifu_ftu_itc_ctl_l1clkhdr_ctl_macro clkgen (
////////////////////////////////////////////////////////////////////////////////
ifu_ftu_itc_ctl_msff_ctl_macro__width_3 lsu_err_inj_sig_reg (
.scan_in(lsu_err_inj_sig_reg_scanin),
.scan_out(lsu_err_inj_sig_reg_scanout),
.din ({lsu_asi_error_inject_b31,
lsu_asi_error_inject_b29,
lsu_asi_error_inject_b28} ),
.dout ({asi_error_inject_b31_ff,
asi_error_inject_b28_ff} ),
assign tag_error_inj = asi_error_inject_b31_ff & asi_error_inject_b28_ff & wr_vld_in;
assign data_error_inj = asi_error_inject_b31_ff & asi_error_inject_b29_ff & wr_vld_in;
ifu_ftu_itc_ctl_msff_ctl_macro__width_2 error_inj_latch (
.scan_in(error_inj_latch_scanin),
.scan_out(error_inj_latch_scanout),
.din ({ tag_error_inj, data_error_inj }),
.dout ({itc_tag_error_inj,itc_data_error_inj }),
assign itc_sel_trap_pc_0 =
tlu_itlb_reload[0] | reload[0];
assign itc_sel_trap_pc_1 =
tlu_itlb_reload[1] | reload[1];
assign demap_next_in = (| tlu_itlb_reload[1:0] );
ifu_ftu_itc_ctl_msff_ctl_macro__width_3 reload0_latch (
.scan_in(reload0_latch_scanin),
.scan_out(reload0_latch_scanout),
.din ({tlu_itlb_reload[1:0], demap_next_in} ),
.dout ({reload[1:0],itc_demap_next} ),
////////////////////////////////////////////////////
// Add logic here for timing reasons. //
////////////////////////////////////////////////////
assign tlu_tte[37:35] = itc_sel_trap_pc_0 ? tlu_trap_pc_0[37:35] : tlu_trap_pc_1[37:35] ;
assign tlu_tte_45_43[2:0] = itc_sel_trap_pc_0 ? tlu_trap_pc_0_45_43[2:0] : tlu_trap_pc_1_45_43[2:0] ;
ifu_ftu_itc_ctl_msff_ctl_macro__width_3 tte0_lat (
.scan_in(tte0_lat_scanin),
.scan_out(tte0_lat_scanout),
assign tte0_tid_dec[0] = ~tte0[37] & ~tte0[36] & ~tte0[35] ;
assign tte0_tid_dec[1] = ~tte0[37] & ~tte0[36] & tte0[35] ;
assign tte0_tid_dec[2] = ~tte0[37] & tte0[36] & ~tte0[35] ;
assign tte0_tid_dec[3] = ~tte0[37] & tte0[36] & tte0[35] ;
assign tte0_tid_dec[4] = tte0[37] & ~tte0[36] & ~tte0[35] ;
assign tte0_tid_dec[5] = tte0[37] & ~tte0[36] & tte0[35] ;
assign tte0_tid_dec[6] = tte0[37] & tte0[36] & ~tte0[35] ;
assign tte0_tid_dec[7] = tte0[37] & tte0[36] & tte0[35] ;
ifu_ftu_itc_ctl_msff_ctl_macro__width_8 tte1_lat (
.scan_in(tte1_lat_scanin),
.scan_out(tte1_lat_scanout),
.din (tte0_tid_dec[7:0]),
.dout (tte1_tid_dec[7:0]),
assign itc_thr_to_write[7:0] = thr_to_write_in[7:0] ;
assign thr_to_write_in[7:0] = ({8{ reload0}} & tte0_tid_dec[7:0]) |
({8{~reload0}} & tte1_tid_dec[7:0]) ;
////////////////////////////////////////////////////
////////////////////////////////////////////////////
////////////////////////////////////////////////////
////////////////////////////////////////////////////
ifu_ftu_itc_ctl_msff_ctl_macro__width_3 demap_c0_reg (
.scan_in(demap_c0_reg_scanin),
.scan_out(demap_c0_reg_scanout),
.din (tlu_tte_45_43[2:0] ),
ifu_ftu_itc_ctl_msff_ctl_macro__width_3 demap_c1_reg (
.scan_in(demap_c1_reg_scanin),
.scan_out(demap_c1_reg_scanout),
ifu_ftu_itc_ctl_msff_ctl_macro__width_1 reload1_latch (
.scan_in(reload1_latch_scanin),
.scan_out(reload1_latch_scanout),
// demap_control[2]: 1 means demap, 0 means write
// demap_control[1:0] (if demap_control[2] is 1)
// demap_control[1:0] (if demap_control[2] is 0)
// 00 Demap and write with supplied context
// 01 Demap and write with context_0
// 10 Demap and write with context_1
// 11 Illegal (but demap and write with context_0)
ifu_ftu_itc_ctl_msff_ctl_macro__width_5 wr_vld_latch (
.scan_in(wr_vld_latch_scanin),
.scan_out(wr_vld_latch_scanout),
.din ({wr_vld_in, mbi_dis_clr_ubit , mbi_repl_write, mbi_itb_cam_en_pre, itc_cam_vld_1} ),
.dout ({wr_vld , mbist_dis_clr_ubit_ff, itc_repl_wrire ,itc_cam_vld_1, itc_cam_vld_2} ),
assign itc_cam_vld_2_unused = itc_cam_vld_2 ;
ifu_ftu_itc_ctl_msff_ctl_macro__width_9 bist_run_reg (
.scan_in(bist_run_reg_scanin),
.scan_out(bist_run_reg_scanout),
.din ({mbi_run,mbi_cambist_run, mbi_itb_demap_en,mbi_demap_type[1:0],
mbi_itb_read_en,mbi_itb_write_en,mbi_wdata_6,mbi_wdata_0}),
.dout ({itc_mbist_run,itc_cambist_run,itc_itb_demap_en,itc_demap_type[1:0],
itc_mbi_itb_read_en,itc_mbi_itb_write_en,itc_mbi_wdata_6,itc_mbi_wdata_0} ),
assign itc_tte_ubit_old = (itc_mbist_run & ~itc_cambist_run) ? itc_mbi_wdata_0 : itc_mbi_wdata_6 ;
assign itc_tte_ubit = itc_tte_ubit_old | (~itc_cambist_run & ~itc_mbist_run) ;
(reload1 & demap_c1[2] & ~demap_c1[1] & ~demap_c1[0]) |
(reload1 & ~demap_c1[2]);
reload1 & demap_c1[2] & ~demap_c1[1] & demap_c1[0];
reload1 & demap_c1[2] & demap_c1[1] & ~demap_c1[0];
reload1 & demap_c1[2] & demap_c1[1] & demap_c1[0];
assign itc_sel_demap_tag_d_in = (reload0 & demap_c0[2] & ~mbi_run) |
(reload0 & ~demap_c0[2] & ~demap_c0[1] & ~mbi_run) ;
assign itc_sel_demap_tag_c0_in = (reload0 & ~demap_c0[2] & demap_c0[0] & ~mbi_run) ;
assign itc_sel_demap_tag_c1_in =
(reload0 & ~demap_c0[2] & demap_c0[1] & ~demap_c0[0] & ~mbi_run) ;
ifu_ftu_itc_ctl_msff_ctl_macro__width_7 itc_sel_demap_reg (
.scan_in(itc_sel_demap_reg_scanin),
.scan_out(itc_sel_demap_reg_scanout),
.din ({itc_sel_demap_tag_d_in,
itc_sel_write_tag_indexed_in,
.dout ({itc_sel_demap_tag_d,
itc_sel_write_tag_indexed,
assign itc_sel_write_tag_in = wr_vld_in & ~itd_index_valid_in & ~mbi_run;
assign itc_sel_write_tag_indexed_in = wr_vld_in & itd_index_valid_in & ~mbi_run;
assign itc_sel_mbist = itc_mbist_run ;
assign itc_sel_default_in = ~reload0 & ~wr_vld_in & ~mbi_run;
assign itc_write_next = wr_vld_in ;
assign itc_demap = (itc_mbist_run & itc_cambist_run) ? itc_itb_demap_en : (!itc_mbist_run & reload1);
assign itc_demap_page = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b00)) :
(!itc_mbist_run & demap_page);
assign itc_demap_context = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b10)) :
(!itc_mbist_run & demap_context);
assign itc_demap_all = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b11)) :
(!itc_mbist_run & demap_all);
assign itc_demap_real = (itc_mbist_run & itc_cambist_run) ? (itc_itb_demap_en & (itc_demap_type[1:0] == 2'b01)) :
(!itc_mbist_run & demap_real);
assign itc_wr_u_en = (wr_vld & ~itc_mbist_run) |
(itc_mbi_itb_write_en & itc_mbist_run);
assign itc_rw_index_vld = (wr_vld & index_valid & ~itc_mbist_run) |
(ftp_itt_rd_req_bf & ~itc_mbist_run) |
(ftp_itd_rd_req_bf & ~itc_mbist_run) |
(itc_mbist_run & ~itc_repl_wrire) |
assign itc_demap_page_unused = itc_demap_page ;
//////////////////////////////////////////////////////////////////////
ifu_ftu_itc_ctl_msff_ctl_macro__width_8 itlb_bypass_lat (
.scan_in(itlb_bypass_lat_scanin),
.scan_out(itlb_bypass_lat_scanout),
.din (tlu_itlb_bypass [7:0] ),
.dout (itlb_bypass [7:0] ),
ifu_ftu_itc_ctl_msff_ctl_macro__width_8 immu_enable_lat (
.scan_in(immu_enable_lat_scanin),
.scan_out(immu_enable_lat_scanout),
.din (lsu_immu_enable [7:0] ),
.dout (immu_enable [7:0] ),
assign pre_bypass_bf[7:0] = ftp_ith_det_req_bf ? 8'h00 :
assign pre_ra_to_pa[7:0] = ftp_ith_det_req_bf ? {8{asi_real_bf}} :
~itlb_bypass[7:0] &~immu_enable[7:0];
(| (ftp_itb_fetch_thr_bf[7:0] & pre_ra_to_pa[7:0]));
(| (ftp_itb_fetch_thr_bf[7:0] & pre_bypass_bf[7:0])) & ~itc_mbist_run;
assign itc_itlb_rd_vld_bf = (ftp_itt_rd_req_bf & ~itc_mbist_run) |
(ftp_itd_rd_req_bf & ~itc_mbist_run) |
(itc_mbi_itb_read_en & itc_mbist_run) ;
assign itc_itb_data_sz_1 = ~itb_tte_data_v_27_22 & itb_tte_data_v_21_16 ;
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
ifu_ftu_itc_ctl_spare_ctl_macro__num_1 spares (
.scan_out(spares_scanout),
assign itc_dis_clr_ubit = itc_mbist_run & mbist_dis_clr_ubit_ff;
assign se = tcu_scan_en ;
assign lsu_err_inj_sig_reg_scanin = scan_in ;
assign error_inj_latch_scanin = lsu_err_inj_sig_reg_scanout;
assign reload0_latch_scanin = error_inj_latch_scanout ;
assign tte0_lat_scanin = reload0_latch_scanout ;
assign tte1_lat_scanin = tte0_lat_scanout ;
assign demap_c0_reg_scanin = tte1_lat_scanout ;
assign demap_c1_reg_scanin = demap_c0_reg_scanout ;
assign reload1_latch_scanin = demap_c1_reg_scanout ;
assign wr_vld_latch_scanin = reload1_latch_scanout ;
assign bist_run_reg_scanin = wr_vld_latch_scanout ;
assign itc_sel_demap_reg_scanin = bist_run_reg_scanout ;
assign itlb_bypass_lat_scanin = itc_sel_demap_reg_scanout;
assign immu_enable_lat_scanin = itlb_bypass_lat_scanout ;
assign spares_scanin = immu_enable_lat_scanout ;
assign scan_out = spares_scanout ;
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_l1clkhdr_ctl_macro (
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_msff_ctl_macro__width_3 (
assign fdin[2:0] = din[2:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_msff_ctl_macro__width_2 (
assign fdin[1:0] = din[1:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_msff_ctl_macro__width_8 (
assign fdin[7:0] = din[7:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_msff_ctl_macro__width_5 (
assign fdin[4:0] = din[4:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_msff_ctl_macro__width_9 (
assign fdin[8:0] = din[8:0];
// any PARAMS parms go into naming of macro
module ifu_ftu_itc_ctl_msff_ctl_macro__width_7 (
assign fdin[6:0] = din[6:0];
// Description: Spare gate macro for control blocks
// Param num controls the number of times the macro is added
// flops=0 can be used to use only combination spare logic
module ifu_ftu_itc_ctl_spare_ctl_macro__num_1 (
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
.out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
.out(spare0_nand3_8x_unused));
cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
.out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
.out(spare0_aoi22_4x_unused));
cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
.out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
.out(spare0_oai22_4x_unused));
cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
.out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
.out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
.out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
.out(spare0_nand2_8x_unused));
cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
.out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
.out(spare0_nor2_16x_unused));
cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
.out(spare0_inv_32x_unused));