| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: n2_ras_vec_dru_8core_64th.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap |
| 39 | #define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap |
| 40 | |
| 41 | #define ENABLE_PCIE_LINK_TRAINING |
| 42 | /* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */ |
| 43 | #define MAIN_PAGE_HV_ALSO |
| 44 | |
| 45 | #include "err_defines.h" |
| 46 | #include "hboot.s" |
| 47 | #include "peu_defines.h" |
| 48 | |
| 49 | #define DMA_DATA_ADDR 0x0000000123456700 |
| 50 | #define DMA_DATA_BYP_ADDR1 0xfffc000123456700 |
| 51 | #define DMA_DATA_BYP_ADDR2 0xfffc000123456780 |
| 52 | #define DMA_DATA_BYP_ADDR3 0xfffc000123456800 |
| 53 | |
| 54 | #define DMA_DATA_ADDR 0x0000000123456700 |
| 55 | #define DMA_DATA_BYP_SADDR 0xfffc000123456700 |
| 56 | #define DMA_DATA_BYP_EADDR 0xfffc000123456800 |
| 57 | |
| 58 | #define ADDR1 0xfffc00002000aa00 |
| 59 | #define TEST_DATA1 0xaaaaaaaaaaaaaaaa |
| 60 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 61 | |
| 62 | #define ERR_BITS 0x2 |
| 63 | #define ERR_BITS_EXPECT 0x8000000000000002 |
| 64 | |
| 65 | |
| 66 | #ifdef L2_0 |
| 67 | #define L2CS_REG 0xA900000000 |
| 68 | #define L2_ERR_STAT_REG 0xAB00000000 |
| 69 | |
| 70 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 71 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 72 | |
| 73 | #define L2_ADDR1 0x2000aa00 |
| 74 | #define L2_ADDR2 0x1000aa00 |
| 75 | |
| 76 | #define ADDR1 0xfffc00002000aa00 |
| 77 | #endif |
| 78 | |
| 79 | |
| 80 | #ifdef L2_1 |
| 81 | #define L2CS_REG 0xA900000040 |
| 82 | #define L2_ERR_STAT_REG 0xAB00000040 |
| 83 | |
| 84 | #define DRAM_ERR_INJ_REG 0x8400000290 |
| 85 | #define DRAM_ERR_STAT_REG 0x8400000280 |
| 86 | |
| 87 | #define L2_ADDR1 0x2000aa40 |
| 88 | #define L2_ADDR2 0x1000aa40 |
| 89 | |
| 90 | #define ADDR1 0xfffc00002000aa40 |
| 91 | #endif |
| 92 | |
| 93 | #ifdef L2_2 |
| 94 | #define L2CS_REG 0xA900000080 |
| 95 | #define L2_ERR_STAT_REG 0xAB00000080 |
| 96 | |
| 97 | #define DRAM_ERR_INJ_REG 0x8400001290 |
| 98 | #define DRAM_ERR_STAT_REG 0x8400001280 |
| 99 | |
| 100 | #define L2_ADDR1 0x2000aa80 |
| 101 | #define L2_ADDR2 0x1000aa80 |
| 102 | |
| 103 | #define ADDR1 0xfffc00002000aa80 |
| 104 | #endif |
| 105 | |
| 106 | |
| 107 | #ifdef L2_3 |
| 108 | #define L2CS_REG 0xA9000000c0 |
| 109 | #define L2_ERR_STAT_REG 0xAB000000c0 |
| 110 | |
| 111 | #define DRAM_ERR_INJ_REG 0x8400001290 |
| 112 | #define DRAM_ERR_STAT_REG 0x8400001280 |
| 113 | |
| 114 | #define L2_ADDR1 0x2000aac0 |
| 115 | #define L2_ADDR2 0x1000aac0 |
| 116 | |
| 117 | #define ADDR1 0xfffc00002000aac0 |
| 118 | #endif |
| 119 | |
| 120 | #ifdef L2_4 |
| 121 | #define L2CS_REG 0xA900000100 |
| 122 | #define L2_ERR_STAT_REG 0xAB00000100 |
| 123 | |
| 124 | #define DRAM_ERR_INJ_REG 0x8400002290 |
| 125 | #define DRAM_ERR_STAT_REG 0x8400002280 |
| 126 | |
| 127 | #define L2_ADDR1 0x2000ab00 |
| 128 | #define L2_ADDR2 0x1000ab00 |
| 129 | |
| 130 | #define ADDR1 0xfffc00002000ab00 |
| 131 | #endif |
| 132 | |
| 133 | #ifdef L2_5 |
| 134 | #define L2CS_REG 0xA900000140 |
| 135 | #define L2_ERR_STAT_REG 0xAB00000140 |
| 136 | |
| 137 | #define DRAM_ERR_INJ_REG 0x8400002290 |
| 138 | #define DRAM_ERR_STAT_REG 0x8400002280 |
| 139 | |
| 140 | #define L2_ADDR1 0x2000ab40 |
| 141 | #define L2_ADDR2 0x1000ab40 |
| 142 | |
| 143 | #define ADDR1 0xfffc00002000ab40 |
| 144 | #endif |
| 145 | |
| 146 | #ifdef L2_6 |
| 147 | #define L2CS_REG 0xA900000180 |
| 148 | #define L2_ERR_STAT_REG 0xAB00000180 |
| 149 | |
| 150 | #define DRAM_ERR_INJ_REG 0x8400003290 |
| 151 | #define DRAM_ERR_STAT_REG 0x8400003280 |
| 152 | |
| 153 | #define L2_ADDR1 0x2000ab80 |
| 154 | #define L2_ADDR2 0x1000ab80 |
| 155 | |
| 156 | #define ADDR1 0xfffc00002000ab80 |
| 157 | #endif |
| 158 | |
| 159 | #ifdef L2_7 |
| 160 | #define L2CS_REG 0xA9000001c0 |
| 161 | #define L2_ERR_STAT_REG 0xAB000001c0 |
| 162 | |
| 163 | #define DRAM_ERR_INJ_REG 0x8400003290 |
| 164 | #define DRAM_ERR_STAT_REG 0x8400003280 |
| 165 | |
| 166 | #define L2_ADDR1 0x2000abc0 |
| 167 | #define L2_ADDR2 0x1000abc0 |
| 168 | |
| 169 | #define ADDR1 0xfffc00002000abc0 |
| 170 | #endif |
| 171 | |
| 172 | #define SYNC_ADDR 0x55500000 |
| 173 | #define L2_ES_W1C_VALUE 0xc03ffffc00000000 |
| 174 | #define DRAM_ES_W1C_VALUE 0xfe00000000000000 |
| 175 | |
| 176 | /************************************************************************ |
| 177 | Test case code start |
| 178 | ************************************************************************/ |
| 179 | .text |
| 180 | .global main |
| 181 | .global My_Corrected_ECC_error_trap |
| 182 | .global My_Recoverable_Sw_error_trap |
| 183 | |
| 184 | main: |
| 185 | ta T_CHANGE_HPRIV |
| 186 | nop |
| 187 | |
| 188 | get_th_id: |
| 189 | ta T_RD_THID |
| 190 | |
| 191 | cmp %o1, 0 |
| 192 | be main_th0 |
| 193 | nop |
| 194 | |
| 195 | ba main_all_other_threads |
| 196 | nop |
| 197 | |
| 198 | main_th0: |
| 199 | clr %i0 |
| 200 | |
| 201 | disable_l1_th0: |
| 202 | ldxa [%g0] ASI_LSU_CONTROL, %l0 |
| 203 | ! Remove the lower 2 bits (I-Cache and D-Cache enables) |
| 204 | andn %l0, 0x3, %l0 |
| 205 | stxa %l0, [%g0] ASI_LSU_CONTROL |
| 206 | |
| 207 | initialize_SYNC_ADDR_th0: |
| 208 | setx SYNC_ADDR, %g7, %o2 |
| 209 | setx 0x1111111111111111, %g7, %g2 |
| 210 | stx %g2, [%o2] |
| 211 | |
| 212 | DRAM_error_inject_th0: |
| 213 | mov 0x606, %l1 ! ECC Mask (2-bit error) |
| 214 | mov 0x1, %l2 |
| 215 | sllx %l2, DRAM_EI_SSHOT, %l3 |
| 216 | Or %l1, %l3, %l1 ! Set single shot ; |
| 217 | mov 0x1, %l2 |
| 218 | sllx %l2, DRAM_EI_ENB, %l3 |
| 219 | or %l1, %l3, %l1 ! Enable error injection for the next write |
| 220 | setx DRAM_ERR_INJ_REG, %l3, %g6 |
| 221 | stx %l1, [%g6] |
| 222 | membar 0x40 |
| 223 | |
| 224 | L2_err_enable_th0: |
| 225 | set 0x3, %l1 |
| 226 | mov 0xaa, %g2 |
| 227 | sllx %g2, 32, %g2 |
| 228 | stx %l1, [%g2] |
| 229 | stx %l1, [%g2 + 0x40] |
| 230 | stx %l1, [%g2 + 0x80] |
| 231 | stx %l1, [%g2 + 0xc0] |
| 232 | stx %l1, [%g2 + 0x100] |
| 233 | stx %l1, [%g2 + 0x140] |
| 234 | stx %l1, [%g2 + 0x180] |
| 235 | stx %l1, [%g2 + 0x1c0] |
| 236 | |
| 237 | |
| 238 | /******************************************************** |
| 239 | INJECT ERROR TO MCU |
| 240 | ********************************************************/ |
| 241 | set_L2_Direct_Mapped_Mode_th0: |
| 242 | setx L2CS_PA0, %l6, %g1 |
| 243 | ldx [%g1], %o6 |
| 244 | mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode |
| 245 | or %o6, %o5, %o6 |
| 246 | stx %o6, [%g1] |
| 247 | membar 0x40 |
| 248 | |
| 249 | |
| 250 | store_to_L2_way0_th0: |
| 251 | setx TEST_DATA1, %l0, %g5 |
| 252 | setx L2_ADDR1, %l0, %g2 ! bits [21:18] select way |
| 253 | stx %g5, [%g2] |
| 254 | membar #Sync |
| 255 | |
| 256 | ! Storing to same L2 way0 but different tag,this will write to mcu |
| 257 | write_mcu_th0: |
| 258 | setx L2_ADDR2, %l0, %g3 ! bits [21:18] select way |
| 259 | stx %g5, [%g3] |
| 260 | membar #Sync |
| 261 | |
| 262 | |
| 263 | /******************************************************* |
| 264 | PIU Init |
| 265 | ********************************************************/ |
| 266 | piu_iommu_th0: |
| 267 | ! enable bypass in IOMMU |
| 268 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 |
| 269 | setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3 |
| 270 | stx %g3, [%g2] |
| 271 | ldx [%g2], %g3 |
| 272 | |
| 273 | |
| 274 | /******************************************************* |
| 275 | LOOP: RDD from DMU |
| 276 | ********************************************************/ |
| 277 | !Loop Count: %i3 |
| 278 | clr %i3 |
| 279 | dma_rdd_loop_th0: |
| 280 | nop |
| 281 | |
| 282 | error_steering_th0: |
| 283 | setx L2CS_PA0, %l6, %g1 |
| 284 | mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode |
| 285 | sllx %i3, 15, %o4 |
| 286 | or %o5, %o4, %o5 |
| 287 | stx %o5, [%g1] |
| 288 | membar 0x40 |
| 289 | |
| 290 | UsrEvnt_rdd_th0: |
| 291 | nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_th0)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * ) |
| 292 | nop |
| 293 | nop |
| 294 | |
| 295 | set_for_loop_th0: |
| 296 | add %i3, 1, %i4 |
| 297 | sllx %i4, 8, %g5 ! Different timeout for each thread |
| 298 | setx 0x2222222222222222, %g7, %g3 |
| 299 | sllx %i3, 22, %g6 |
| 300 | setx 0x22000000, %g7, %g1 |
| 301 | setx 0x88000000, %g7, %g2 |
| 302 | or %g1, %g6, %g1 |
| 303 | or %g2, %g6, %g2 |
| 304 | cause_trap_th0: |
| 305 | stx %g3, [%g1] |
| 306 | ldx [%g2], %g7 |
| 307 | |
| 308 | ! Access another tag; same index in next iteration |
| 309 | sllx %i3, 24, %g4 |
| 310 | add %g1, %g4, %g1 |
| 311 | add %g2, %g4, %g2 |
| 312 | |
| 313 | timeout_th0: |
| 314 | dec %g5 |
| 315 | cmp %g5, %g0 |
| 316 | be test_failed |
| 317 | nop |
| 318 | |
| 319 | thrap_loop_control_th0: |
| 320 | ! Each Thread will Write its THID to SYNC_ADDR |
| 321 | setx SYNC_ADDR, %g7, %g6 |
| 322 | ldx [%g6], %o3 ! Each thread will write to SYNC_ADDR its THID in trap handler |
| 323 | cmp %o3, %i3 ! %i3 has the THID which will get the Trap |
| 324 | bne %xcc, cause_trap_th0 |
| 325 | nop |
| 326 | |
| 327 | |
| 328 | dma_loop_control_th0: |
| 329 | inc %i3 |
| 330 | cmp %i3, NUMBER_THREADS |
| 331 | bne %xcc, dma_rdd_loop_th0 |
| 332 | nop |
| 333 | |
| 334 | !trap handler increases %i0 |
| 335 | check_err_trap_taken_th0: |
| 336 | cmp %i0, 1 |
| 337 | bne test_failed |
| 338 | nop |
| 339 | |
| 340 | pass_th0: |
| 341 | ba test_passed |
| 342 | nop |
| 343 | |
| 344 | |
| 345 | |
| 346 | /******************************************************* |
| 347 | All NON-ZERO THREADS STARTS HERE |
| 348 | ********************************************************/ |
| 349 | main_all_other_threads: |
| 350 | clr %i0 |
| 351 | |
| 352 | ! timeout for TH1=0x400, TH2=0x800 |
| 353 | sllx %o1, 10, %i6 |
| 354 | wait_for_err_trap_all_th: |
| 355 | dec %i6 |
| 356 | cmp %i6, %g0 |
| 357 | timeout_all_th: |
| 358 | be %xcc, test_failed |
| 359 | nop; nop; nop |
| 360 | nop; nop; nop |
| 361 | nop; nop; nop |
| 362 | nop; nop; nop |
| 363 | nop; nop; nop |
| 364 | |
| 365 | !trap handler increases %i0 |
| 366 | cmp %i0, 1 |
| 367 | bne wait_for_err_trap_all_th |
| 368 | nop |
| 369 | |
| 370 | nonzero_th_pass: |
| 371 | nop |
| 372 | /*******************************************************************/ |
| 373 | |
| 374 | |
| 375 | |
| 376 | test_passed: |
| 377 | EXIT_GOOD |
| 378 | |
| 379 | test_failed: |
| 380 | EXIT_BAD |
| 381 | |
| 382 | |
| 383 | /************************************************************************ |
| 384 | RAS |
| 385 | Trap Handlers |
| 386 | ************************************************************************/ |
| 387 | My_Recoverable_Sw_error_trap: |
| 388 | inc %i0 |
| 389 | |
| 390 | check_desr_NcuTrap_tt40: |
| 391 | ldxa [%g0]0x4c, %g2 |
| 392 | nop |
| 393 | setx 0xb000000000000000, %g7, %g3 |
| 394 | subcc %g2, %g3, %g4 |
| 395 | brnz %g4, test_failed |
| 396 | nop |
| 397 | |
| 398 | check_mcu_esr_tt40: |
| 399 | mov 0x1, %l1 |
| 400 | sllx %l1, DRAM_ES_DAU, %l0 |
| 401 | setx DRAM_ERR_STAT_REG, %g7, %g5 |
| 402 | ldx [%g5], %l3 |
| 403 | setx 0x7fffffffffff0000, %g7, %l1 |
| 404 | andcc %l1, %l3, %l4 ! Donot check SYND bits |
| 405 | sub %l0, %l4, %i4 |
| 406 | brnz %i4, test_failed |
| 407 | nop |
| 408 | |
| 409 | clear_mcu_esr_tt40: |
| 410 | setx DRAM_ES_W1C_VALUE, %g7, %g4 |
| 411 | stx %g4, [%g5] |
| 412 | |
| 413 | check_L2_ESR_tt40: |
| 414 | setx L2_ERR_STAT_REG, %g7, %g5 |
| 415 | ldx [%g5], %l6 |
| 416 | setx 0x7ffffffff0000000, %g7, %l0 |
| 417 | andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU |
| 418 | mov 0x1, %l1 |
| 419 | sllx %l1, L2ES_DRU, %l0 |
| 420 | mov 0x1, %l1 |
| 421 | sllx %l1, L2ES_VEU, %l2 |
| 422 | or %l0, %l2, %i4 |
| 423 | cmp %l5, %i4 |
| 424 | bne %xcc, test_failed |
| 425 | nop |
| 426 | |
| 427 | clear_l2_esr_L2Trap_tt40: |
| 428 | setx L2_ES_W1C_VALUE, %g7, %g4 |
| 429 | stx %g4, [%g5] |
| 430 | |
| 431 | sync_addr_0x40: |
| 432 | setx SYNC_ADDR, %g7, %o2 |
| 433 | stx %o1, [%o2] |
| 434 | |
| 435 | trap_done_tt40: |
| 436 | retry |
| 437 | nop |
| 438 | |
| 439 | |
| 440 | |
| 441 | My_Corrected_ECC_error_trap: |
| 442 | ba test_failed |
| 443 | nop |
| 444 | |
| 445 | |
| 446 | /************************************************************************ |
| 447 | Test case data start |
| 448 | ************************************************************************/ |
| 449 | |
| 450 | SECTION .DATA DATA_VA=DMA_DATA_ADDR |
| 451 | attr_data { |
| 452 | Name = .DATA, |
| 453 | hypervisor, |
| 454 | compressimage |
| 455 | } |
| 456 | |
| 457 | .data |
| 458 | .global PCIAddr9 |
| 459 | .xword 0x0001020304050607 |
| 460 | .xword 0x08090a0b0c0d0e0f |
| 461 | .xword 0x1011121314151617 |
| 462 | .xword 0x18191a1b1c1d1e1f |
| 463 | .xword 0x2021222324252627 |
| 464 | .xword 0x28292a2b2c2d2e2f |
| 465 | .xword 0x3031323334353637 |
| 466 | .xword 0x38393a3b3c3d3e3f |
| 467 | |
| 468 | .xword 0x4041424344454647 |
| 469 | .xword 0x48494a4b4c4d4e4f |
| 470 | .xword 0x5051525354555657 |
| 471 | .xword 0x58595a5b5c5d5e5f |
| 472 | .xword 0x6061626364656667 |
| 473 | .xword 0x68696a6b6c6d6e6f |
| 474 | .xword 0x7071727374757677 |
| 475 | .xword 0x78797a7b7c7d7e7f |
| 476 | |
| 477 | .xword 0x8081828384858687 |
| 478 | .xword 0x88898a8b8c8d8e8f |
| 479 | .xword 0x9091929394959697 |
| 480 | .xword 0x98999a9b9c9d9e9f |
| 481 | .xword 0xa0a1a2a3a4a5a6a7 |
| 482 | .xword 0xa8a9aaabacadaeaf |
| 483 | .xword 0xb0b1b2b3b4b5b6b7 |
| 484 | .xword 0xb8b9babbbcbdbebf |
| 485 | |
| 486 | .xword 0xc0c1c2c3c4c5c6c7 |
| 487 | .xword 0xc8c9cacbcccdcecf |
| 488 | .xword 0xd0d1d2d3d4d5d6d7 |
| 489 | .xword 0xd8d9dadbdcdddedf |
| 490 | .xword 0xe0e1e2e3e4e5e6e7 |
| 491 | .xword 0xe8e9eaebecedeeef |
| 492 | .xword 0xf0f1f2f3f4f5f6f7 |
| 493 | .xword 0xf8f9fafbfcfdfeff |
| 494 | |
| 495 | .xword 0x0001020304050607 |
| 496 | .xword 0x08090a0b0c0d0e0f |
| 497 | .xword 0x1011121314151617 |
| 498 | .xword 0x18191a1b1c1d1e1f |
| 499 | .xword 0x2021222324252627 |
| 500 | .xword 0x28292a2b2c2d2e2f |
| 501 | .xword 0x3031323334353637 |
| 502 | .xword 0x38393a3b3c3d3e3f |
| 503 | |
| 504 | .xword 0x4041424344454647 |
| 505 | .xword 0x48494a4b4c4d4e4f |
| 506 | .xword 0x5051525354555657 |
| 507 | .xword 0x58595a5b5c5d5e5f |
| 508 | .xword 0x6061626364656667 |
| 509 | .xword 0x68696a6b6c6d6e6f |
| 510 | .xword 0x7071727374757677 |
| 511 | .xword 0x78797a7b7c7d7e7f |
| 512 | |
| 513 | .xword 0x8081828384858687 |
| 514 | .xword 0x88898a8b8c8d8e8f |
| 515 | .xword 0x9091929394959697 |
| 516 | .xword 0x98999a9b9c9d9e9f |
| 517 | .xword 0xa0a1a2a3a4a5a6a7 |
| 518 | .xword 0xa8a9aaabacadaeaf |
| 519 | .xword 0xb0b1b2b3b4b5b6b7 |
| 520 | .xword 0xb8b9babbbcbdbebf |
| 521 | |
| 522 | .xword 0xc0c1c2c3c4c5c6c7 |
| 523 | .xword 0xc8c9cacbcccdcecf |
| 524 | .xword 0xd0d1d2d3d4d5d6d7 |
| 525 | .xword 0xd8d9dadbdcdddedf |
| 526 | .xword 0xe0e1e2e3e4e5e6e7 |
| 527 | .xword 0xe8e9eaebecedeeef |
| 528 | .xword 0xf0f1f2f3f4f5f6f7 |
| 529 | .xword 0xf8f9fafbfcfdfeff |
| 530 | |
| 531 | /************************************************************************/ |
| 532 | |