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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / verif / diag / assembly / arch / error / vec / n2_ras_vec_dru_8core_64th.s
/*
* ========== Copyright Header Begin ==========================================
*
* OpenSPARC T2 Processor File: n2_ras_vec_dru_8core_64th.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
*
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* otherwise unspecified.
*
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* have any questions.
*
*
* ========== Copyright Header End ============================================
*/
#define H_HT0_Hw_Corrected_Error_0x63 My_Corrected_ECC_error_trap
#define H_HT0_Sw_Recoverable_Error_0x40 My_Recoverable_Sw_error_trap
#define ENABLE_PCIE_LINK_TRAINING
/* #define MAIN_PAGE_NUCLEUS_ALSO */ /* Access main in priviledge mode */
#define MAIN_PAGE_HV_ALSO
#include "err_defines.h"
#include "hboot.s"
#include "peu_defines.h"
#define DMA_DATA_ADDR 0x0000000123456700
#define DMA_DATA_BYP_ADDR1 0xfffc000123456700
#define DMA_DATA_BYP_ADDR2 0xfffc000123456780
#define DMA_DATA_BYP_ADDR3 0xfffc000123456800
#define DMA_DATA_ADDR 0x0000000123456700
#define DMA_DATA_BYP_SADDR 0xfffc000123456700
#define DMA_DATA_BYP_EADDR 0xfffc000123456800
#define ADDR1 0xfffc00002000aa00
#define TEST_DATA1 0xaaaaaaaaaaaaaaaa
#define DRAM_ERR_INJ_REG 0x8400000290
#define ERR_BITS 0x2
#define ERR_BITS_EXPECT 0x8000000000000002
#ifdef L2_0
#define L2CS_REG 0xA900000000
#define L2_ERR_STAT_REG 0xAB00000000
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define L2_ADDR1 0x2000aa00
#define L2_ADDR2 0x1000aa00
#define ADDR1 0xfffc00002000aa00
#endif
#ifdef L2_1
#define L2CS_REG 0xA900000040
#define L2_ERR_STAT_REG 0xAB00000040
#define DRAM_ERR_INJ_REG 0x8400000290
#define DRAM_ERR_STAT_REG 0x8400000280
#define L2_ADDR1 0x2000aa40
#define L2_ADDR2 0x1000aa40
#define ADDR1 0xfffc00002000aa40
#endif
#ifdef L2_2
#define L2CS_REG 0xA900000080
#define L2_ERR_STAT_REG 0xAB00000080
#define DRAM_ERR_INJ_REG 0x8400001290
#define DRAM_ERR_STAT_REG 0x8400001280
#define L2_ADDR1 0x2000aa80
#define L2_ADDR2 0x1000aa80
#define ADDR1 0xfffc00002000aa80
#endif
#ifdef L2_3
#define L2CS_REG 0xA9000000c0
#define L2_ERR_STAT_REG 0xAB000000c0
#define DRAM_ERR_INJ_REG 0x8400001290
#define DRAM_ERR_STAT_REG 0x8400001280
#define L2_ADDR1 0x2000aac0
#define L2_ADDR2 0x1000aac0
#define ADDR1 0xfffc00002000aac0
#endif
#ifdef L2_4
#define L2CS_REG 0xA900000100
#define L2_ERR_STAT_REG 0xAB00000100
#define DRAM_ERR_INJ_REG 0x8400002290
#define DRAM_ERR_STAT_REG 0x8400002280
#define L2_ADDR1 0x2000ab00
#define L2_ADDR2 0x1000ab00
#define ADDR1 0xfffc00002000ab00
#endif
#ifdef L2_5
#define L2CS_REG 0xA900000140
#define L2_ERR_STAT_REG 0xAB00000140
#define DRAM_ERR_INJ_REG 0x8400002290
#define DRAM_ERR_STAT_REG 0x8400002280
#define L2_ADDR1 0x2000ab40
#define L2_ADDR2 0x1000ab40
#define ADDR1 0xfffc00002000ab40
#endif
#ifdef L2_6
#define L2CS_REG 0xA900000180
#define L2_ERR_STAT_REG 0xAB00000180
#define DRAM_ERR_INJ_REG 0x8400003290
#define DRAM_ERR_STAT_REG 0x8400003280
#define L2_ADDR1 0x2000ab80
#define L2_ADDR2 0x1000ab80
#define ADDR1 0xfffc00002000ab80
#endif
#ifdef L2_7
#define L2CS_REG 0xA9000001c0
#define L2_ERR_STAT_REG 0xAB000001c0
#define DRAM_ERR_INJ_REG 0x8400003290
#define DRAM_ERR_STAT_REG 0x8400003280
#define L2_ADDR1 0x2000abc0
#define L2_ADDR2 0x1000abc0
#define ADDR1 0xfffc00002000abc0
#endif
#define SYNC_ADDR 0x55500000
#define L2_ES_W1C_VALUE 0xc03ffffc00000000
#define DRAM_ES_W1C_VALUE 0xfe00000000000000
/************************************************************************
Test case code start
************************************************************************/
.text
.global main
.global My_Corrected_ECC_error_trap
.global My_Recoverable_Sw_error_trap
main:
ta T_CHANGE_HPRIV
nop
get_th_id:
ta T_RD_THID
cmp %o1, 0
be main_th0
nop
ba main_all_other_threads
nop
main_th0:
clr %i0
disable_l1_th0:
ldxa [%g0] ASI_LSU_CONTROL, %l0
! Remove the lower 2 bits (I-Cache and D-Cache enables)
andn %l0, 0x3, %l0
stxa %l0, [%g0] ASI_LSU_CONTROL
initialize_SYNC_ADDR_th0:
setx SYNC_ADDR, %g7, %o2
setx 0x1111111111111111, %g7, %g2
stx %g2, [%o2]
DRAM_error_inject_th0:
mov 0x606, %l1 ! ECC Mask (2-bit error)
mov 0x1, %l2
sllx %l2, DRAM_EI_SSHOT, %l3
Or %l1, %l3, %l1 ! Set single shot ;
mov 0x1, %l2
sllx %l2, DRAM_EI_ENB, %l3
or %l1, %l3, %l1 ! Enable error injection for the next write
setx DRAM_ERR_INJ_REG, %l3, %g6
stx %l1, [%g6]
membar 0x40
L2_err_enable_th0:
set 0x3, %l1
mov 0xaa, %g2
sllx %g2, 32, %g2
stx %l1, [%g2]
stx %l1, [%g2 + 0x40]
stx %l1, [%g2 + 0x80]
stx %l1, [%g2 + 0xc0]
stx %l1, [%g2 + 0x100]
stx %l1, [%g2 + 0x140]
stx %l1, [%g2 + 0x180]
stx %l1, [%g2 + 0x1c0]
/********************************************************
INJECT ERROR TO MCU
********************************************************/
set_L2_Direct_Mapped_Mode_th0:
setx L2CS_PA0, %l6, %g1
ldx [%g1], %o6
mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
or %o6, %o5, %o6
stx %o6, [%g1]
membar 0x40
store_to_L2_way0_th0:
setx TEST_DATA1, %l0, %g5
setx L2_ADDR1, %l0, %g2 ! bits [21:18] select way
stx %g5, [%g2]
membar #Sync
! Storing to same L2 way0 but different tag,this will write to mcu
write_mcu_th0:
setx L2_ADDR2, %l0, %g3 ! bits [21:18] select way
stx %g5, [%g3]
membar #Sync
/*******************************************************
PIU Init
********************************************************/
piu_iommu_th0:
! enable bypass in IOMMU
setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
setx FIRE_DLC_MMU_CSR_A_CTL__BYPASS_EN, %g1, %g3
stx %g3, [%g2]
ldx [%g2], %g3
/*******************************************************
LOOP: RDD from DMU
********************************************************/
!Loop Count: %i3
clr %i3
dma_rdd_loop_th0:
nop
error_steering_th0:
setx L2CS_PA0, %l6, %g1
mov 0x2, %o5 ! L2_CSR_REG<1>=1 => DM mode
sllx %i3, 15, %o4
or %o5, %o4, %o5
stx %o5, [%g1]
membar 0x40
UsrEvnt_rdd_th0:
nop ! $EV trig_pc_d(1, @VA(.MAIN.UsrEvnt_rdd_th0)) -> EnablePCIeIgCmd ("DMARD_UE", ADDR1, ADDR1, "64'h40", 1, *, * )
nop
nop
set_for_loop_th0:
add %i3, 1, %i4
sllx %i4, 8, %g5 ! Different timeout for each thread
setx 0x2222222222222222, %g7, %g3
sllx %i3, 22, %g6
setx 0x22000000, %g7, %g1
setx 0x88000000, %g7, %g2
or %g1, %g6, %g1
or %g2, %g6, %g2
cause_trap_th0:
stx %g3, [%g1]
ldx [%g2], %g7
! Access another tag; same index in next iteration
sllx %i3, 24, %g4
add %g1, %g4, %g1
add %g2, %g4, %g2
timeout_th0:
dec %g5
cmp %g5, %g0
be test_failed
nop
thrap_loop_control_th0:
! Each Thread will Write its THID to SYNC_ADDR
setx SYNC_ADDR, %g7, %g6
ldx [%g6], %o3 ! Each thread will write to SYNC_ADDR its THID in trap handler
cmp %o3, %i3 ! %i3 has the THID which will get the Trap
bne %xcc, cause_trap_th0
nop
dma_loop_control_th0:
inc %i3
cmp %i3, NUMBER_THREADS
bne %xcc, dma_rdd_loop_th0
nop
!trap handler increases %i0
check_err_trap_taken_th0:
cmp %i0, 1
bne test_failed
nop
pass_th0:
ba test_passed
nop
/*******************************************************
All NON-ZERO THREADS STARTS HERE
********************************************************/
main_all_other_threads:
clr %i0
! timeout for TH1=0x400, TH2=0x800
sllx %o1, 10, %i6
wait_for_err_trap_all_th:
dec %i6
cmp %i6, %g0
timeout_all_th:
be %xcc, test_failed
nop; nop; nop
nop; nop; nop
nop; nop; nop
nop; nop; nop
nop; nop; nop
!trap handler increases %i0
cmp %i0, 1
bne wait_for_err_trap_all_th
nop
nonzero_th_pass:
nop
/*******************************************************************/
test_passed:
EXIT_GOOD
test_failed:
EXIT_BAD
/************************************************************************
RAS
Trap Handlers
************************************************************************/
My_Recoverable_Sw_error_trap:
inc %i0
check_desr_NcuTrap_tt40:
ldxa [%g0]0x4c, %g2
nop
setx 0xb000000000000000, %g7, %g3
subcc %g2, %g3, %g4
brnz %g4, test_failed
nop
check_mcu_esr_tt40:
mov 0x1, %l1
sllx %l1, DRAM_ES_DAU, %l0
setx DRAM_ERR_STAT_REG, %g7, %g5
ldx [%g5], %l3
setx 0x7fffffffffff0000, %g7, %l1
andcc %l1, %l3, %l4 ! Donot check SYND bits
sub %l0, %l4, %i4
brnz %i4, test_failed
nop
clear_mcu_esr_tt40:
setx DRAM_ES_W1C_VALUE, %g7, %g4
stx %g4, [%g5]
check_L2_ESR_tt40:
setx L2_ERR_STAT_REG, %g7, %g5
ldx [%g5], %l6
setx 0x7ffffffff0000000, %g7, %l0
andcc %l0, %l6, %l5 ! Donot check L2ESR SYND bits and MEU
mov 0x1, %l1
sllx %l1, L2ES_DRU, %l0
mov 0x1, %l1
sllx %l1, L2ES_VEU, %l2
or %l0, %l2, %i4
cmp %l5, %i4
bne %xcc, test_failed
nop
clear_l2_esr_L2Trap_tt40:
setx L2_ES_W1C_VALUE, %g7, %g4
stx %g4, [%g5]
sync_addr_0x40:
setx SYNC_ADDR, %g7, %o2
stx %o1, [%o2]
trap_done_tt40:
retry
nop
My_Corrected_ECC_error_trap:
ba test_failed
nop
/************************************************************************
Test case data start
************************************************************************/
SECTION .DATA DATA_VA=DMA_DATA_ADDR
attr_data {
Name = .DATA,
hypervisor,
compressimage
}
.data
.global PCIAddr9
.xword 0x0001020304050607
.xword 0x08090a0b0c0d0e0f
.xword 0x1011121314151617
.xword 0x18191a1b1c1d1e1f
.xword 0x2021222324252627
.xword 0x28292a2b2c2d2e2f
.xword 0x3031323334353637
.xword 0x38393a3b3c3d3e3f
.xword 0x4041424344454647
.xword 0x48494a4b4c4d4e4f
.xword 0x5051525354555657
.xword 0x58595a5b5c5d5e5f
.xword 0x6061626364656667
.xword 0x68696a6b6c6d6e6f
.xword 0x7071727374757677
.xword 0x78797a7b7c7d7e7f
.xword 0x8081828384858687
.xword 0x88898a8b8c8d8e8f
.xword 0x9091929394959697
.xword 0x98999a9b9c9d9e9f
.xword 0xa0a1a2a3a4a5a6a7
.xword 0xa8a9aaabacadaeaf
.xword 0xb0b1b2b3b4b5b6b7
.xword 0xb8b9babbbcbdbebf
.xword 0xc0c1c2c3c4c5c6c7
.xword 0xc8c9cacbcccdcecf
.xword 0xd0d1d2d3d4d5d6d7
.xword 0xd8d9dadbdcdddedf
.xword 0xe0e1e2e3e4e5e6e7
.xword 0xe8e9eaebecedeeef
.xword 0xf0f1f2f3f4f5f6f7
.xword 0xf8f9fafbfcfdfeff
.xword 0x0001020304050607
.xword 0x08090a0b0c0d0e0f
.xword 0x1011121314151617
.xword 0x18191a1b1c1d1e1f
.xword 0x2021222324252627
.xword 0x28292a2b2c2d2e2f
.xword 0x3031323334353637
.xword 0x38393a3b3c3d3e3f
.xword 0x4041424344454647
.xword 0x48494a4b4c4d4e4f
.xword 0x5051525354555657
.xword 0x58595a5b5c5d5e5f
.xword 0x6061626364656667
.xword 0x68696a6b6c6d6e6f
.xword 0x7071727374757677
.xword 0x78797a7b7c7d7e7f
.xword 0x8081828384858687
.xword 0x88898a8b8c8d8e8f
.xword 0x9091929394959697
.xword 0x98999a9b9c9d9e9f
.xword 0xa0a1a2a3a4a5a6a7
.xword 0xa8a9aaabacadaeaf
.xword 0xb0b1b2b3b4b5b6b7
.xword 0xb8b9babbbcbdbebf
.xword 0xc0c1c2c3c4c5c6c7
.xword 0xc8c9cacbcccdcecf
.xword 0xd0d1d2d3d4d5d6d7
.xword 0xd8d9dadbdcdddedf
.xword 0xe0e1e2e3e4e5e6e7
.xword 0xe8e9eaebecedeeef
.xword 0xf0f1f2f3f4f5f6f7
.xword 0xf8f9fafbfcfdfeff
/************************************************************************/
Full OpenSPARC design & verification tarball including full HDL.