| 1 | /* |
| 2 | * ========== Copyright Header Begin ========================================== |
| 3 | * |
| 4 | * OpenSPARC T2 Processor File: PCIeIommu4UBypTrInv.s |
| 5 | * Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 6 | * 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 7 | * |
| 8 | * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License as published by |
| 12 | * the Free Software Foundation; version 2 of the License. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | * |
| 19 | * You should have received a copy of the GNU General Public License |
| 20 | * along with this program; if not, write to the Free Software |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 22 | * |
| 23 | * For the avoidance of doubt, and except that if any non-GPL license |
| 24 | * choice is available it will apply instead, Sun elects to use only |
| 25 | * the General Public License version 2 (GPLv2) at this time for any |
| 26 | * software where a choice of GPL license versions is made |
| 27 | * available with the language indicating that GPLv2 or any later version |
| 28 | * may be used, or where a choice of which version of the GPL is applied is |
| 29 | * otherwise unspecified. |
| 30 | * |
| 31 | * Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 32 | * CA 95054 USA or visit www.sun.com if you need additional information or |
| 33 | * have any questions. |
| 34 | * |
| 35 | * |
| 36 | * ========== Copyright Header End ============================================ |
| 37 | */ |
| 38 | #define ENABLE_PCIE_LINK_TRAINING |
| 39 | #define MAIN_PAGE_HV_ALSO |
| 40 | |
| 41 | #define ENABLE_INTR0x60 1 |
| 42 | |
| 43 | #define INTR0x60_MONDO_IV 63 |
| 44 | |
| 45 | #define INTR0x60_MONDO_20_V 1 |
| 46 | #define INTR0x60_MONDO_20_THREAD 0 |
| 47 | #define INTR0x60_MONDO_20_CNTRL 0 |
| 48 | |
| 49 | |
| 50 | #define INTR0x60_INTA_EXTRA_HANDLER \ |
| 51 | setx intr_count, %g4, %g3; \ |
| 52 | add %g3, %g1, %g3; \ |
| 53 | ldub [%g3], %g4; \ |
| 54 | inc %g4; \ |
| 55 | stb %g4, [%g3] |
| 56 | |
| 57 | #include "interrupt0x60_defines.h" |
| 58 | |
| 59 | #include "hboot.s" |
| 60 | #include "peu_defines.h" |
| 61 | #include "ncu_defines.h" |
| 62 | #include "cmp_macros.h" |
| 63 | |
| 64 | #include "interrupt0x60_handler.s" |
| 65 | |
| 66 | #define MEM32_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA) |
| 67 | |
| 68 | #define DMA_DATA_ADDR 0x00800000 |
| 69 | |
| 70 | #define IOMMU_TTE_ADDR 0x40000000 |
| 71 | |
| 72 | ! Bit 8 = Page Size: 0=8KB, 1=64KB; Bits 3:0 = TSB Table size: 6=64k entries |
| 73 | #define MMU_TSB_CNTRL_REG_DATA mpeval(IOMMU_TTE_ADDR | 0x100 | 6) |
| 74 | |
| 75 | #define NCU_IOMMU_INVALIDATE_REG_ADDR 0x8000002030 |
| 76 | |
| 77 | /************************************************************************ |
| 78 | Test case code start |
| 79 | ************************************************************************/ |
| 80 | SECTION .MAIN |
| 81 | .text |
| 82 | .global main |
| 83 | |
| 84 | main: |
| 85 | ta T_CHANGE_HPRIV |
| 86 | nop |
| 87 | |
| 88 | th_fork(th_main, %l0) |
| 89 | |
| 90 | th_main_0: |
| 91 | ! enable interrupts & provide basic handler |
| 92 | !#include "piu_rupt_enable.s" |
| 93 | |
| 94 | ! enable SUN4U translation in the IOMMU |
| 95 | |
| 96 | setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2 |
| 97 | setx 0x00301, %g1, %g3 ! 9:8 11 = Cache enabled, 0: 1 = translation enabled |
| 98 | stx %g3, [%g2] |
| 99 | ldx [%g2], %g3 |
| 100 | |
| 101 | ! load address of the TSB table, and the page size (64KB) |
| 102 | |
| 103 | setx FIRE_DLC_MMU_CSR_A_TSB_ADDR, %g1, %g2 |
| 104 | setx MMU_TSB_CNTRL_REG_DATA, %g1, %g3 |
| 105 | stx %g3, [%g2] |
| 106 | ldx [%g2], %g3 |
| 107 | |
| 108 | ! Trigger some DMA Reads that will create IOMMU tlb entries |
| 109 | |
| 110 | #define DMA_ADDR_1 mpeval(0x00800000,16,16) |
| 111 | DMA1: nop |
| 112 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA1)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1) |
| 113 | #define DMA_ADDR_2 mpeval(0x00810000,16,16) |
| 114 | DMA2: nop |
| 115 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA2)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1) |
| 116 | #define DMA_ADDR_3 mpeval(0x00820000,16,16) |
| 117 | DMA3: nop |
| 118 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA3)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1) |
| 119 | #define DMA_ADDR_4 mpeval(0x00830000,16,16) |
| 120 | DMA4: nop |
| 121 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA4)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1) |
| 122 | #define DMA_ADDR_5 mpeval(0x00840000,16,16) |
| 123 | DMA5: nop |
| 124 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA5)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1) |
| 125 | #define DMA_ADDR_6 mpeval(0x00850000,16,16) |
| 126 | DMA6: nop |
| 127 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA6)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1) |
| 128 | #define DMA_ADDR_7 mpeval(0x00860000,16,16) |
| 129 | DMA7: nop |
| 130 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA7)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1) |
| 131 | |
| 132 | #define DMA_ADDR_8 mpeval(0x00870000,16,16) |
| 133 | #define DMA_ADDR_8d mpeval(0x00870000) |
| 134 | DMA8: nop |
| 135 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1) |
| 136 | |
| 137 | INTA_ASSERT_Evnt: nop |
| 138 | ! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1 ) |
| 139 | |
| 140 | intr_wait_1: |
| 141 | mov 1, %g4 |
| 142 | setx intr_count, %l1, %g3 |
| 143 | best_set_reg(0x200, %l1, %g2) ! timeout count |
| 144 | |
| 145 | intr_wait_loop_top_1: |
| 146 | ldub [%g3], %g5 |
| 147 | cmp %g5, %g4 |
| 148 | be INTA_DEASSERT_Evnt |
| 149 | dec %g2 |
| 150 | |
| 151 | cmp %g2, 0 |
| 152 | bne intr_wait_loop_top_1 |
| 153 | nop |
| 154 | |
| 155 | intr_timeout1: |
| 156 | !$EV trig_pc_d(1, @VA(.MAIN.intr_timeout1)) -> printf("ERROR: Timeout waiting for interrupt 1",*,1) |
| 157 | EXIT_BAD |
| 158 | |
| 159 | |
| 160 | INTA_DEASSERT_Evnt: nop |
| 161 | ! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1 ) |
| 162 | |
| 163 | ! the last DMA should be complete |
| 164 | |
| 165 | setx DMA_ADDR_8d, %g1, %g2 ! DMA tgt address |
| 166 | ldx [%g2], %g5 ! get the last dma data area |
| 167 | brnz %g5, invalidate_the_TTE_in_memory |
| 168 | nop |
| 169 | b test_failed |
| 170 | nop |
| 171 | |
| 172 | ! now clear the VALID bit of the TTEs in memory |
| 173 | |
| 174 | invalidate_the_TTE_in_memory: |
| 175 | !setx iommu_tte_addr, %g1, %g2 ! TTE address |
| 176 | |
| 177 | setx mpeval(IOMMU_TTE_ADDR+(8*0x80)), %g1, %g2 ! get the TTE address |
| 178 | |
| 179 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 180 | add %g2, 8, %g2 ! address of next TTE |
| 181 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 182 | add %g2, 8, %g2 ! address of next TTE |
| 183 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 184 | add %g2, 8, %g2 ! address of next TTE |
| 185 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 186 | add %g2, 8, %g2 ! address of next TTE |
| 187 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 188 | add %g2, 8, %g2 ! address of next TTE |
| 189 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 190 | add %g2, 8, %g2 ! address of next TTE |
| 191 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 192 | add %g2, 8, %g2 ! address of next TTE |
| 193 | stb %g0, [%g2 + 7] ! clear the last byte of the TTE |
| 194 | membar 0x40 |
| 195 | |
| 196 | ! now do some more DMAs using the same TTEs |
| 197 | |
| 198 | DMA65: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA65) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1) |
| 199 | DMA66: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA66) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1) |
| 200 | DMA67: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA67) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1) |
| 201 | DMA68: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA68) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1) |
| 202 | DMA69: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA69) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1) |
| 203 | DMA70: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA70) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1) |
| 204 | DMA71: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA71) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1) |
| 205 | DMA72: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA72) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1) |
| 206 | #define DMA_ADDR_9 mpeval(0x00880000,16,16) |
| 207 | #define DMA_ADDR_9d mpeval(0x00880000) |
| 208 | DMA9: nop |
| 209 | ! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_9, DMA_ADDR_9, "64'h40",1) |
| 210 | |
| 211 | INTA_ASSERT_Evnt2: nop |
| 212 | ! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1) |
| 213 | |
| 214 | intr_wait_2: |
| 215 | mov 2, %g4 |
| 216 | setx intr_count, %l1, %g3 |
| 217 | best_set_reg(0x200, %l1, %g2) ! timeout count |
| 218 | |
| 219 | intr_wait_loop_top_2: |
| 220 | ldub [%g3], %g5 |
| 221 | cmp %g5, %g4 |
| 222 | be INTA_DEASSERT_Evnt2 |
| 223 | dec %g2 |
| 224 | |
| 225 | cmp %g2, 0 |
| 226 | bne intr_wait_loop_top_2 |
| 227 | nop |
| 228 | |
| 229 | intr_timeout2: |
| 230 | !$EV trig_pc_d(1, @VA(.MAIN.intr_timeout2)) -> printf("ERROR: Timeout waiting for interrupt 2",*,1) |
| 231 | EXIT_BAD |
| 232 | |
| 233 | |
| 234 | INTA_DEASSERT_Evnt2: nop |
| 235 | ! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT",1 ) |
| 236 | |
| 237 | ! the last DMA should be complete |
| 238 | |
| 239 | setx DMA_ADDR_9d, %g1, %g2 ! DMA tgt address |
| 240 | ldx [%g2], %g5 ! get the last dma data area |
| 241 | brnz %g5, test_passed |
| 242 | nop |
| 243 | b test_failed |
| 244 | nop |
| 245 | |
| 246 | |
| 247 | /************************************************************************ |
| 248 | Threads 1 - 7 will issue the IOMMU INVALIDATES |
| 249 | ************************************************************************/ |
| 250 | th_main_1: |
| 251 | setx th_data_1, %g1, %g2 |
| 252 | b th_1to7_join |
| 253 | nop |
| 254 | th_main_2: |
| 255 | setx th_data_2, %g1, %g2 |
| 256 | b th_1to7_join |
| 257 | nop |
| 258 | th_main_3: |
| 259 | setx th_data_3, %g1, %g2 |
| 260 | b th_1to7_join |
| 261 | nop |
| 262 | th_main_4: |
| 263 | setx th_data_4, %g1, %g2 |
| 264 | b th_1to7_join |
| 265 | nop |
| 266 | th_main_5: |
| 267 | setx th_data_5, %g1, %g2 |
| 268 | b th_1to7_join |
| 269 | nop |
| 270 | th_main_6: |
| 271 | setx th_data_6, %g1, %g2 |
| 272 | b th_1to7_join |
| 273 | nop |
| 274 | th_main_7: |
| 275 | setx th_data_7, %g1, %g2 |
| 276 | b th_1to7_join |
| 277 | nop |
| 278 | |
| 279 | th_1to7_join: |
| 280 | set 90, %g3 ! loop 90 times |
| 281 | setx NCU_IOMMU_INVALIDATE_REG_ADDR, %g1, %g4 ! NCU register address |
| 282 | |
| 283 | iommu_invalidate_loop: |
| 284 | ldx [%g2], %g5 ! get an address |
| 285 | stx %g5, [%g4] ! issue an IOMMU INVALIDATE |
| 286 | add %g2, 8, %g2 ! increment data address |
| 287 | |
| 288 | dec %g3 ! decrement counter |
| 289 | brnz %g3, iommu_invalidate_loop ! loop if not zero |
| 290 | nop |
| 291 | |
| 292 | test_passed: |
| 293 | EXIT_GOOD |
| 294 | |
| 295 | test_failed: |
| 296 | EXIT_BAD |
| 297 | /************************************************************************ |
| 298 | Test case data start |
| 299 | ************************************************************************/ |
| 300 | |
| 301 | .align 1024 |
| 302 | .data |
| 303 | user_data_start: |
| 304 | intr_expect: |
| 305 | .byte 0x1 ! expected interrupt count for thread 0 |
| 306 | .byte 0x0 ! expected interrupt count for thread 1 |
| 307 | .byte 0x1 ! expected interrupt count for thread 2 |
| 308 | .byte 0x0 ! expected interrupt count for thread 3 |
| 309 | .byte 0x1 ! expected interrupt count for thread 4 |
| 310 | .byte 0x0 ! expected interrupt count for thread 5 |
| 311 | .byte 0x1 ! expected interrupt count for thread 6 |
| 312 | .byte 0x0 ! expected interrupt count for thread 7 |
| 313 | user_data_end: |
| 314 | |
| 315 | /************************************************************************ |
| 316 | Test case INVALIDATE data start. We don't want any values to match |
| 317 | the IOMMU_TTE_ADDR being used, which is IOMMU_TTE_ADDR + 0x80 |
| 318 | ************************************************************************/ |
| 319 | .align 64 |
| 320 | th_data_1: |
| 321 | init_mem(IOMMU_TTE_ADDR+0x0040, 64, 8, +, 0, +, 0x0004004004004040) |
| 322 | |
| 323 | th_data_2: |
| 324 | init_mem(IOMMU_TTE_ADDR+0x0080, 64, 8, +, 0, +, 0x0000800800808080) |
| 325 | |
| 326 | th_data_3: |
| 327 | init_mem(IOMMU_TTE_ADDR+0x0100, 64, 8, +, 0, +, 0x0000100100101101) |
| 328 | |
| 329 | th_data_4: |
| 330 | init_mem(IOMMU_TTE_ADDR+0x0200, 64, 8, +, 0, +, 0x0002020202020202) |
| 331 | |
| 332 | th_data_5: |
| 333 | init_mem(IOMMU_TTE_ADDR+0x0800, 64, 8, +, 0, +, 0x0004040404040404) |
| 334 | |
| 335 | th_data_6: |
| 336 | init_mem(IOMMU_TTE_ADDR+0x1000, 64, 8, +, 0, +, 0x0008080808080808) |
| 337 | |
| 338 | th_data_7: |
| 339 | init_mem(IOMMU_TTE_ADDR+0x2000, 64, 8, +, 0, +, 0x0001010101001010) |
| 340 | |
| 341 | |
| 342 | |
| 343 | /************************************************************************ |
| 344 | Test case DMA data start. |
| 345 | ************************************************************************/ |
| 346 | |
| 347 | SECTION .DATA DATA_VA=DMA_DATA_ADDR |
| 348 | attr_data { |
| 349 | Name = .DATA, |
| 350 | hypervisor, |
| 351 | compressimage |
| 352 | } |
| 353 | .data |
| 354 | init_mem(0x0101010201030104, 8, 8, +, 0, +, 0x0004000400040004) |
| 355 | .skip 0x10000 - 64 |
| 356 | init_mem(0x0201020202030204, 8, 8, +, 0, +, 0x0004000400040004) |
| 357 | .skip 0x10000 - 64 |
| 358 | init_mem(0x0301030203030304, 8, 8, +, 0, +, 0x0004000400040004) |
| 359 | .skip 0x10000 - 64 |
| 360 | init_mem(0x0401040204030404, 8, 8, +, 0, +, 0x0004000400040004) |
| 361 | .skip 0x10000 - 64 |
| 362 | init_mem(0x0501050205030504, 8, 8, +, 0, +, 0x0004000400040004) |
| 363 | .skip 0x10000 - 64 |
| 364 | init_mem(0x0601060206030604, 8, 8, +, 0, +, 0x0004000400040004) |
| 365 | .skip 0x10000 - 64 |
| 366 | init_mem(0x0701070207030704, 8, 8, +, 0, +, 0x0004000400040004) |
| 367 | |
| 368 | .skip 0x10000 - 64 |
| 369 | !! test expects this to be zero until DMA writes it |
| 370 | init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000) |
| 371 | |
| 372 | .skip 0x10000 - 64 |
| 373 | !! test expects this to be zero until DMA writes it |
| 374 | init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000) |
| 375 | |
| 376 | |
| 377 | |
| 378 | /************************************************************************ |
| 379 | IOMMU TTE start |
| 380 | TTE Format: |
| 381 | 63: 48 DEV KEY - set to 0 |
| 382 | 47: 39 reserved - set to 0 |
| 383 | 38: 13 DATA PA - set to VA for VA=RA |
| 384 | 12: 7 DATA_SOFT - set to 0 |
| 385 | 6: 5 reserved - set to 0 |
| 386 | 5: 3 FNM MASK - set to 0 |
| 387 | 2: 2 KEY VALID - set to 0 |
| 388 | 1: 1 DATA_W - set to 1 |
| 389 | 0: 0 DATA_V - set to 1 |
| 390 | ************************************************************************/ |
| 391 | |
| 392 | SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR |
| 393 | attr_data { |
| 394 | Name = .DATA2, |
| 395 | hypervisor, |
| 396 | compressimage |
| 397 | } |
| 398 | |
| 399 | .data |
| 400 | .skip 8*0x80 |
| 401 | |
| 402 | !!! we only need 8+1 TTEs for this test |
| 403 | iommu_tte_addr: |
| 404 | init_mem(0x0000000000800003, 9, 8, +, 0, +, 0x0000000000010000) |
| 405 | |
| 406 | /************************************************************************/ |
| 407 | |
| 408 | SECTION .HTRAPS |
| 409 | .data |
| 410 | .global intr_count |
| 411 | intr_count: |
| 412 | .byte 0x0 ! interrupt count for thread 0 |
| 413 | .byte 0x0 ! interrupt count for thread 1 |
| 414 | .byte 0x0 ! interrupt count for thread 2 |
| 415 | .byte 0x0 ! interrupt count for thread 3 |
| 416 | .byte 0x0 ! interrupt count for thread 4 |
| 417 | .byte 0x0 ! interrupt count for thread 5 |
| 418 | .byte 0x0 ! interrupt count for thread 6 |
| 419 | .byte 0x0 ! interrupt count for thread 7 |
| 420 | |
| 421 | .end |
| 422 | |
| 423 | /************************************************************************/ |