* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: PCIeIommu4UBypTrInv.s
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
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* ========== Copyright Header End ============================================
#define ENABLE_PCIE_LINK_TRAINING
#define MAIN_PAGE_HV_ALSO
#define ENABLE_INTR0x60 1
#define INTR0x60_MONDO_IV 63
#define INTR0x60_MONDO_20_V 1
#define INTR0x60_MONDO_20_THREAD 0
#define INTR0x60_MONDO_20_CNTRL 0
#define INTR0x60_INTA_EXTRA_HANDLER \
setx intr_count, %g4, %g3; \
#include "interrupt0x60_defines.h"
#include "interrupt0x60_handler.s"
#define MEM32_WR_ADDR mpeval(N2_PCIE_BASE_ADDR + MEM32_OFFSET_BASE_REG_DATA)
#define DMA_DATA_ADDR 0x00800000
#define IOMMU_TTE_ADDR 0x40000000
! Bit 8 = Page Size: 0=8KB, 1=64KB; Bits 3:0 = TSB Table size: 6=64k entries
#define MMU_TSB_CNTRL_REG_DATA mpeval(IOMMU_TTE_ADDR | 0x100 | 6)
#define NCU_IOMMU_INVALIDATE_REG_ADDR 0x8000002030
/************************************************************************
************************************************************************/
! enable interrupts & provide basic handler
!#include "piu_rupt_enable.s"
! enable SUN4U translation in the IOMMU
setx FIRE_DLC_MMU_CSR_A_CTL_ADDR, %g1, %g2
setx 0x00301, %g1, %g3 ! 9:8 11 = Cache enabled, 0: 1 = translation enabled
! load address of the TSB table, and the page size (64KB)
setx FIRE_DLC_MMU_CSR_A_TSB_ADDR, %g1, %g2
setx MMU_TSB_CNTRL_REG_DATA, %g1, %g3
! Trigger some DMA Reads that will create IOMMU tlb entries
#define DMA_ADDR_1 mpeval(0x00800000,16,16)
! $EV trig_pc_d(1,@VA(.MAIN.DMA1)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1)
#define DMA_ADDR_2 mpeval(0x00810000,16,16)
! $EV trig_pc_d(1,@VA(.MAIN.DMA2)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1)
#define DMA_ADDR_3 mpeval(0x00820000,16,16)
! $EV trig_pc_d(1,@VA(.MAIN.DMA3)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1)
#define DMA_ADDR_4 mpeval(0x00830000,16,16)
! $EV trig_pc_d(1,@VA(.MAIN.DMA4)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1)
#define DMA_ADDR_5 mpeval(0x00840000,16,16)
! $EV trig_pc_d(1,@VA(.MAIN.DMA5)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1)
#define DMA_ADDR_6 mpeval(0x00850000,16,16)
! $EV trig_pc_d(1,@VA(.MAIN.DMA6)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1)
#define DMA_ADDR_7 mpeval(0x00860000,16,16)
! $EV trig_pc_d(1,@VA(.MAIN.DMA7)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1)
#define DMA_ADDR_8 mpeval(0x00870000,16,16)
#define DMA_ADDR_8d mpeval(0x00870000)
! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1)
! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1 )
setx intr_count, %l1, %g3
best_set_reg(0x200, %l1, %g2) ! timeout count
!$EV trig_pc_d(1, @VA(.MAIN.intr_timeout1)) -> printf("ERROR: Timeout waiting for interrupt 1",*,1)
! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT", 1 )
! the last DMA should be complete
setx DMA_ADDR_8d, %g1, %g2 ! DMA tgt address
ldx [%g2], %g5 ! get the last dma data area
brnz %g5, invalidate_the_TTE_in_memory
! now clear the VALID bit of the TTEs in memory
invalidate_the_TTE_in_memory:
!setx iommu_tte_addr, %g1, %g2 ! TTE address
setx mpeval(IOMMU_TTE_ADDR+(8*0x80)), %g1, %g2 ! get the TTE address
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
add %g2, 8, %g2 ! address of next TTE
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
add %g2, 8, %g2 ! address of next TTE
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
add %g2, 8, %g2 ! address of next TTE
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
add %g2, 8, %g2 ! address of next TTE
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
add %g2, 8, %g2 ! address of next TTE
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
add %g2, 8, %g2 ! address of next TTE
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
add %g2, 8, %g2 ! address of next TTE
stb %g0, [%g2 + 7] ! clear the last byte of the TTE
! now do some more DMAs using the same TTEs
DMA65: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA65) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_1, DMA_ADDR_1, "64'h40",1)
DMA66: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA66) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_2, DMA_ADDR_2, "64'h40",1)
DMA67: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA67) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_3, DMA_ADDR_3, "64'h40",1)
DMA68: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA68) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_4, DMA_ADDR_4, "64'h40",1)
DMA69: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA69) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_5, DMA_ADDR_5, "64'h40",1)
DMA70: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA70) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_6, DMA_ADDR_6, "64'h40",1)
DMA71: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA71) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_7, DMA_ADDR_7, "64'h40",1)
DMA72: nop ! $EV trig_pc_d(1,@VA(.MAIN.DMA72) -> EnablePCIeIgCmd("DMARD", DMA_ADDR_8, DMA_ADDR_8, "64'h40",1)
#define DMA_ADDR_9 mpeval(0x00880000,16,16)
#define DMA_ADDR_9d mpeval(0x00880000)
! $EV trig_pc_d(1,@VA(.MAIN.DMA8)) -> EnablePCIeIgCmd("DMAWR", DMA_ADDR_9, DMA_ADDR_9, "64'h40",1)
! $EV trig_pc_d(1, @VA(.MAIN.INTA_ASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "ASSERT", 1)
setx intr_count, %l1, %g3
best_set_reg(0x200, %l1, %g2) ! timeout count
!$EV trig_pc_d(1, @VA(.MAIN.intr_timeout2)) -> printf("ERROR: Timeout waiting for interrupt 2",*,1)
! $EV trig_pc_d(1, @VA(.MAIN.INTA_DEASSERT_Evnt2)) -> EnablePCIeIgCmd ("INTA", 0, 0, "DEASSERT",1 )
! the last DMA should be complete
setx DMA_ADDR_9d, %g1, %g2 ! DMA tgt address
ldx [%g2], %g5 ! get the last dma data area
/************************************************************************
Threads 1 - 7 will issue the IOMMU INVALIDATES
************************************************************************/
set 90, %g3 ! loop 90 times
setx NCU_IOMMU_INVALIDATE_REG_ADDR, %g1, %g4 ! NCU register address
ldx [%g2], %g5 ! get an address
stx %g5, [%g4] ! issue an IOMMU INVALIDATE
add %g2, 8, %g2 ! increment data address
dec %g3 ! decrement counter
brnz %g3, iommu_invalidate_loop ! loop if not zero
/************************************************************************
************************************************************************/
.byte 0x1 ! expected interrupt count for thread 0
.byte 0x0 ! expected interrupt count for thread 1
.byte 0x1 ! expected interrupt count for thread 2
.byte 0x0 ! expected interrupt count for thread 3
.byte 0x1 ! expected interrupt count for thread 4
.byte 0x0 ! expected interrupt count for thread 5
.byte 0x1 ! expected interrupt count for thread 6
.byte 0x0 ! expected interrupt count for thread 7
/************************************************************************
Test case INVALIDATE data start. We don't want any values to match
the IOMMU_TTE_ADDR being used, which is IOMMU_TTE_ADDR + 0x80
************************************************************************/
init_mem(IOMMU_TTE_ADDR+0x0040, 64, 8, +, 0, +, 0x0004004004004040)
init_mem(IOMMU_TTE_ADDR+0x0080, 64, 8, +, 0, +, 0x0000800800808080)
init_mem(IOMMU_TTE_ADDR+0x0100, 64, 8, +, 0, +, 0x0000100100101101)
init_mem(IOMMU_TTE_ADDR+0x0200, 64, 8, +, 0, +, 0x0002020202020202)
init_mem(IOMMU_TTE_ADDR+0x0800, 64, 8, +, 0, +, 0x0004040404040404)
init_mem(IOMMU_TTE_ADDR+0x1000, 64, 8, +, 0, +, 0x0008080808080808)
init_mem(IOMMU_TTE_ADDR+0x2000, 64, 8, +, 0, +, 0x0001010101001010)
/************************************************************************
Test case DMA data start.
************************************************************************/
SECTION .DATA DATA_VA=DMA_DATA_ADDR
init_mem(0x0101010201030104, 8, 8, +, 0, +, 0x0004000400040004)
init_mem(0x0201020202030204, 8, 8, +, 0, +, 0x0004000400040004)
init_mem(0x0301030203030304, 8, 8, +, 0, +, 0x0004000400040004)
init_mem(0x0401040204030404, 8, 8, +, 0, +, 0x0004000400040004)
init_mem(0x0501050205030504, 8, 8, +, 0, +, 0x0004000400040004)
init_mem(0x0601060206030604, 8, 8, +, 0, +, 0x0004000400040004)
init_mem(0x0701070207030704, 8, 8, +, 0, +, 0x0004000400040004)
!! test expects this to be zero until DMA writes it
init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000)
!! test expects this to be zero until DMA writes it
init_mem(0x0000000000000000, 8, 8, +, 0, +, 0x0000000000000000)
/************************************************************************
63: 48 DEV KEY - set to 0
47: 39 reserved - set to 0
38: 13 DATA PA - set to VA for VA=RA
12: 7 DATA_SOFT - set to 0
2: 2 KEY VALID - set to 0
************************************************************************/
SECTION .DATA2 DATA_VA=IOMMU_TTE_ADDR
!!! we only need 8+1 TTEs for this test
init_mem(0x0000000000800003, 9, 8, +, 0, +, 0x0000000000010000)
/************************************************************************/
.byte 0x0 ! interrupt count for thread 0
.byte 0x0 ! interrupt count for thread 1
.byte 0x0 ! interrupt count for thread 2
.byte 0x0 ! interrupt count for thread 3
.byte 0x0 ! interrupt count for thread 4
.byte 0x0 ! interrupt count for thread 5
.byte 0x0 ! interrupt count for thread 6
.byte 0x0 ! interrupt count for thread 7
/************************************************************************/