| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: core_qual_pm.diaglist |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | <sys(core_qual_pm) name=sys(core_qual_pm)> |
| 36 | <sys(pm_all)> |
| 37 | |
| 38 | //Core0_2bank |
| 39 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff> |
| 40 | |
| 41 | //FAILS OOB |
| 42 | //<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS > |
| 43 | //e2_st_atomic_8t8b_core0_2bank n2_st_atomic_8t8b.s |
| 44 | //</runargs> |
| 45 | |
| 46 | <runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS> |
| 47 | mpgen_dynamic_caches_core0_2bank mpgen_dynamic_caches.s |
| 48 | mpgen_dynamic_pwr_mgmt_core0_2bank mpgen_dynamic_pwr_mgmt.s |
| 49 | mpgen_tso_all_banks_core0_2bank mpgen_tso_all_banks.s |
| 50 | mpgen_tso_ba_one_bank_core0_2bank mpgen_tso_ba_one_bank.s |
| 51 | mpgen_tso_ba_all_banks_core0_2bank mpgen_tso_ba_all_banks.s |
| 52 | mpgen_tso_atomic_all_banks_core0_2bank mpgen_tso_atomic_all_banks.s |
| 53 | </runargs> |
| 54 | |
| 55 | <runargs -vcs_run_args=+8_FBDIMMS> |
| 56 | tlu_fcrand05_ind_14_core0_2bank tlu_fcrand05_ind_14.s |
| 57 | //FAILS OOB |
| 58 | //fcrand05_rand_88_core0_2bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 |
| 59 | //FAILS OOB |
| 60 | //fcrand05_rand_4_core0_2bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 |
| 61 | </runargs> |
| 62 | |
| 63 | </runargs> |
| 64 | |
| 65 | //Core0_4bank |
| 66 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff> |
| 67 | |
| 68 | <runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS > |
| 69 | n2_st_atomic_8t8b_core0_4bank n2_st_atomic_8t8b.s |
| 70 | </runargs> |
| 71 | |
| 72 | <runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS> |
| 73 | mpgen_dynamic_caches_core0_4bank mpgen_dynamic_caches.s |
| 74 | mpgen_dynamic_pwr_mgmt_core0_4bank mpgen_dynamic_pwr_mgmt.s |
| 75 | mpgen_tso_all_banks_core0_4bank mpgen_tso_all_banks.s |
| 76 | mpgen_tso_ba_one_bank_core0_4bank mpgen_tso_ba_one_bank.s |
| 77 | mpgen_tso_ba_all_banks_core0_4bank mpgen_tso_ba_all_banks.s |
| 78 | mpgen_tso_atomic_all_banks_core0_4bank mpgen_tso_atomic_all_banks.s |
| 79 | </runargs> |
| 80 | |
| 81 | <runargs -vcs_run_args=+8_FBDIMMS> |
| 82 | //FAILS TIMEOUT |
| 83 | //tlu_fcrand05_ind_14_core0_4bank tlu_fcrand05_ind_14.s |
| 84 | //FAILS OOB |
| 85 | //fcrand05_rand_88_core0_4bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 |
| 86 | //FAILS ESR |
| 87 | //fcrand05_rand_4_core0_4bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 |
| 88 | </runargs> |
| 89 | |
| 90 | </runargs> |
| 91 | |
| 92 | //Core1_2bank |
| 93 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00> |
| 94 | |
| 95 | //FAILS OOB |
| 96 | //<runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DCREGS_LSU_CTL_REG_DC=0 -midas_args=-DCREGS_LSU_CTL_REG_IC=0 -midas_args=-DPORTABLE_CORE -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS > |
| 97 | //n2_st_atomic_8t8b_core1_2bank n2_st_atomic_8t8b.s |
| 98 | //</runargs> |
| 99 | |
| 100 | <runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS> |
| 101 | mpgen_dynamic_caches_core1_2bank mpgen_dynamic_caches.s |
| 102 | mpgen_dynamic_pwr_mgmt_core1_2bank mpgen_dynamic_pwr_mgmt.s |
| 103 | mpgen_tso_all_banks_core1_2bank mpgen_tso_all_banks.s |
| 104 | mpgen_tso_ba_one_bank_core1_2bank mpgen_tso_ba_one_bank.s |
| 105 | mpgen_tso_ba_all_banks_core1_2bank mpgen_tso_ba_all_banks.s |
| 106 | mpgen_tso_atomic_all_banks_core1_2bank mpgen_tso_atomic_all_banks.s |
| 107 | </runargs> |
| 108 | |
| 109 | <runargs -vcs_run_args=+8_FBDIMMS> |
| 110 | tlu_fcrand05_ind_14_core1_2bank tlu_fcrand05_ind_14.s |
| 111 | //FAILS OOB |
| 112 | //fcrand05_rand_88_core1_2bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 |
| 113 | //FAILS ESR |
| 114 | //fcrand05_rand_4_core1_2bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 |
| 115 | </runargs> |
| 116 | |
| 117 | </runargs> |
| 118 | |
| 119 | //Core1_4bank |
| 120 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x00000000000000ff -finish_mask=00000000000000ff> |
| 121 | |
| 122 | <runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS > |
| 123 | n2_st_atomic_8t8b_core1_4bank n2_st_atomic_64t.s |
| 124 | </runargs> |
| 125 | |
| 126 | <runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS> |
| 127 | mpgen_dynamic_caches_core1_4bank mpgen_dynamic_caches.s |
| 128 | mpgen_dynamic_pwr_mgmt_core1_4bank mpgen_dynamic_pwr_mgmt.s |
| 129 | mpgen_tso_all_banks_core1_4bank mpgen_tso_all_banks.s |
| 130 | mpgen_tso_ba_one_bank_core1_4bank mpgen_tso_ba_one_bank.s |
| 131 | mpgen_tso_ba_all_banks_core1_4bank mpgen_tso_ba_all_banks.s |
| 132 | mpgen_tso_atomic_all_banks_core1_4bank mpgen_tso_atomic_all_banks.s |
| 133 | </runargs> |
| 134 | |
| 135 | <runargs -vcs_run_args=+8_FBDIMMS> |
| 136 | tlu_fcrand05_ind_14_core1_4bank tlu_fcrand05_ind_14.s |
| 137 | //FAILS OOB |
| 138 | //fcrand05_rand_88_core1_4bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 |
| 139 | //FAILS ESR |
| 140 | //fcrand05_rand_4_core1_4bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 |
| 141 | </runargs> |
| 142 | |
| 143 | </runargs> |
| 144 | |
| 145 | //Core1_8bank |
| 146 | <runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0x000000000000ff00 -finish_mask=000000000000ff00 > |
| 147 | |
| 148 | <runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS > |
| 149 | n2_st_atomic_8t8b_core1_8bank n2_st_atomic_64t.s |
| 150 | </runargs> |
| 151 | |
| 152 | <runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS> |
| 153 | mpgen_dynamic_caches_core1_8bank mpgen_dynamic_caches.s |
| 154 | mpgen_dynamic_pwr_mgmt_core1_8bank mpgen_dynamic_pwr_mgmt.s |
| 155 | mpgen_tso_all_banks_core1_8bank mpgen_tso_all_banks.s |
| 156 | mpgen_tso_ba_one_bank_core1_8bank mpgen_tso_ba_one_bank.s |
| 157 | mpgen_tso_ba_all_banks_core1_8bank mpgen_tso_ba_all_banks.s |
| 158 | mpgen_tso_atomic_all_banks_core1_8bank mpgen_tso_atomic_all_banks.s |
| 159 | </runargs> |
| 160 | |
| 161 | <runargs -vcs_run_args=+8_FBDIMMS -vcs_run_args=+gchkr_off > |
| 162 | tlu_fcrand05_ind_14_core1_8bank tlu_fcrand05_ind_14.s |
| 163 | //FAILS OOB |
| 164 | //fcrand05_rand_88_core1_8bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 |
| 165 | //FAILS ESR |
| 166 | //fcrand05_rand_4_core1_8bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 |
| 167 | </runargs> |
| 168 | |
| 169 | </runargs> |
| 170 | |
| 171 | //Core1257_4bank |
| 172 | <runargs -vcs_run_args=+core_set_mask=a6 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00ff0000ffff00 -finish_mask=ff00ff0000ffff00> |
| 173 | |
| 174 | <runargs -fast_boot -midas_args=-allow_tsb_conflicts -vcs_run_args=+show_delta -max_cycle=+3000000 -vcs_run_args=+TIMEOUT=10000 -midas_args=-DPART_0_BASE=0x200000000 -vcs_run_args=+8_FBDIMMS > |
| 175 | n2_st_atomic_8t8b_core1257_4bank n2_st_atomic_64t.s |
| 176 | </runargs> |
| 177 | |
| 178 | <runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+8_FBDIMMS> |
| 179 | //UNFINISHED |
| 180 | //mpgen_dynamic_caches_core1257_4bank mpgen_dynamic_caches.s |
| 181 | //mpgen_dynamic_pwr_mgmt_core1257_4bank mpgen_dynamic_pwr_mgmt.s |
| 182 | mpgen_tso_all_banks_core1257_4bank mpgen_tso_all_banks.s |
| 183 | //mpgen_tso_ba_one_bank_core1257_4bank mpgen_tso_ba_one_bank.s |
| 184 | mpgen_tso_ba_all_banks_core1257_4bank mpgen_tso_ba_all_banks.s |
| 185 | mpgen_tso_atomic_all_banks_core1257_4bank mpgen_tso_atomic_all_banks.s |
| 186 | </runargs> |
| 187 | |
| 188 | <runargs -vcs_run_args=+8_FBDIMMS> |
| 189 | tlu_fcrand05_ind_14_core1257_4bank tlu_fcrand05_ind_14.s |
| 190 | //FAILS OOB |
| 191 | //fcrand05_rand_88_core1257_4bank fcrand05_rand_88.s -midas_args=-DMULTIPASS=1 |
| 192 | //FAILS ESR |
| 193 | //fcrand05_rand_4_core1257_4bank fcrand05_rand_4.s -midas_args=-DMULTIPASS=1 |
| 194 | </runargs> |
| 195 | |
| 196 | </runargs> |
| 197 | |
| 198 | </sys(pm_all)> |
| 199 | </sys(core_qual_pm)> |