| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pm_mcu.diaglist |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | <sys(mcu_pm) name=sys(mcu_pm)> |
| 36 | <sys(pm_all)> |
| 37 | |
| 38 | <sys(pm_mcu)> |
| 39 | |
| 40 | <runargs -midas_args=-allow_tsb_conflicts -vcs_run_args=+TIMEOUT=10000 -vcs_run_args=+8_FBDIMMS -midas_args=-DSYNC_THREADS -vcs_run_args=+mon+mcu_fmon=1=1 -vcs_run_args=+debug -vcs_run_args=+gchkr_off> |
| 41 | |
| 42 | |
| 43 | //Core0_2bank |
| 44 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -vcs_run_args=+STACK_DIMM> |
| 45 | n2_pm_mcu_cmda_Core0_2Bank n2_pm_mcu_cmda_2bank.s |
| 46 | </runargs> |
| 47 | |
| 48 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff > |
| 49 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 50 | |
| 51 | n2_pm_mcu_all_th_wr_Core0_2bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0 |
| 52 | n2_pm_mcu_all_th_rd_Core0_2bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0 |
| 53 | n2_pm_mcu_all_th_wrrd_Core0_2bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0 |
| 54 | n2_pm_mcu_diff_th_wr_rd_Core0_2bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0 |
| 55 | |
| 56 | n2_pm_mcu_all_th_wr_Core0_2bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1 |
| 57 | n2_pm_mcu_all_th_rd_Core0_2bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1 |
| 58 | n2_pm_mcu_all_th_wrrd_Core0_2bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1 |
| 59 | n2_pm_mcu_diff_th_wr_rd_Core0_2bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1 |
| 60 | |
| 61 | n2_pm_all_dimm_Core0_2bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK0 |
| 62 | n2_pm_all_dimm_Core0_2bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK1 |
| 63 | |
| 64 | n2_pm_all_dimm_rdwr_Core0_2bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK0 |
| 65 | n2_pm_all_dimm_rdwr_Core0_2bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK1 |
| 66 | |
| 67 | n2_pm_all_dimm_rdwr_2_Core0_2bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK0 |
| 68 | n2_pm_all_dimm_rdwr_2_Core0_2bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK1 |
| 69 | |
| 70 | n2_pm_all_dimm_rdwr_3_Core0_2bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK |
| 71 | n2_pm_all_dimm_rdwr_4_Core0_2bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK |
| 72 | |
| 73 | n2_pm_all_dimm_rdwr_5_Core0_2bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK |
| 74 | n2_pm_all_dimm_rdwr_6_Core0_2bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK |
| 75 | |
| 76 | // fails DBU; n2_mcu_0_all_bcopy_all_banks_Core0_2bank n2_mcu_0_all_bcopy_all_banks.s |
| 77 | </runargs> |
| 78 | |
| 79 | n2_pm_all_dimm_rdwr_3_Core0_2bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK |
| 80 | n2_pm_all_dimm_rdwr_4_Core0_2bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK |
| 81 | |
| 82 | n2_pm_all_dimm_rdwr_5_Core0_2bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK |
| 83 | n2_pm_all_dimm_rdwr_6_Core0_2bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK |
| 84 | </runargs> |
| 85 | |
| 86 | |
| 87 | //Core0_4bank |
| 88 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x01 -finish_mask=01 -vcs_run_args=+STACK_DIMM> |
| 89 | n2_pm_mcu_cmda_Core0_4Bank n2_pm_mcu_cmda_4bank.s |
| 90 | </runargs> |
| 91 | |
| 92 | <runargs -vcs_run_args=+core_set_mask=01 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff -finish_mask=ff > |
| 93 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 94 | n2_pm_mcu_all_th_wr_Core0_4bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0 |
| 95 | n2_pm_mcu_all_th_rd_Core0_4bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0 |
| 96 | n2_pm_mcu_all_th_wrrd_Core0_4bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0 |
| 97 | n2_pm_mcu_diff_th_wr_rd_Core0_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0 |
| 98 | |
| 99 | n2_pm_mcu_all_th_wr_Core0_4bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1 |
| 100 | n2_pm_mcu_all_th_rd_Core0_4bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1 |
| 101 | n2_pm_mcu_all_th_wrrd_Core0_4bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1 |
| 102 | n2_pm_mcu_diff_th_wr_rd_Core0_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1 |
| 103 | |
| 104 | n2_pm_all_dimm_Core0_4bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 105 | n2_pm_all_dimm_Core0_4bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 106 | |
| 107 | n2_pm_all_dimm_rdwr_Core0_4bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 108 | n2_pm_all_dimm_rdwr_Core0_4bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 109 | |
| 110 | n2_pm_all_dimm_rdwr_2_Core0_4bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 111 | n2_pm_all_dimm_rdwr_2_Core0_4bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 112 | |
| 113 | n2_pm_all_dimm_rdwr_5_Core0_4bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK |
| 114 | n2_pm_all_dimm_rdwr_6_Core0_4bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK |
| 115 | |
| 116 | n2_mcu_0_all_bcopy_all_banks_Core0_4bank n2_mcu_0_all_bcopy_all_banks.s |
| 117 | </runargs> |
| 118 | |
| 119 | n2_pm_all_dimm_rdwr_3_Core0_4bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK |
| 120 | n2_pm_all_dimm_rdwr_4_Core0_4bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK |
| 121 | |
| 122 | n2_pm_all_dimm_rdwr_5_Core0_4bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK |
| 123 | n2_pm_all_dimm_rdwr_6_Core0_4bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK |
| 124 | </runargs> |
| 125 | |
| 126 | //Core1_2bank |
| 127 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM> |
| 128 | n2_pm_mcu_cmda_Core1_2Bank n2_pm_mcu_cmda_2bank.s |
| 129 | </runargs> |
| 130 | |
| 131 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=1 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 > |
| 132 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 133 | n2_pm_mcu_all_th_wr_Core1_2bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0 |
| 134 | n2_pm_mcu_all_th_rd_Core1_2bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0 |
| 135 | n2_pm_mcu_all_th_wrrd_Core1_2bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0 |
| 136 | n2_pm_mcu_diff_th_wr_rd_Core1_2bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0 |
| 137 | |
| 138 | n2_pm_mcu_all_th_wr_Core1_2bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1 |
| 139 | n2_pm_mcu_all_th_rd_Core1_2bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1 |
| 140 | n2_pm_mcu_all_th_wrrd_Core1_2bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1 |
| 141 | n2_pm_mcu_diff_th_wr_rd_Core1_2bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1 |
| 142 | |
| 143 | n2_pm_all_dimm_Core1_2bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK0 |
| 144 | n2_pm_all_dimm_Core1_2bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_2BANK -midas_args=-DBANK1 |
| 145 | |
| 146 | n2_pm_all_dimm_rdwr_Core1_2bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK0 |
| 147 | n2_pm_all_dimm_rdwr_Core1_2bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_2BANK -midas_args=-DBANK1 |
| 148 | |
| 149 | n2_pm_all_dimm_rdwr_2_Core1_2bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK0 |
| 150 | n2_pm_all_dimm_rdwr_2_Core1_2bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_2BANK -midas_args=-DBANK1 |
| 151 | |
| 152 | n2_pm_all_dimm_rdwr_3_Core1_2bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK |
| 153 | n2_pm_all_dimm_rdwr_4_Core1_2bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK |
| 154 | |
| 155 | n2_pm_all_dimm_rdwr_5_Core1_2bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK |
| 156 | n2_pm_all_dimm_rdwr_6_Core1_2bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK |
| 157 | |
| 158 | // fails DBU; n2_mcu_0_all_bcopy_all_banks_Core1_2bank n2_mcu_0_all_bcopy_all_banks.s |
| 159 | </runargs> |
| 160 | |
| 161 | n2_pm_all_dimm_rdwr_3_Core1_2bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_2BANK |
| 162 | n2_pm_all_dimm_rdwr_4_Core1_2bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_2BANK |
| 163 | |
| 164 | n2_pm_all_dimm_rdwr_5_Core1_2bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_2BANK |
| 165 | n2_pm_all_dimm_rdwr_6_Core1_2bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_2BANK |
| 166 | </runargs> |
| 167 | |
| 168 | //Core1_4bank |
| 169 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM> |
| 170 | n2_pm_mcu_cmda_Core1_4Bank n2_pm_mcu_cmda_4bank.s |
| 171 | </runargs> |
| 172 | |
| 173 | <runargs -vcs_run_args=+core_set_mask=02 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 > |
| 174 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 175 | n2_pm_mcu_all_th_wr_Core1_4bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0 |
| 176 | n2_pm_mcu_all_th_rd_Core1_4bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0 |
| 177 | n2_pm_mcu_all_th_wrrd_Core1_4bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0 |
| 178 | n2_pm_mcu_diff_th_wr_rd_Core1_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0 |
| 179 | |
| 180 | n2_pm_mcu_all_th_wr_Core1_4bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1 |
| 181 | n2_pm_mcu_all_th_rd_Core1_4bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1 |
| 182 | n2_pm_mcu_all_th_wrrd_Core1_4bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1 |
| 183 | n2_pm_mcu_diff_th_wr_rd_Core1_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1 |
| 184 | |
| 185 | n2_pm_all_dimm_Core1_4bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 186 | n2_pm_all_dimm_Core1_4bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 187 | |
| 188 | n2_pm_all_dimm_rdwr_Core1_4bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 189 | n2_pm_all_dimm_rdwr_Core1_4bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 190 | |
| 191 | n2_pm_all_dimm_rdwr_2_Core1_4bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 192 | n2_pm_all_dimm_rdwr_2_Core1_4bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 193 | |
| 194 | n2_pm_all_dimm_rdwr_3_Core1_4bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK |
| 195 | n2_pm_all_dimm_rdwr_4_Core1_4bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK |
| 196 | |
| 197 | n2_pm_all_dimm_rdwr_5_Core1_4bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK |
| 198 | n2_pm_all_dimm_rdwr_6_Core1_4bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK |
| 199 | |
| 200 | n2_mcu_0_all_bcopy_all_banks_Core1_4bank n2_mcu_0_all_bcopy_all_banks.s |
| 201 | </runargs> |
| 202 | |
| 203 | n2_pm_all_dimm_rdwr_3_Core1_4bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK |
| 204 | n2_pm_all_dimm_rdwr_4_Core1_4bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK |
| 205 | |
| 206 | n2_pm_all_dimm_rdwr_5_Core1_4bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK |
| 207 | n2_pm_all_dimm_rdwr_6_Core1_4bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK |
| 208 | </runargs> |
| 209 | |
| 210 | //Core1_8bank |
| 211 | <runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0x0100 -finish_mask=0100 -vcs_run_args=+STACK_DIMM> |
| 212 | n2_pm_mcu_cmda_Core1_8Bank n2_pm_mcu_cmda_8bank.s |
| 213 | </runargs> |
| 214 | |
| 215 | <runargs -vcs_run_args=+core_set_mask=02 -midas_args=-DCMP_THREAD_START=0xff00 -finish_mask=ff00 -midas_args=-DL2_DIRECT_MAP> |
| 216 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 217 | n2_pm_mcu_all_th_wr_Core1_8bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0 |
| 218 | n2_pm_mcu_all_th_rd_Core1_8bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0 |
| 219 | n2_pm_mcu_all_th_wrrd_Core1_8bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0 |
| 220 | n2_pm_mcu_diff_th_wr_rd_Core1_8bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0 |
| 221 | |
| 222 | |
| 223 | n2_pm_mcu_all_th_wr_Core1_8bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1 |
| 224 | n2_pm_mcu_all_th_rd_Core1_8bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1 |
| 225 | n2_pm_mcu_all_th_wrrd_Core1_8bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1 |
| 226 | n2_pm_mcu_diff_th_wr_rd_Core1_8bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1 |
| 227 | |
| 228 | n2_pm_all_dimm_Core1_8bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_8BANK -midas_args=-DBANK0 |
| 229 | n2_pm_all_dimm_Core1_8bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_8BANK -midas_args=-DBANK1 |
| 230 | |
| 231 | n2_pm_all_dimm_rdwr_Core1_8bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_8BANK -midas_args=-DBANK0 |
| 232 | n2_pm_all_dimm_rdwr_Core1_8bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_8BANK -midas_args=-DBANK1 |
| 233 | |
| 234 | n2_pm_all_dimm_rdwr_2_Core1_8bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_8BANK -midas_args=-DBANK0 |
| 235 | n2_pm_all_dimm_rdwr_2_Core1_8bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_8BANK -midas_args=-DBANK1 |
| 236 | |
| 237 | n2_pm_all_dimm_rdwr_3_Core1_8bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_8BANK |
| 238 | n2_pm_all_dimm_rdwr_4_Core1_8bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_8BANK |
| 239 | |
| 240 | n2_pm_all_dimm_rdwr_5_Core1_8bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_8BANK |
| 241 | n2_pm_all_dimm_rdwr_6_Core1_8bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_8BANK |
| 242 | |
| 243 | |
| 244 | n2_mcu_0_all_bcopy_all_banks_Core1_8bank n2_mcu_0_all_bcopy_all_banks.s |
| 245 | </runargs> |
| 246 | |
| 247 | n2_pm_all_dimm_rdwr_3_Core1_8bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_8BANK |
| 248 | n2_pm_all_dimm_rdwr_4_Core1_8bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_8BANK |
| 249 | |
| 250 | n2_pm_all_dimm_rdwr_5_Core1_8bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_8BANK |
| 251 | n2_pm_all_dimm_rdwr_6_Core1_8bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_8BANK |
| 252 | </runargs> |
| 253 | |
| 254 | //Core1257_4bank |
| 255 | <runargs -vcs_run_args=+core_set_mask=a6 -midas_args=-DCMP_THREAD_START=0x0100010000010100 -finish_mask=0100010000010100 -vcs_run_args=+STACK_DIMM> |
| 256 | n2_pm_mcu_cmda_Core1257_4Bank n2_pm_mcu_cmda_4bank.s |
| 257 | </runargs> |
| 258 | |
| 259 | <runargs -vcs_run_args=+core_set_mask=a6 -vcs_run_args=+bank_set_mask=3 -midas_args=-DCMP_THREAD_START=0xff00ff0000ffff00 -finish_mask=ff00ff0000ffff00 > |
| 260 | <runargs -midas_args=-DL2_DIRECT_MAP> |
| 261 | n2_pm_mcu_all_th_wr_Core1257_4bank_Bank0 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK0 |
| 262 | n2_pm_mcu_all_th_rd_Core1257_4bank_Bank0 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK0 |
| 263 | n2_pm_mcu_all_th_wrrd_Core1257_4bank_Bank0 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK0 |
| 264 | n2_pm_mcu_diff_th_wr_rd_Core1257_4bank_Bank0 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK0 |
| 265 | |
| 266 | n2_pm_mcu_all_th_wr_Core1257_4bank_Bank1 n2_pm_mcu_all_th_wr.s -midas_args=-DBANK1 |
| 267 | n2_pm_mcu_all_th_rd_Core1257_4bank_Bank1 n2_pm_mcu_all_th_rd.s -midas_args=-DBANK1 |
| 268 | n2_pm_mcu_all_th_wrrd_Core1257_4bank_Bank1 n2_pm_mcu_all_th_wrrd.s -midas_args=-DBANK1 |
| 269 | n2_pm_mcu_diff_th_wr_rd_Core1257_4bank_Bank1 n2_pm_mcu_diff_th_wr_rd.s -midas_args=-DBANK1 |
| 270 | |
| 271 | n2_pm_all_dimm_Core1257_4bank_B0 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 272 | n2_pm_all_dimm_Core1257_4bank_B1 n2_pm_all_dimm.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 273 | |
| 274 | n2_pm_all_dimm_rdwr_Core1257_4bank_B0 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 275 | n2_pm_all_dimm_rdwr_Core1257_4bank_B1 n2_pm_all_dimm_rdwr.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 276 | |
| 277 | n2_pm_all_dimm_rdwr_2_Core1257_4bank_B0 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK0 |
| 278 | n2_pm_all_dimm_rdwr_2_Core1257_4bank_B1 n2_pm_all_dimm_rdwr_2.s -midas_args=-DPM_4BANK -midas_args=-DBANK1 |
| 279 | |
| 280 | n2_pm_all_dimm_rdwr_3_Core1257_4bank n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK |
| 281 | n2_pm_all_dimm_rdwr_4_Core1257_4bank n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK |
| 282 | |
| 283 | n2_pm_all_dimm_rdwr_5_Core1257_4bank n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK |
| 284 | n2_pm_all_dimm_rdwr_6_Core1257_4bank n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK |
| 285 | |
| 286 | // long running n2_mcu_0_all_bcopy_all_banks_Core1257_4bank n2_mcu_0_all_bcopy_all_banks.s |
| 287 | </runargs> |
| 288 | |
| 289 | n2_pm_all_dimm_rdwr_3_Core1257_4bank_way n2_pm_all_dimm_rdwr_3.s -midas_args=-DPM_4BANK |
| 290 | n2_pm_all_dimm_rdwr_4_Core1257_4bank_way n2_pm_all_dimm_rdwr_4.s -midas_args=-DPM_4BANK |
| 291 | |
| 292 | n2_pm_all_dimm_rdwr_5_Core1257_4bank_way n2_pm_all_dimm_rdwr_5.s -midas_args=-DPM_4BANK |
| 293 | n2_pm_all_dimm_rdwr_6_Core1257_4bank_way n2_pm_all_dimm_rdwr_6.s -midas_args=-DPM_4BANK |
| 294 | </runargs> |
| 295 | |
| 296 | |
| 297 | |
| 298 | </runargs> |
| 299 | |
| 300 | </sys(pm_mcu)> |
| 301 | |
| 302 | |
| 303 | </sys(pm_all)> |
| 304 | </sys(mcu_pm)> |
| 305 | |