| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: niu_intr_util.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include "niu_intr_memory_map.vri" |
| 36 | #include "niu_gen_pio.vrh" |
| 37 | |
| 38 | #define TIME {get_time(HI), get_time(LO)} |
| 39 | |
| 40 | extern niu_gen_pio gen_pio_drv; |
| 41 | extern Mesg be_msg; |
| 42 | |
| 43 | class niu_intr_util { |
| 44 | |
| 45 | task new() { } |
| 46 | task set_sid_data_function(bit [ 5:0] gn, bit [1:0] fn); |
| 47 | task rearm_arm_bit(bit [ 5:0] gn); |
| 48 | task arm_all_intrs(bit [ 5:0] timer); |
| 49 | |
| 50 | } |
| 51 | |
| 52 | |
| 53 | // This function sets sid_data[6:5] (function number bits) |
| 54 | // for the passed group number |
| 55 | task niu_intr_util :: set_sid_data_function(bit [ 5:0] gn, bit [1:0] fn) { |
| 56 | bit [63:0] wr_data, rd_data; |
| 57 | bit [31:0] addr; |
| 58 | |
| 59 | addr = INTR_SID + 8*gn; |
| 60 | gen_pio_drv.pio_rd(addr, rd_data); |
| 61 | wr_data = {57'h0, fn, rd_data[4:0]}; |
| 62 | gen_pio_drv.pio_wr(addr, wr_data); |
| 63 | printf("%d niu_intr_util :: set_sid_data_function addr = %x wr_data = %x \n",TIME, addr, wr_data); |
| 64 | } |
| 65 | |
| 66 | |
| 67 | // This function polls ARM bit and if it becomes 0 |
| 68 | // it will set it back to 1 for the passed GROUP Number |
| 69 | // |
| 70 | |
| 71 | task niu_intr_util :: rearm_arm_bit(bit [ 5:0] gn){ |
| 72 | bit exit_loop; |
| 73 | bit [63:0] wr_data, rd_data; |
| 74 | bit [31:0] addr; |
| 75 | |
| 76 | wr_data = 64'h0000_0000_8000_0000; // setting ARM bit (31) |
| 77 | addr = PCIE_LDGIMGN + 8192*gn; |
| 78 | exit_loop = 0; |
| 79 | while(~exit_loop) { |
| 80 | gen_pio_drv.pio_rd(addr, rd_data); |
| 81 | if( (rd_data & wr_data) == 0 ) { |
| 82 | printf("%d niu_intr_util :: rearm_arm_bit :: ReArming the Arm bit \n", TIME); |
| 83 | gen_pio_drv.pio_wr(addr, wr_data); |
| 84 | exit_loop = 1; |
| 85 | } |
| 86 | } |
| 87 | } |
| 88 | |
| 89 | // This function assigns each device to unique logic device group number |
| 90 | // Enables Mask0 and Mask1 |
| 91 | // ARMs all interrupts |
| 92 | // Sets timer resolution to 0 |
| 93 | // set the TIMER value to timer |
| 94 | // set SID to unique value starting at 0 |
| 95 | task niu_intr_util :: arm_all_intrs(bit [ 5:0] timer){ |
| 96 | integer i; |
| 97 | bit [63:0] wr_data; |
| 98 | bit [63:0] rd_data; |
| 99 | bit [31:0] addr; |
| 100 | |
| 101 | |
| 102 | for(i = 0; i < 68; i = i+1) { |
| 103 | wr_data = i; |
| 104 | addr = PCIE_LDG_NUM + 8*i; |
| 105 | gen_pio_drv.pio_wr(addr, wr_data); |
| 106 | printf("%d niu_intr_util :: arm_all_intrs LDG_NUM:: addr = %x wr_data = %x \n",TIME, addr, wr_data); |
| 107 | } |
| 108 | |
| 109 | |
| 110 | wr_data = 64'b0; |
| 111 | for(i = 0; i < 64; i = i+1) { |
| 112 | addr = PIO_IMASK0 + 8192*i; |
| 113 | gen_pio_drv.pio_wr(addr, wr_data); |
| 114 | printf("%d niu_intr_util :: arm_all_intrs IMASK0 :: addr = %x wr_data = %x \n",TIME, addr, wr_data); |
| 115 | } |
| 116 | |
| 117 | wr_data = 64'b0; |
| 118 | for(i = 0; i < 5; i = i+1) { |
| 119 | addr = PIO_IMASK1 + 8192*i; |
| 120 | gen_pio_drv.pio_wr(addr, wr_data); |
| 121 | printf("%d niu_intr_util :: arm_all_intrs IMASK1 :: addr = %x wr_data = %x \n",TIME, addr, wr_data); |
| 122 | } |
| 123 | // setting ARM bit (31) for all devices |
| 124 | wr_data = 64'h0000_0000_8000_0000; // setting ARM bit (31) |
| 125 | wr_data = wr_data + timer; |
| 126 | for(i = 0; i < 64; i = i+1) { |
| 127 | addr = PCIE_LDGIMGN + 8192*i; |
| 128 | gen_pio_drv.pio_wr(addr, wr_data); |
| 129 | printf("%d niu_intr_util :: arm_all_intrs ARM :: addr = %x wr_data = %x \n",TIME, addr, wr_data); |
| 130 | } |
| 131 | |
| 132 | for(i = 0; i < 64; i = i+1) { |
| 133 | wr_data = i; |
| 134 | addr = INTR_SID + 8*i; |
| 135 | gen_pio_drv.pio_wr(addr, wr_data); |
| 136 | printf("%d niu_intr_util :: arm_all_intrs SID :: addr = %x wr_data = %x \n",TIME, addr, wr_data); |
| 137 | } |
| 138 | |
| 139 | } |