| 1 | //Common files for encrypted and unencrypted |
| 2 | $DV_ROOT/verif/env/common/verilog/misc/defines.vh |
| 3 | $DV_ROOT/verif/env/common/verilog/misc/dispmonDefines.vh |
| 4 | ilu_peu_top.h |
| 5 | //+incdir++ |
| 6 | //+incdir+. |
| 7 | //+incdir+../common/verilog/checkers |
| 8 | //+incdir+../common/verilog/misc |
| 9 | |
| 10 | +incdir+$DV_ROOT/design/sys/iop/dmu/rtl |
| 11 | // commented this out |
| 12 | //+incdir+$DV_ROOT/design/sys/iop/peu/rtl |
| 13 | //+incdir+$DV_ROOT/design/sys/iop/pcie_common/rtl |
| 14 | //+incdir+$DV_ROOT/design/sys/iop/pcie_common/rtl |
| 15 | |
| 16 | $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie.h |
| 17 | $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_csr_defines.h |
| 18 | |
| 19 | |
| 20 | //ILU |
| 21 | //DMU needed but using -vcs_build_args=+define+NO_DMC+NO_DSN+NO_MB0+NO_CB0 |
| 22 | // so only ILU gets instantiated |
| 23 | // 04/22/04 udevan |
| 24 | // move dmu.v to verif flist so that this files can be reused for FC |
| 25 | // |
| 26 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu.h |
| 27 | // $DV_ROOT/design/sys/iop/dmu/rtl/dmu.v |
| 28 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu.v |
| 29 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_defines.h |
| 30 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en_entry.v |
| 31 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil.v |
| 32 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib.v |
| 33 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err.v |
| 34 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_stage_mux_only.v |
| 35 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_bufmgr.v |
| 36 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_addr_decode.v |
| 37 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_err_entry.v |
| 38 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil.v |
| 39 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_crdtcnt.v |
| 40 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_cim.v |
| 41 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en.v |
| 42 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_bufmgr.v |
| 43 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_parchk.v |
| 44 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr.v |
| 45 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_pec_int_en_entry.v |
| 46 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_datafsm.v |
| 47 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_rcdbldr.v |
| 48 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en.v |
| 49 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_5.v |
| 50 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_rcdbldr.v |
| 51 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_iil_xfrfsm.v |
| 52 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_int_en_entry.v |
| 53 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csrpipe_6.v |
| 54 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_relgen.v |
| 55 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_isb.v |
| 56 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_log_en.v |
| 57 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_default_grp.v |
| 58 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_eil_xfrfsm.v |
| 59 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos_entry.v |
| 60 | $DV_ROOT/design/sys/iop/dmu/rtl/dmu_ilu_cib_csr_ilu_diagnos.v |
| 61 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcb.v |
| 62 | |
| 63 | |
| 64 | //+incdir+$DV_ROOT/design/sys/iop/plp/rtl/ |
| 65 | // commented this out |
| 66 | //$DV_ROOT/design/sys/iop/peu/rtl/peu.h |
| 67 | $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie.h |
| 68 | $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_csr_defines.h |
| 69 | |
| 70 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_dcm_daemon.v |
| 71 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/csr_sw.v |
| 72 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcc.v |
| 73 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq.v |
| 74 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qdp.v |
| 75 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qcp.v |
| 76 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_srq_qci.v |
| 77 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs.v |
| 78 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_ism.v |
| 79 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_osm.v |
| 80 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcs_sdp.v |
| 81 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_dcd.v |
| 82 | -v $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_frr_arbiter.v |
| 83 | // AT-: $DV_ROOT/design/sys/iop/pcie_common/rtl/lbist_rst_cct.v |
| 84 | // $DV_ROOT/design/sys/iop/pcie_common/rtl/pcie_common_sync_flop.v |
| 85 | |
| 86 | //Generic clock modules |
| 87 | -v $DV_ROOT/libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v |
| 88 | -v $DV_ROOT/libs/clk/n2_clk_clstr_hdr2_cust_l/n2_clk_clstr_hdr2_cust/rtl/n2_clk_clstr_hdr2_cust.v |
| 89 | |
| 90 | |
| 91 | //Added for the real clocks for DMU |
| 92 | -v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_dmu_io_cust/rtl/n2_clk_dmu_io_cust.v |
| 93 | -v $DV_ROOT/libs/clk/rtl/clkgen_dmu_io.v |
| 94 | |
| 95 | // AT: PEU Clk Gen modules |
| 96 | //-v $DV_ROOT/libs/clk/rtl/clkgen_peu_io.v |
| 97 | //-v $DV_ROOT/libs/clk/rtl/clkgen_peu_pc.v |
| 98 | //-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_peu_io_cust/rtl/n2_clk_peu_io_cust.v |
| 99 | //-v $DV_ROOT/libs/clk/n2_clk_pgrid_cust_l/n2_clk_peu_pc_cust/rtl/n2_clk_peu_pc_cust.v |
| 100 | |
| 101 | |
| 102 | //End Common rtl |
| 103 | |