| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mac_reset_port.vri |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #define OUTPUT_EDGE PHOLD |
| 36 | #define INPUT_EDGE PSAMPLE |
| 37 | #define OUTPUT_SKEW #1 |
| 38 | |
| 39 | |
| 40 | interface top_level_iface { |
| 41 | input core_clock CLOCK verilog_node |
| 42 | MAC_DUV_PATH.ht_top.core_clk"; |
| 43 | |
| 44 | output reset_l OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 45 | MAC_DUV_PATH.reset_l"; |
| 46 | } |
| 47 | |
| 48 | |
| 49 | /**** |
| 50 | |
| 51 | output reset_core OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 52 | MAC_DUV_PATH.ht_top.reset_core"; |
| 53 | |
| 54 | output pio_rd_wr OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 55 | MAC_DUV_PATH.ht_top.pio_rd_wr"; |
| 56 | |
| 57 | output [8:0] pio_reg_offset OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 58 | MAC_DUV_PATH.ht_top.pio_reg_offset"; |
| 59 | |
| 60 | output [31:0] pio_wr_data OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 61 | MAC_DUV_PATH.ht_top.pio_wr_data"; |
| 62 | |
| 63 | output [2:0] bif_pio_rd_mux_sel OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 64 | MAC_DUV_PATH.ht_top.bif_pio_rd_mux_sel"; |
| 65 | |
| 66 | |
| 67 | output bif_mac0_core_sel OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 68 | MAC_DUV_PATH.ht_top.bif_mac0_core_sel"; |
| 69 | |
| 70 | output bif_mac1_core_sel OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 71 | MAC_DUV_PATH.ht_top.bif_mac1_core_sel"; |
| 72 | |
| 73 | output bif_mac2_core_sel OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 74 | MAC_DUV_PATH.ht_top.bif_mac2_core_sel"; |
| 75 | |
| 76 | output bif_mac3_core_sel OUTPUT_EDGE OUTPUT_SKEW verilog_node |
| 77 | MAC_DUV_PATH.ht_top.bif_mac3_core_sel"; |
| 78 | |
| 79 | ***********/ |