| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: mbox_defines.vri |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #define IAM_MAC_IPP_CHKR 8'h00 |
| 36 | #define IAM_IPP_DMC_CHKR 8'h01 |
| 37 | #define IAM_NTX_MAC_CHKR 8'h02 |
| 38 | #define IAM_RDMC_WR_CHKR 8'h03 |
| 39 | |
| 40 | // FFLP |
| 41 | #define IAM_FFLP_CAM_MBOX 8'h10 |
| 42 | #define IAM_CAM_RAM_MBOX 8'h11 |
| 43 | #define IAM_RAM_IPP_MBOX 8'h12 |
| 44 | #define IAM_RAM_BMC_MBOX 8'h13 |
| 45 | #define IAM_BMC_CAM_RAM_MBOX 8'h14 |
| 46 | #define IAM_FFLP_IPP_MBOX 8'h15 |
| 47 | #define IAM_RAM_CAM_MBOX 8'h16 |
| 48 | #define IAM_FFLP_CAM_V4_MBOX 8'h17 |
| 49 | #define IAM_FFLP_CAM_V6_MBOX 8'h18 |
| 50 | |
| 51 | // IPP |
| 52 | #define IAM_PG_IPP_MBOX 8'h20 |
| 53 | #define IAM_IPP_FFL_MBOX 8'h21 |
| 54 | |
| 55 | |
| 56 | //IPP |
| 57 | |
| 58 | #define IAM_NRX_FFL_CHK_MBOX 8'h80 |
| 59 | |
| 60 | //TX DMA |
| 61 | |
| 62 | #define IAM_TXC_DMA0_MBOX 8'h90 |
| 63 | #define IAM_TXC_DMA1_MBOX 8'h91 |
| 64 | #define IAM_TXC_DMA2_MBOX 8'h92 |
| 65 | #define IAM_TXC_DMA3_MBOX 8'h93 |
| 66 | #define IAM_TXC_DMA4_MBOX 8'h94 |
| 67 | #define IAM_TXC_DMA5_MBOX 8'h95 |
| 68 | #define IAM_TXC_DMA6_MBOX 8'h96 |
| 69 | #define IAM_TXC_DMA7_MBOX 8'h97 |
| 70 | #define IAM_TXC_DMA8_MBOX 8'h98 |
| 71 | #define IAM_TXC_DMA9_MBOX 8'h99 |
| 72 | #define IAM_TXC_DMA10_MBOX 8'h9a |
| 73 | #define IAM_TXC_DMA11_MBOX 8'h9b |
| 74 | #define IAM_TXC_DMA12_MBOX 8'h9c |
| 75 | #define IAM_TXC_DMA13_MBOX 8'h9d |
| 76 | #define IAM_TXC_DMA14_MBOX 8'h9e |
| 77 | #define IAM_TXC_DMA15_MBOX 8'h9f |
| 78 | #define IAM_TXC_DMA16_MBOX 8'ha0 |
| 79 | #define IAM_TXC_DMA17_MBOX 8'ha1 |
| 80 | #define IAM_TXC_DMA18_MBOX 8'ha2 |
| 81 | #define IAM_TXC_DMA19_MBOX 8'ha3 |
| 82 | #define IAM_TXC_DMA20_MBOX 8'ha4 |
| 83 | #define IAM_TXC_DMA21_MBOX 8'ha5 |
| 84 | #define IAM_TXC_DMA22_MBOX 8'ha6 |
| 85 | #define IAM_TXC_DMA23_MBOX 8'ha7 |
| 86 | #define IAM_TXC_DMA24_MBOX 8'ha8 |
| 87 | #define IAM_TXC_DMA25_MBOX 8'ha9 |
| 88 | #define IAM_TXC_DMA26_MBOX 8'haa |
| 89 | #define IAM_TXC_DMA27_MBOX 8'hab |
| 90 | #define IAM_TXC_DMA28_MBOX 8'hac |
| 91 | #define IAM_TXC_DMA29_MBOX 8'had |
| 92 | #define IAM_TXC_DMA30_MBOX 8'hae |
| 93 | #define IAM_TXC_DMA31_MBOX 8'haf |