| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: siu_chk_ports.vri |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include "neptune_defines.vri" |
| 36 | /* |
| 37 | |
| 38 | Port defines for SIU Stub interface to NIU for checkers |
| 39 | |
| 40 | |
| 41 | */ |
| 42 | |
| 43 | |
| 44 | #define OUTPUT_EDGE PHOLD |
| 45 | #define INPUT_EDGE PSAMPLE #-1 |
| 46 | #define OUTPUT_SKEW #1 |
| 47 | |
| 48 | #ifdef NIU_GATE |
| 49 | |
| 50 | interface niu_siu_chk { |
| 51 | |
| 52 | input clk CLOCK verilog_node TDS_DUV_PATH.iol2clk"; |
| 53 | |
| 54 | input niu_sii_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_hdr_vld"; // Ethernet requesting to send packet to SIU |
| 55 | input niu_sii_reqbypass INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_reqbypass"; // Ethernet requesting to send packet to bypass queue of SIU |
| 56 | |
| 57 | input niu_sii_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_datareq"; // Ethernet requesting to send packet w/data to SIU |
| 58 | input [127:0] niu_sii_data INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_data"; // Packet from Ethernet to SIU |
| 59 | input [7:0] niu_sii_parity INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_parity"; // Packet parity from Ethernet to SIU |
| 60 | |
| 61 | input niu_reset_l INPUT_EDGE verilog_node TDS_DUV_PATH.rst_por_" ; // Asserted when SIU dqs an NIU entry from Ordered Queue VJH |
| 62 | |
| 63 | input sii_niu_oqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_oqdq" ; // Asserted when SIU dqs an NIU entry from Ordered Queue |
| 64 | input sii_niu_bqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_bqdq" ; // Asserted when SIU dqs an NIU entry from Bypass Queue |
| 65 | |
| 66 | input sio_niu_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_hdr_vld" ; // SIO requesting to send packet to Ethernet |
| 67 | input sio_niu_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_datareq" ; // Valid during header phase only - 1=current request is a read data return |
| 68 | input [127:0] sio_niu_data INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_data" ; // Packet from SIO to Ethernet |
| 69 | input [7:0] sio_niu_parity INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_parity" ; // Packet parity from SIO to Ethernet |
| 70 | } |
| 71 | |
| 72 | #else |
| 73 | |
| 74 | interface niu_siu_chk { |
| 75 | |
| 76 | input clk CLOCK verilog_node TDS_DUV_PATH.niu_smx.niu_clk"; |
| 77 | |
| 78 | input niu_sii_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_hdr_vld"; // Ethernet requesting to send packet to SIU |
| 79 | input niu_sii_reqbypass INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_reqbypass"; // Ethernet requesting to send packet to bypass queue of SIU |
| 80 | input niu_sii_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_datareq"; // Ethernet requesting to send packet w/data to SIU |
| 81 | input [127:0] niu_sii_data INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_data"; // Packet from Ethernet to SIU |
| 82 | input [7:0] niu_sii_parity INPUT_EDGE verilog_node TDS_DUV_PATH.niu_sii_parity"; // Packet parity from Ethernet to SIU |
| 83 | |
| 84 | input niu_reset_l INPUT_EDGE verilog_node TDS_DUV_PATH.niu_smx.niu_reset_l" ; // Asserted when SIU dqs an NIU entry from Ordered Queue |
| 85 | |
| 86 | input sii_niu_oqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_oqdq" ; // Asserted when SIU dqs an NIU entry from Ordered Queue |
| 87 | input sii_niu_bqdq INPUT_EDGE verilog_node TDS_DUV_PATH.sii_niu_bqdq" ; // Asserted when SIU dqs an NIU entry from Bypass Queue |
| 88 | input sio_niu_hdr_vld INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_hdr_vld" ; // SIO requesting to send packet to Ethernet |
| 89 | input sio_niu_datareq INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_datareq" ; // Valid during header phase only - 1=current request is a read data return |
| 90 | input [127:0] sio_niu_data INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_data" ; // Packet from SIO to Ethernet |
| 91 | input [7:0] sio_niu_parity INPUT_EDGE verilog_node TDS_DUV_PATH.sio_niu_parity" ; // Packet parity from SIO to Ethernet |
| 92 | } |
| 93 | |
| 94 | #endif |
| 95 | |
| 96 | // RAS Interface from NCU- |
| 97 | |
| 98 | #ifdef NIU_GATE |
| 99 | |
| 100 | interface ncu_smx_chk { |
| 101 | input clk CLOCK verilog_node TDS_DUV_PATH.iol2clk"; |
| 102 | |
| 103 | input ncu_niu_ctag_uei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_uei"; |
| 104 | input ncu_niu_ctag_cei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_cei"; |
| 105 | input ncu_niu_d_pei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_d_pei "; |
| 106 | |
| 107 | input niu_ncu_ctag_ue INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ue"; |
| 108 | input niu_ncu_ctag_ce INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ce"; |
| 109 | input niu_ncu_d_pe INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_d_pe "; |
| 110 | |
| 111 | } |
| 112 | |
| 113 | #else |
| 114 | |
| 115 | interface ncu_smx_chk { |
| 116 | input clk CLOCK verilog_node TDS_DUV_PATH.niu_smx.niu_clk"; |
| 117 | |
| 118 | input ncu_niu_ctag_uei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_uei"; |
| 119 | input ncu_niu_ctag_cei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_ctag_cei"; |
| 120 | input ncu_niu_d_pei INPUT_EDGE verilog_node TDS_DUV_PATH.ncu_niu_d_pei "; |
| 121 | |
| 122 | input niu_ncu_ctag_ue INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ue"; |
| 123 | input niu_ncu_ctag_ce INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_ctag_ce"; |
| 124 | input niu_ncu_d_pe INPUT_EDGE verilog_node TDS_DUV_PATH.niu_ncu_d_pe "; |
| 125 | |
| 126 | } |
| 127 | |
| 128 | #endif |
| 129 | |
| 130 | port niu_siu_chk_iface { |
| 131 | |
| 132 | clk; |
| 133 | niu_reset_l; |
| 134 | niu_sii_hdr_vld; |
| 135 | niu_sii_reqbypass; |
| 136 | niu_sii_datareq; |
| 137 | niu_sii_data; |
| 138 | niu_sii_parity; |
| 139 | |
| 140 | sii_niu_oqdq; |
| 141 | sii_niu_bqdq; |
| 142 | sio_niu_hdr_vld; |
| 143 | sio_niu_datareq; |
| 144 | sio_niu_data; |
| 145 | sio_niu_parity; |
| 146 | |
| 147 | |
| 148 | } |
| 149 | |
| 150 | |
| 151 | bind niu_siu_chk_iface niu_siu_chk_pbind { |
| 152 | |
| 153 | clk niu_siu_chk.clk; |
| 154 | niu_reset_l niu_siu_chk.niu_reset_l; |
| 155 | niu_sii_hdr_vld niu_siu_chk.niu_sii_hdr_vld; |
| 156 | niu_sii_reqbypass niu_siu_chk.niu_sii_reqbypass; |
| 157 | niu_sii_datareq niu_siu_chk.niu_sii_datareq; |
| 158 | niu_sii_data niu_siu_chk.niu_sii_data; |
| 159 | niu_sii_parity niu_siu_chk.niu_sii_parity; |
| 160 | |
| 161 | sii_niu_oqdq niu_siu_chk.sii_niu_oqdq; |
| 162 | sii_niu_bqdq niu_siu_chk.sii_niu_bqdq; |
| 163 | sio_niu_hdr_vld niu_siu_chk.sio_niu_hdr_vld; |
| 164 | sio_niu_datareq niu_siu_chk.sio_niu_datareq; |
| 165 | sio_niu_data niu_siu_chk.sio_niu_data; |
| 166 | sio_niu_parity niu_siu_chk.sio_niu_parity; |
| 167 | |
| 168 | } |
| 169 | |
| 170 | port ncu_smx_chk_iface { |
| 171 | clk; |
| 172 | ncu_niu_ctag_uei; |
| 173 | ncu_niu_ctag_cei; |
| 174 | ncu_niu_d_pei; |
| 175 | niu_ncu_ctag_ue; |
| 176 | niu_ncu_ctag_ce; |
| 177 | niu_ncu_d_pe; |
| 178 | } |
| 179 | bind ncu_smx_chk_iface ncu_smx_chk_ras_pbind { |
| 180 | clk ncu_smx_chk.clk ; |
| 181 | ncu_niu_ctag_uei ncu_smx_chk.ncu_niu_ctag_uei; |
| 182 | ncu_niu_ctag_cei ncu_smx_chk.ncu_niu_ctag_cei; |
| 183 | ncu_niu_d_pei ncu_smx_chk.ncu_niu_d_pei ; |
| 184 | niu_ncu_ctag_ue ncu_smx_chk.niu_ncu_ctag_ue ; |
| 185 | niu_ncu_ctag_ce ncu_smx_chk.niu_ncu_ctag_ce ; |
| 186 | niu_ncu_d_pe ncu_smx_chk.niu_ncu_d_pe ; |
| 187 | |
| 188 | } |
| 189 | |