| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: pll.if.vri |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #ifndef INC_PLL_IF_VRI |
| 36 | #define INC_PLL_IF_VRI |
| 37 | |
| 38 | #include "fc_top_defines.vri" |
| 39 | |
| 40 | // |
| 41 | // WHAT: output of DIV2 divider block. In real PLL, DIV2 output is the feedback clock |
| 42 | // which is the input to PLL Phase Detector (PFD). In PLL vgate model, DIV2 |
| 43 | // output is NOT used, so the testbench needs to verify. |
| 44 | // |
| 45 | interface pll_core_div2_output_if { |
| 46 | input clk CLOCK verilog_node "`CCU.ccu_pll.x1.x8.div_ck"; // x1: module n2_core_pll_pecl_all_cust, x8: module n2_core_pll_tdm_cust |
| 47 | } |
| 48 | |
| 49 | // |
| 50 | // WHAT: interface for PLL ports |
| 51 | // |
| 52 | interface pll_core_if { |
| 53 | input clk CLOCK verilog_node "`CCU.cmp_pll_clk"; |
| 54 | |
| 55 | input ccu_rst_ref_buf2 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.ccu_rst_ref_buf2"; |
| 56 | input ccu_rst_sys_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.ccu_rst_sys_clk"; |
| 57 | input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CCU.ccu_pll.ccu_serdes_dtm"; |
| 58 | input dft_rst_a_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dft_rst_a_l"; |
| 59 | input dr_clk_out PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_clk_out"; |
| 60 | input dr_clk_out_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_clk_out_l"; |
| 61 | input dr_ext_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_ext_clk"; |
| 62 | input [1:0] dr_sdel PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_sdel"; |
| 63 | input [1:0] dr_sel_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_sel_a"; |
| 64 | input dr_stretch_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_stretch_a"; |
| 65 | input pll_arst_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_arst_l"; |
| 66 | input pll_bypass PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_bypass"; |
| 67 | input pll_char_in PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_char_in"; |
| 68 | input [1:0] pll_char_out PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_char_out"; |
| 69 | input pll_clamp_fltr PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_clamp_fltr"; |
| 70 | input pll_clk_out PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_clk_out"; |
| 71 | input pll_clk_out_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_clk_out_l"; |
| 72 | input [5:0] pll_div1 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div1"; |
| 73 | input [5:0] pll_div2 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div2"; |
| 74 | input [5:0] pll_div3 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div3"; |
| 75 | input [6:0] pll_div4 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div4"; |
| 76 | input pll_ext_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_ext_clk"; |
| 77 | input [1:0] pll_sdel PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_sdel"; |
| 78 | input [1:0] pll_sel_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_sel_a"; |
| 79 | input pll_stretch_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_stretch_a"; |
| 80 | input [1:0] pll_sys_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_sys_clk"; |
| 81 | input pll_testmode PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_testmode"; |
| 82 | input sel_l2clk_fbk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.sel_l2clk_fbk"; |
| 83 | input vdd_hv15 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.vdd_hv15"; |
| 84 | input vreg_selbg_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.vreg_selbg_l"; |
| 85 | } |
| 86 | |
| 87 | #endif |