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// OpenSPARC T2 Processor File: pll.if.vri
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#include "fc_top_defines.vri"
// WHAT: output of DIV2 divider block. In real PLL, DIV2 output is the feedback clock
// which is the input to PLL Phase Detector (PFD). In PLL vgate model, DIV2
// output is NOT used, so the testbench needs to verify.
interface pll_core_div2_output_if {
input clk CLOCK verilog_node "`CCU.ccu_pll.x1.x8.div_ck"; // x1: module n2_core_pll_pecl_all_cust, x8: module n2_core_pll_tdm_cust
// WHAT: interface for PLL ports
input clk CLOCK verilog_node "`CCU.cmp_pll_clk";
input ccu_rst_ref_buf2 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.ccu_rst_ref_buf2";
input ccu_rst_sys_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.ccu_rst_sys_clk";
input ccu_serdes_dtm PSAMPLE #-1 verilog_node "`CCU.ccu_pll.ccu_serdes_dtm";
input dft_rst_a_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dft_rst_a_l";
input dr_clk_out PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_clk_out";
input dr_clk_out_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_clk_out_l";
input dr_ext_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_ext_clk";
input [1:0] dr_sdel PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_sdel";
input [1:0] dr_sel_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_sel_a";
input dr_stretch_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.dr_stretch_a";
input pll_arst_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_arst_l";
input pll_bypass PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_bypass";
input pll_char_in PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_char_in";
input [1:0] pll_char_out PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_char_out";
input pll_clamp_fltr PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_clamp_fltr";
input pll_clk_out PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_clk_out";
input pll_clk_out_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_clk_out_l";
input [5:0] pll_div1 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div1";
input [5:0] pll_div2 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div2";
input [5:0] pll_div3 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div3";
input [6:0] pll_div4 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_div4";
input pll_ext_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_ext_clk";
input [1:0] pll_sdel PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_sdel";
input [1:0] pll_sel_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_sel_a";
input pll_stretch_a PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_stretch_a";
input [1:0] pll_sys_clk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_sys_clk";
input pll_testmode PSAMPLE #-1 verilog_node "`CCU.ccu_pll.pll_testmode";
input sel_l2clk_fbk PSAMPLE #-1 verilog_node "`CCU.ccu_pll.sel_l2clk_fbk";
input vdd_hv15 PSAMPLE #-1 verilog_node "`CCU.ccu_pll.vdd_hv15";
input vreg_selbg_l PSAMPLE #-1 verilog_node "`CCU.ccu_pll.vreg_selbg_l";
projects / OpenSPARC-T2-DV / blob