| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2t_dirrep_ctl.v |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | module l2t_dirrep_ctl ( |
| 36 | tcu_pce_ov, |
| 37 | tcu_aclk, |
| 38 | tcu_bclk, |
| 39 | tcu_scan_en, |
| 40 | dirrep_dir_wr_par_c4, |
| 41 | dirrep_dir_vld_c4_l, |
| 42 | dirrep_dc_rd_en_c4, |
| 43 | dirrep_dc_wr_en_c4, |
| 44 | dirrep_inval_mask_dcd_c4, |
| 45 | dirrep_dc_rdwr_row_en_c4, |
| 46 | dirrep_dc_rdwr_panel_dec_c4, |
| 47 | dirrep_dc_lkup_row_dec_c4, |
| 48 | dirrep_dc_lkup_panel_dec_c4, |
| 49 | dirrep_wr_dc_dir_entry_c4, |
| 50 | dirrep_dc_dir_clear_c4, |
| 51 | dirrep_ic_rd_en_c4, |
| 52 | dirrep_ic_wr_en_c4, |
| 53 | dirrep_inval_mask_icd_c4, |
| 54 | dirrep_ic_rdwr_row_en_c4, |
| 55 | dirrep_ic_rdwr_panel_dec_c4, |
| 56 | dirrep_ic_lkup_row_dec_c4, |
| 57 | dirrep_ic_lkup_panel_dec_c4, |
| 58 | dirrep_wr_ic_dir_entry_c4, |
| 59 | dirrep_ic_dir_clear_c4, |
| 60 | dirrep_dir_error_c8, |
| 61 | scan_out, |
| 62 | ic_parity_out, |
| 63 | dc_parity_out, |
| 64 | arbadr_arbdp_addr5to4_c3, |
| 65 | arbadr_arbdp_addr4_c4, |
| 66 | arbadr_arbdp_dc_addr4_c4, |
| 67 | arbadr_arbdp_ic_addr4_c4, |
| 68 | arbadr_arbdp_index_ic_addr4_c4, |
| 69 | arbadr_arbdp_index_dc_addr4_c4, |
| 70 | arb_inval_inst_vld_c3, |
| 71 | arb_dc_ic_rd_bit_4, |
| 72 | arbadr_arbdp_dir_wr_par_c3, |
| 73 | arb_dir_vld_c3_l, |
| 74 | arb_ic_rd_en_c3, |
| 75 | arb_dc_rd_en_c3, |
| 76 | arb_ic_wr_en_c3, |
| 77 | arb_dc_wr_en_c3, |
| 78 | arb_dir_panel_dcd_c3, |
| 79 | arb_dir_panel_icd_c3, |
| 80 | arb_lkup_bank_ena_dcd_c3, |
| 81 | arb_lkup_bank_ena_icd_c3, |
| 82 | arb_inval_mask_dcd_c3, |
| 83 | arb_inval_mask_icd_c3, |
| 84 | arb_wr_dc_dir_entry_c3, |
| 85 | arb_wr_ic_dir_entry_c3, |
| 86 | tagd_lkup_row_addr_dcd_c3, |
| 87 | tagd_lkup_row_addr_icd_c3, |
| 88 | arb_ic_inval_vld_c7, |
| 89 | csr_oneshot_dir_clear_c3, |
| 90 | por_l, |
| 91 | l2t_mb0_run, |
| 92 | l2clk, |
| 93 | scan_in); |
| 94 | wire pce_ov; |
| 95 | wire stop; |
| 96 | wire siclk; |
| 97 | wire soclk; |
| 98 | wire se; |
| 99 | wire l1clk; |
| 100 | wire spares_scanin; |
| 101 | wire spares_scanout; |
| 102 | wire ff_dir_error_c8_scanin; |
| 103 | wire ff_dir_error_c8_scanout; |
| 104 | wire ff_wr_par_c4_scanin; |
| 105 | wire ff_wr_par_c4_scanout; |
| 106 | wire ff_dir_vld_dcd_c4_l_scanin; |
| 107 | wire ff_dir_vld_dcd_c4_l_scanout; |
| 108 | wire ff_dc_rd_en_c4_scanin; |
| 109 | wire ff_dc_rd_en_c4_scanout; |
| 110 | wire ff_ic_rd_en_c4_scanin; |
| 111 | wire ff_ic_rd_en_c4_scanout; |
| 112 | wire ff_dc_wr_en_c4_scanin; |
| 113 | wire ff_dc_wr_en_c4_scanout; |
| 114 | wire ff_ic_wr_en_c4_scanin; |
| 115 | wire ff_ic_wr_en_c4_scanout; |
| 116 | wire ff_inval_mask_dcd_c4_scanin; |
| 117 | wire ff_inval_mask_dcd_c4_scanout; |
| 118 | wire ff_inval_mask_icd_c4_scanin; |
| 119 | wire ff_inval_mask_icd_c4_scanout; |
| 120 | wire [1:0] arbadr_arbdp_addr5to4_c4; |
| 121 | wire ff_dir_panel_dcd_c4_scanin; |
| 122 | wire ff_dir_panel_dcd_c4_scanout; |
| 123 | wire ff_inval_addrbit4_c4_scanin; |
| 124 | wire ff_inval_addrbit4_c4_scanout; |
| 125 | wire inval_inst_vld_c4; |
| 126 | wire inval_inst_vld_c5; |
| 127 | wire inval_inst_vld_c52; |
| 128 | wire inval_inst_vld_c6; |
| 129 | wire [1:0] arbadr_arbdp_addr5to4_c5; |
| 130 | wire [1:0] arbadr_arbdp_addr5to4_c52; |
| 131 | wire [1:0] arbadr_arbdp_addr5to4_c6; |
| 132 | wire arb_dc_ic_rd_bit_4_c4; |
| 133 | wire def_inval_entry; |
| 134 | wire arbadr_arbdp_dc_addr4_c4_fnl; |
| 135 | wire ff_dir_panel_icd_c4_scanin; |
| 136 | wire ff_dir_panel_icd_c4_scanout; |
| 137 | wire ff_inval_vld_c78910_scanin; |
| 138 | wire ff_inval_vld_c78910_scanout; |
| 139 | wire ic_inval_vld_c8; |
| 140 | wire ic_inval_vld_c9; |
| 141 | wire ic_inval_vld_c10; |
| 142 | wire ic_invalidation_bit4_flip; |
| 143 | wire arbadr_arbdp_ic_addr4_c4_fnl; |
| 144 | wire ff_lkup_row_addr_dcd_c4_scanin; |
| 145 | wire ff_lkup_row_addr_dcd_c4_scanout; |
| 146 | wire ff_lkup_bank_ena_dcd_c4_scanin; |
| 147 | wire ff_lkup_bank_ena_dcd_c4_scanout; |
| 148 | wire ff_lkup_row_addr_icd_c4_scanin; |
| 149 | wire ff_lkup_row_addr_icd_c4_scanout; |
| 150 | wire ff_lkup_bank_ena_icd_c4_scanin; |
| 151 | wire ff_lkup_bank_ena_icd_c4_scanout; |
| 152 | wire ff_wr_dc_dir_entry_c4_scanin; |
| 153 | wire ff_wr_dc_dir_entry_c4_scanout; |
| 154 | wire ff_wr_ic_dir_entry_c4_scanin; |
| 155 | wire ff_wr_ic_dir_entry_c4_scanout; |
| 156 | wire ff_ic_dir_clear_c4_scanin; |
| 157 | wire ff_ic_dir_clear_c4_scanout; |
| 158 | wire reset_dir_cams_c3; |
| 159 | wire ff_dc_dir_clear_c4_scanin; |
| 160 | wire ff_dc_dir_clear_c4_scanout; |
| 161 | wire fnl_csr_oneshot_dir_clear_c3; |
| 162 | wire l2t_mb0_run_r1; |
| 163 | wire ff_l2t_mb0_run_scanin; |
| 164 | wire ff_l2t_mb0_run_scanout; |
| 165 | |
| 166 | |
| 167 | input tcu_pce_ov; |
| 168 | input tcu_aclk; |
| 169 | input tcu_bclk; |
| 170 | input tcu_scan_en; |
| 171 | |
| 172 | |
| 173 | output dirrep_dir_wr_par_c4; |
| 174 | output dirrep_dir_vld_c4_l; |
| 175 | |
| 176 | |
| 177 | // D$ directory ( Left Bottom ) |
| 178 | output dirrep_dc_rd_en_c4; |
| 179 | output dirrep_dc_wr_en_c4; |
| 180 | output [7:0] dirrep_inval_mask_dcd_c4; |
| 181 | // Read and write addresses require a rd_en/wr_en qualification |
| 182 | output [3:0] dirrep_dc_rdwr_row_en_c4; // bits 4,3 of panel decode (i.e. address 10:9 ) |
| 183 | output [3:0] dirrep_dc_rdwr_panel_dec_c4; // dec bits 1:0 of the panel address (i.e. address 5,4 ); |
| 184 | // Lkup addresses do not require a qualification as the |
| 185 | // _lkup_row_dec_c4 is actually a qualified vector. |
| 186 | output [3:0] dirrep_dc_lkup_row_dec_c4 ; |
| 187 | output [3:0] dirrep_dc_lkup_panel_dec_c4 ;// use lkup_row_addr_dcd[2:1] dec |
| 188 | output [4:0] dirrep_wr_dc_dir_entry_c4 ; // lsb is arb_dir_panel_dcd[2] , BS and SR 11/18/03 Reverse Directory change |
| 189 | output dirrep_dc_dir_clear_c4; // Bottom left |
| 190 | // ie bit 8 of the address. |
| 191 | |
| 192 | // I$ directory ( Left TOp ) |
| 193 | output dirrep_ic_rd_en_c4; |
| 194 | output dirrep_ic_wr_en_c4; |
| 195 | output [7:0] dirrep_inval_mask_icd_c4; |
| 196 | // Read and write addresses require a rd_en/wr_en qualification |
| 197 | output [3:0] dirrep_ic_rdwr_row_en_c4; // bits 4,3 of panel decode (i.e. address 10:9 ) |
| 198 | output [3:0] dirrep_ic_rdwr_panel_dec_c4; // dec bits 1:0 of the panel address (i.e. address 5,4 ); |
| 199 | // Lkup addresses do not require a qualification as the |
| 200 | // _lkup_row_dec_c4 is actually a qualified vector. |
| 201 | output [3:0] dirrep_ic_lkup_row_dec_c4 ; // use lkup_row_addr_dcd[2:1] dec |
| 202 | output [3:0] dirrep_ic_lkup_panel_dec_c4 ; |
| 203 | output [4:0] dirrep_wr_ic_dir_entry_c4 ; // lsb is arb_dir_panel_icd[2], BS and SR 11/18/03 Reverse Directory change |
| 204 | // ie bit 8 of the address. |
| 205 | output dirrep_ic_dir_clear_c4; // Top left |
| 206 | |
| 207 | output dirrep_dir_error_c8; // Right |
| 208 | |
| 209 | output scan_out; |
| 210 | |
| 211 | input [3:0] ic_parity_out; // LeftTop ( C7 signal.) |
| 212 | input [3:0] dc_parity_out; // LeftBottom ( C7 signal.) |
| 213 | |
| 214 | // |
| 215 | // Directory restructure |
| 216 | // |
| 217 | |
| 218 | input [1:0] arbadr_arbdp_addr5to4_c3; |
| 219 | output arbadr_arbdp_addr4_c4; |
| 220 | output arbadr_arbdp_dc_addr4_c4; |
| 221 | output arbadr_arbdp_ic_addr4_c4; |
| 222 | output arbadr_arbdp_index_ic_addr4_c4; |
| 223 | output arbadr_arbdp_index_dc_addr4_c4; |
| 224 | |
| 225 | input arb_inval_inst_vld_c3; |
| 226 | input arb_dc_ic_rd_bit_4; |
| 227 | |
| 228 | // Use same pin positions as before. |
| 229 | input arbadr_arbdp_dir_wr_par_c3; |
| 230 | input arb_dir_vld_c3_l; |
| 231 | input arb_ic_rd_en_c3; |
| 232 | input arb_dc_rd_en_c3; |
| 233 | input arb_ic_wr_en_c3; |
| 234 | input arb_dc_wr_en_c3; |
| 235 | input [4:0] arb_dir_panel_dcd_c3; |
| 236 | input [4:0] arb_dir_panel_icd_c3; |
| 237 | input [3:0] arb_lkup_bank_ena_dcd_c3; // translates to a row_en |
| 238 | input [3:0] arb_lkup_bank_ena_icd_c3; |
| 239 | input [7:0] arb_inval_mask_dcd_c3; |
| 240 | input [7:0] arb_inval_mask_icd_c3; |
| 241 | input [4:0] arb_wr_dc_dir_entry_c3; |
| 242 | input [4:0] arb_wr_ic_dir_entry_c3; |
| 243 | input [2:0] tagd_lkup_row_addr_dcd_c3; // translates to a panel enable. |
| 244 | input [2:0] tagd_lkup_row_addr_icd_c3 ; |
| 245 | // comes from tagd |
| 246 | |
| 247 | input arb_ic_inval_vld_c7; |
| 248 | input csr_oneshot_dir_clear_c3; |
| 249 | input por_l; |
| 250 | |
| 251 | input l2t_mb0_run; |
| 252 | |
| 253 | input l2clk; |
| 254 | input scan_in; |
| 255 | |
| 256 | // BS 2/1/04 : Brought out IC inval signal to separate from IC fill |
| 257 | // because IC fill will load only one panel in 1 row (only one 1 cache waY) while IC inval will write |
| 258 | // to two panels in two rows (2 icache ways) every cycle. This IC dir write enable logic is in |
| 259 | // l2t_dir_ctl.sv. |
| 260 | |
| 261 | // input arb_ic_inval_wr_en_c3; // from l2t_arb_ctl |
| 262 | // output dirrep_ic_inval_wr_en_c4; // to l2t_dir_ctl modules |
| 263 | |
| 264 | |
| 265 | |
| 266 | ////////////////////////////////////////////////// |
| 267 | // L1 clk header |
| 268 | ////////////////////////////////////////////////// |
| 269 | assign pce_ov = tcu_pce_ov; |
| 270 | assign stop = 1'b0; |
| 271 | assign siclk = tcu_aclk; |
| 272 | assign soclk = tcu_bclk; |
| 273 | assign se = tcu_scan_en; |
| 274 | |
| 275 | l2t_dirrep_ctl_l1clkhdr_ctl_macro clkgen ( |
| 276 | .l2clk(l2clk), |
| 277 | .l1en(1'b1 ), |
| 278 | .l1clk(l1clk), |
| 279 | .pce_ov(pce_ov), |
| 280 | .stop(stop), |
| 281 | .se(se)); |
| 282 | |
| 283 | ////////////////////////////////////////////////// |
| 284 | |
| 285 | ////////////////////////////////////////// |
| 286 | // Spare gate insertion |
| 287 | ////////////////////////////////////////// |
| 288 | l2t_dirrep_ctl_spare_ctl_macro__num_5 spares ( |
| 289 | .scan_in(spares_scanin), |
| 290 | .scan_out(spares_scanout), |
| 291 | .l1clk (l1clk), |
| 292 | .siclk(siclk), |
| 293 | .soclk(soclk) |
| 294 | ); |
| 295 | ////////////////////////////////////////// |
| 296 | |
| 297 | |
| 298 | wire dir_error_c7; |
| 299 | wire [4:0] dir_panel_dcd_c4, dir_panel_icd_c4 ; |
| 300 | wire [2:0] lkup_row_addr_dcd_c4, lkup_row_addr_icd_c4; |
| 301 | |
| 302 | assign dir_error_c7 = (|(ic_parity_out)) | (|(dc_parity_out)) ; |
| 303 | |
| 304 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dir_error_c8 |
| 305 | (.dout (dirrep_dir_error_c8), |
| 306 | .scan_in(ff_dir_error_c8_scanin), |
| 307 | .scan_out(ff_dir_error_c8_scanout), |
| 308 | .din (dir_error_c7), |
| 309 | .l1clk (l1clk), |
| 310 | .siclk(siclk), |
| 311 | .soclk(soclk) |
| 312 | |
| 313 | |
| 314 | ) ; |
| 315 | |
| 316 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_wr_par_c4 |
| 317 | (.dout (dirrep_dir_wr_par_c4), |
| 318 | .scan_in(ff_wr_par_c4_scanin), |
| 319 | .scan_out(ff_wr_par_c4_scanout), |
| 320 | .din (arbadr_arbdp_dir_wr_par_c3), |
| 321 | .l1clk (l1clk), |
| 322 | .siclk(siclk), |
| 323 | .soclk(soclk) |
| 324 | |
| 325 | |
| 326 | ) ; |
| 327 | |
| 328 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dir_vld_dcd_c4_l |
| 329 | (.dout (dirrep_dir_vld_c4_l), |
| 330 | .scan_in(ff_dir_vld_dcd_c4_l_scanin), |
| 331 | .scan_out(ff_dir_vld_dcd_c4_l_scanout), |
| 332 | .din (arb_dir_vld_c3_l), |
| 333 | .l1clk (l1clk), |
| 334 | .siclk(siclk), |
| 335 | .soclk(soclk) |
| 336 | |
| 337 | |
| 338 | ) ; |
| 339 | |
| 340 | |
| 341 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dc_rd_en_c4 |
| 342 | (.dout (dirrep_dc_rd_en_c4), |
| 343 | .scan_in(ff_dc_rd_en_c4_scanin), |
| 344 | .scan_out(ff_dc_rd_en_c4_scanout), |
| 345 | .din (arb_dc_rd_en_c3), |
| 346 | .l1clk (l1clk), |
| 347 | .siclk(siclk), |
| 348 | .soclk(soclk) |
| 349 | |
| 350 | |
| 351 | ) ; |
| 352 | |
| 353 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_ic_rd_en_c4 |
| 354 | (.dout (dirrep_ic_rd_en_c4), |
| 355 | .scan_in(ff_ic_rd_en_c4_scanin), |
| 356 | .scan_out(ff_ic_rd_en_c4_scanout), |
| 357 | .din (arb_ic_rd_en_c3), |
| 358 | .l1clk (l1clk), |
| 359 | .siclk(siclk), |
| 360 | .soclk(soclk) |
| 361 | |
| 362 | |
| 363 | ) ; |
| 364 | |
| 365 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dc_wr_en_c4 |
| 366 | (.dout (dirrep_dc_wr_en_c4), |
| 367 | .scan_in(ff_dc_wr_en_c4_scanin), |
| 368 | .scan_out(ff_dc_wr_en_c4_scanout), |
| 369 | .din (arb_dc_wr_en_c3), |
| 370 | .l1clk (l1clk), |
| 371 | .siclk(siclk), |
| 372 | .soclk(soclk) |
| 373 | |
| 374 | |
| 375 | ) ; |
| 376 | |
| 377 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_ic_wr_en_c4 |
| 378 | (.dout (dirrep_ic_wr_en_c4), |
| 379 | .scan_in(ff_ic_wr_en_c4_scanin), |
| 380 | .scan_out(ff_ic_wr_en_c4_scanout), |
| 381 | .din (arb_ic_wr_en_c3), |
| 382 | .l1clk (l1clk), |
| 383 | .siclk(siclk), |
| 384 | .soclk(soclk) |
| 385 | |
| 386 | |
| 387 | ) ; |
| 388 | |
| 389 | //// BS 2/1/04 : Flop arb_ic_inval_wr_en_c3 to generate a C4 signal |
| 390 | //msff_ctl_macro ff_ic_inval_wr_en_c4 (width=1) |
| 391 | // (.dout (dirrep_ic_inval_wr_en_c4), |
| 392 | // .scan_in(ff_ic_inval_wr_en_c4_scanin), |
| 393 | // .scan_out(ff_ic_inval_wr_en_c4_scanout), |
| 394 | // .din (arb_ic_inval_wr_en_c3), |
| 395 | // .l1clk (l1clk), |
| 396 | // |
| 397 | // |
| 398 | // ) ; |
| 399 | |
| 400 | |
| 401 | |
| 402 | l2t_dirrep_ctl_msff_ctl_macro__width_8 ff_inval_mask_dcd_c4 |
| 403 | (.dout (dirrep_inval_mask_dcd_c4[7:0]), |
| 404 | .scan_in(ff_inval_mask_dcd_c4_scanin), |
| 405 | .scan_out(ff_inval_mask_dcd_c4_scanout), |
| 406 | .din (arb_inval_mask_dcd_c3[7:0]), |
| 407 | .l1clk (l1clk), |
| 408 | .siclk(siclk), |
| 409 | .soclk(soclk) |
| 410 | |
| 411 | |
| 412 | ) ; |
| 413 | |
| 414 | l2t_dirrep_ctl_msff_ctl_macro__width_8 ff_inval_mask_icd_c4 |
| 415 | (.dout (dirrep_inval_mask_icd_c4[7:0]), |
| 416 | .scan_in(ff_inval_mask_icd_c4_scanin), |
| 417 | .scan_out(ff_inval_mask_icd_c4_scanout), |
| 418 | .din (arb_inval_mask_icd_c3[7:0]), |
| 419 | .l1clk (l1clk), |
| 420 | .siclk(siclk), |
| 421 | .soclk(soclk) |
| 422 | |
| 423 | |
| 424 | ) ; |
| 425 | |
| 426 | |
| 427 | /////////////////////////////////////////////////////////// |
| 428 | // RD Write row and panel enables. |
| 429 | // Row is dtermined by the lower order bits of the |
| 430 | // address. |
| 431 | // ie bits 5,4 for the I$ |
| 432 | // ie bits 5,11 for the D$. |
| 433 | // Panel is determined by address bits 10,9 |
| 434 | /////////////////////////////////////////////////////////// |
| 435 | |
| 436 | l2t_dirrep_ctl_msff_ctl_macro__width_6 ff_dir_panel_dcd_c4 |
| 437 | (.dout ({arbadr_arbdp_addr5to4_c4[1:0],dir_panel_dcd_c4[4:3], dir_panel_dcd_c4[1:0]}), |
| 438 | .scan_in(ff_dir_panel_dcd_c4_scanin), |
| 439 | .scan_out(ff_dir_panel_dcd_c4_scanout), |
| 440 | .din ({arbadr_arbdp_addr5to4_c3[1:0],arb_dir_panel_dcd_c3[4:3],arb_dir_panel_dcd_c3[1:0]}), |
| 441 | .l1clk (l1clk), |
| 442 | .siclk(siclk), |
| 443 | .soclk(soclk) |
| 444 | ) ; |
| 445 | |
| 446 | |
| 447 | // Directory restructuring |
| 448 | |
| 449 | |
| 450 | l2t_dirrep_ctl_msff_ctl_macro__width_11 ff_inval_addrbit4_c4 |
| 451 | ( |
| 452 | .scan_in(ff_inval_addrbit4_c4_scanin), |
| 453 | .scan_out(ff_inval_addrbit4_c4_scanout), |
| 454 | .dout ({inval_inst_vld_c4,inval_inst_vld_c5,inval_inst_vld_c52,inval_inst_vld_c6, |
| 455 | arbadr_arbdp_addr5to4_c5[1:0],arbadr_arbdp_addr5to4_c52[1:0], |
| 456 | arbadr_arbdp_addr5to4_c6[1:0],arb_dc_ic_rd_bit_4_c4}), |
| 457 | .din ({arb_inval_inst_vld_c3,inval_inst_vld_c4,inval_inst_vld_c5,inval_inst_vld_c52, |
| 458 | arbadr_arbdp_addr5to4_c4[1:0],arbadr_arbdp_addr5to4_c5[1:0], |
| 459 | arbadr_arbdp_addr5to4_c52[1:0],arb_dc_ic_rd_bit_4}), |
| 460 | .l1clk (l1clk), |
| 461 | .siclk(siclk), |
| 462 | .soclk(soclk) |
| 463 | ) ; |
| 464 | |
| 465 | |
| 466 | assign def_inval_entry = ~( inval_inst_vld_c5 | inval_inst_vld_c52 | inval_inst_vld_c6 ) ; |
| 467 | |
| 468 | l2t_dirrep_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_1 mux_inval_dc_panel_c3 |
| 469 | ( |
| 470 | .dout (arbadr_arbdp_dc_addr4_c4_fnl), |
| 471 | .din0(arbadr_arbdp_addr5to4_c4[0]), .din1(arbadr_arbdp_addr5to4_c5[0]), |
| 472 | .din2(arbadr_arbdp_addr5to4_c52[0]), .din3(arbadr_arbdp_addr5to4_c6[0]), |
| 473 | .sel0(def_inval_entry), .sel1(inval_inst_vld_c5), |
| 474 | .sel2(inval_inst_vld_c52), .sel3(inval_inst_vld_c6)); |
| 475 | |
| 476 | |
| 477 | //assign arbadr_arbdp_dc_addr4_c4 = dirrep_dc_rd_en_c4 ? arb_dc_ic_rd_bit_4 : arbadr_arbdp_dc_addr4_c4_fnl ; |
| 478 | |
| 479 | |
| 480 | assign arbadr_arbdp_dc_addr4_c4 = arbadr_arbdp_dc_addr4_c4_fnl ; |
| 481 | |
| 482 | assign arbadr_arbdp_index_dc_addr4_c4 = arb_dc_ic_rd_bit_4_c4; |
| 483 | |
| 484 | assign arbadr_arbdp_addr4_c4 = arbadr_arbdp_addr5to4_c4[0]; |
| 485 | |
| 486 | |
| 487 | |
| 488 | |
| 489 | //assign dirrep_dc_rdwr_panel_dec_c4[0] = ( dir_panel_dcd_c4[4:3] == 2'd0 ); |
| 490 | //assign dirrep_dc_rdwr_panel_dec_c4[1] = ( dir_panel_dcd_c4[4:3] == 2'd1 ); |
| 491 | //assign dirrep_dc_rdwr_panel_dec_c4[2] = ( dir_panel_dcd_c4[4:3] == 2'd2 ); |
| 492 | //assign dirrep_dc_rdwr_panel_dec_c4[3] = ( dir_panel_dcd_c4[4:3] == 2'd3 ); |
| 493 | |
| 494 | assign dirrep_dc_rdwr_panel_dec_c4[0] = ~dir_panel_dcd_c4[4] & ~dir_panel_dcd_c4[3] ; |
| 495 | assign dirrep_dc_rdwr_panel_dec_c4[1] = ~dir_panel_dcd_c4[4] & dir_panel_dcd_c4[3] ; |
| 496 | assign dirrep_dc_rdwr_panel_dec_c4[2] = dir_panel_dcd_c4[4] & ~dir_panel_dcd_c4[3] ; |
| 497 | assign dirrep_dc_rdwr_panel_dec_c4[3] = dir_panel_dcd_c4[4] & dir_panel_dcd_c4[3] ; |
| 498 | |
| 499 | assign dirrep_dc_rdwr_row_en_c4[0] = (dir_panel_dcd_c4[1:0] == 2'd0 ); |
| 500 | assign dirrep_dc_rdwr_row_en_c4[1] = (dir_panel_dcd_c4[1:0] == 2'd1 ); |
| 501 | assign dirrep_dc_rdwr_row_en_c4[2] = (dir_panel_dcd_c4[1:0] == 2'd2 ); |
| 502 | assign dirrep_dc_rdwr_row_en_c4[3] = (dir_panel_dcd_c4[1:0] == 2'd3 ); |
| 503 | |
| 504 | l2t_dirrep_ctl_msff_ctl_macro__width_4 ff_dir_panel_icd_c4 |
| 505 | (.dout ({dir_panel_icd_c4[4:3],dir_panel_icd_c4[1:0]}), |
| 506 | .scan_in(ff_dir_panel_icd_c4_scanin), |
| 507 | .scan_out(ff_dir_panel_icd_c4_scanout), |
| 508 | .din ({arb_dir_panel_icd_c3[4:3],arb_dir_panel_icd_c3[1:0]}), |
| 509 | .l1clk (l1clk), |
| 510 | .siclk(siclk), |
| 511 | .soclk(soclk) |
| 512 | |
| 513 | |
| 514 | ) ; |
| 515 | |
| 516 | |
| 517 | assign dirrep_ic_rdwr_panel_dec_c4[0] = ( dir_panel_icd_c4[4:3] == 2'd0 ); |
| 518 | assign dirrep_ic_rdwr_panel_dec_c4[1] = ( dir_panel_icd_c4[4:3] == 2'd1 ); |
| 519 | assign dirrep_ic_rdwr_panel_dec_c4[2] = ( dir_panel_icd_c4[4:3] == 2'd2 ); |
| 520 | assign dirrep_ic_rdwr_panel_dec_c4[3] = ( dir_panel_icd_c4[4:3] == 2'd3 ); |
| 521 | |
| 522 | assign dirrep_ic_rdwr_row_en_c4[0] = (dir_panel_icd_c4[1:0] == 2'd0 ); |
| 523 | assign dirrep_ic_rdwr_row_en_c4[1] = (dir_panel_icd_c4[1:0] == 2'd1 ); |
| 524 | assign dirrep_ic_rdwr_row_en_c4[2] = (dir_panel_icd_c4[1:0] == 2'd2 ); |
| 525 | assign dirrep_ic_rdwr_row_en_c4[3] = (dir_panel_icd_c4[1:0] == 2'd3 ); |
| 526 | |
| 527 | // Dir changes Bit 4 computation for inval case is different |
| 528 | |
| 529 | |
| 530 | |
| 531 | l2t_dirrep_ctl_msff_ctl_macro__width_3 ff_inval_vld_c78910 |
| 532 | ( |
| 533 | .scan_in(ff_inval_vld_c78910_scanin), |
| 534 | .scan_out(ff_inval_vld_c78910_scanout), |
| 535 | .din ({arb_ic_inval_vld_c7,ic_inval_vld_c8,ic_inval_vld_c9}), |
| 536 | .dout ({ic_inval_vld_c8,ic_inval_vld_c9,ic_inval_vld_c10}), |
| 537 | .l1clk (l1clk), |
| 538 | .siclk(siclk), |
| 539 | .soclk(soclk) |
| 540 | ) ; |
| 541 | |
| 542 | |
| 543 | assign ic_invalidation_bit4_flip = arb_ic_inval_vld_c7 | ic_inval_vld_c8 | ic_inval_vld_c9 | ic_inval_vld_c10; |
| 544 | |
| 545 | // OLD :: assign arbadr_arbdp_ic_addr4_c4 = dir_panel_icd_c4[0]; |
| 546 | |
| 547 | assign arbadr_arbdp_ic_addr4_c4_fnl = ic_invalidation_bit4_flip ? ~dir_panel_icd_c4[0] : dir_panel_icd_c4[0] ; |
| 548 | |
| 549 | //assign arbadr_arbdp_ic_addr4_c4 = dirrep_ic_rd_en_c4 ? arb_dc_ic_rd_bit_4 : arbadr_arbdp_ic_addr4_c4_fnl ; |
| 550 | |
| 551 | assign arbadr_arbdp_ic_addr4_c4 = arbadr_arbdp_ic_addr4_c4_fnl ; |
| 552 | assign arbadr_arbdp_index_ic_addr4_c4 = arb_dc_ic_rd_bit_4_c4 ; |
| 553 | |
| 554 | |
| 555 | |
| 556 | /////////////////////////////////////////////////////////// |
| 557 | // lkup row and panel enables. |
| 558 | // Lkup row coming from tagd corresponds to |
| 559 | // address bits <10:8> of the lkup address. |
| 560 | // The bits <10:9> actually go into determining |
| 561 | // the panel id within the directory. |
| 562 | /////////////////////////////////////////////////////////// |
| 563 | |
| 564 | l2t_dirrep_ctl_msff_ctl_macro__width_3 ff_lkup_row_addr_dcd_c4 |
| 565 | (.dout (lkup_row_addr_dcd_c4[2:0]), |
| 566 | .scan_in(ff_lkup_row_addr_dcd_c4_scanin), |
| 567 | .scan_out(ff_lkup_row_addr_dcd_c4_scanout), |
| 568 | .din (tagd_lkup_row_addr_dcd_c3[2:0]), |
| 569 | .l1clk (l1clk), |
| 570 | .siclk(siclk), |
| 571 | .soclk(soclk) |
| 572 | |
| 573 | |
| 574 | ) ; |
| 575 | |
| 576 | assign dirrep_dc_lkup_panel_dec_c4[0] = ( lkup_row_addr_dcd_c4[1:0] == 2'd0 ); |
| 577 | assign dirrep_dc_lkup_panel_dec_c4[1] = ( lkup_row_addr_dcd_c4[1:0] == 2'd1 ); |
| 578 | assign dirrep_dc_lkup_panel_dec_c4[2] = ( lkup_row_addr_dcd_c4[1:0] == 2'd2 ); |
| 579 | assign dirrep_dc_lkup_panel_dec_c4[3] = ( lkup_row_addr_dcd_c4[1:0] == 2'd3 ); |
| 580 | |
| 581 | |
| 582 | l2t_dirrep_ctl_msff_ctl_macro__width_4 ff_lkup_bank_ena_dcd_c4 |
| 583 | (.dout (dirrep_dc_lkup_row_dec_c4[3:0]), |
| 584 | .scan_in(ff_lkup_bank_ena_dcd_c4_scanin), |
| 585 | .scan_out(ff_lkup_bank_ena_dcd_c4_scanout), |
| 586 | .din (arb_lkup_bank_ena_dcd_c3[3:0]), |
| 587 | .l1clk (l1clk), |
| 588 | .siclk(siclk), |
| 589 | .soclk(soclk) |
| 590 | |
| 591 | |
| 592 | ) ; |
| 593 | |
| 594 | |
| 595 | l2t_dirrep_ctl_msff_ctl_macro__width_3 ff_lkup_row_addr_icd_c4 |
| 596 | (.dout (lkup_row_addr_icd_c4[2:0]), |
| 597 | .scan_in(ff_lkup_row_addr_icd_c4_scanin), |
| 598 | .scan_out(ff_lkup_row_addr_icd_c4_scanout), |
| 599 | .din (tagd_lkup_row_addr_icd_c3[2:0]), |
| 600 | .l1clk (l1clk), |
| 601 | .siclk(siclk), |
| 602 | .soclk(soclk) |
| 603 | |
| 604 | |
| 605 | ) ; |
| 606 | |
| 607 | |
| 608 | assign dirrep_ic_lkup_panel_dec_c4[0] = ( lkup_row_addr_icd_c4[1:0] == 2'd0 ); |
| 609 | assign dirrep_ic_lkup_panel_dec_c4[1] = ( lkup_row_addr_icd_c4[1:0] == 2'd1 ); |
| 610 | assign dirrep_ic_lkup_panel_dec_c4[2] = ( lkup_row_addr_icd_c4[1:0] == 2'd2 ); |
| 611 | assign dirrep_ic_lkup_panel_dec_c4[3] = ( lkup_row_addr_icd_c4[1:0] == 2'd3 ); |
| 612 | |
| 613 | l2t_dirrep_ctl_msff_ctl_macro__width_4 ff_lkup_bank_ena_icd_c4 |
| 614 | (.dout (dirrep_ic_lkup_row_dec_c4[3:0]), |
| 615 | .scan_in(ff_lkup_bank_ena_icd_c4_scanin), |
| 616 | .scan_out(ff_lkup_bank_ena_icd_c4_scanout), |
| 617 | .din (arb_lkup_bank_ena_icd_c3[3:0]), |
| 618 | .l1clk (l1clk), |
| 619 | .siclk(siclk), |
| 620 | .soclk(soclk) |
| 621 | |
| 622 | |
| 623 | ) ; |
| 624 | |
| 625 | |
| 626 | l2t_dirrep_ctl_msff_ctl_macro__width_5 ff_wr_dc_dir_entry_c4 // BS and SR 11/18/03 Reverse Directory change |
| 627 | (.dout (dirrep_wr_dc_dir_entry_c4[4:0]), |
| 628 | .scan_in(ff_wr_dc_dir_entry_c4_scanin), |
| 629 | .scan_out(ff_wr_dc_dir_entry_c4_scanout), |
| 630 | .din (arb_wr_dc_dir_entry_c3[4:0]), // BS and SR 11/18/03 Reverse Directory change |
| 631 | .l1clk (l1clk), |
| 632 | .siclk(siclk), |
| 633 | .soclk(soclk) |
| 634 | |
| 635 | |
| 636 | ) ; |
| 637 | |
| 638 | |
| 639 | l2t_dirrep_ctl_msff_ctl_macro__width_5 ff_wr_ic_dir_entry_c4 // BS and SR 11/18/03 Reverse Directory change |
| 640 | (.dout (dirrep_wr_ic_dir_entry_c4[4:0]), |
| 641 | .scan_in(ff_wr_ic_dir_entry_c4_scanin), |
| 642 | .scan_out(ff_wr_ic_dir_entry_c4_scanout), |
| 643 | .din (arb_wr_ic_dir_entry_c3[4:0]), // BS and SR 11/18/03 Reverse Directory change |
| 644 | .l1clk (l1clk), |
| 645 | .siclk(siclk), |
| 646 | .soclk(soclk) |
| 647 | |
| 648 | |
| 649 | ) ; |
| 650 | |
| 651 | |
| 652 | /////////////////////////////////////////////////////////// |
| 653 | // Dir clear bits. |
| 654 | /////////////////////////////////////////////////////////// |
| 655 | |
| 656 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_ic_dir_clear_c4 |
| 657 | (.dout (dirrep_ic_dir_clear_c4), |
| 658 | .scan_in(ff_ic_dir_clear_c4_scanin), |
| 659 | .scan_out(ff_ic_dir_clear_c4_scanout), |
| 660 | .din (reset_dir_cams_c3), |
| 661 | .l1clk (l1clk), |
| 662 | .siclk(siclk), |
| 663 | .soclk(soclk) |
| 664 | ) ; |
| 665 | |
| 666 | |
| 667 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dc_dir_clear_c4 |
| 668 | (.dout (dirrep_dc_dir_clear_c4), |
| 669 | .scan_in(ff_dc_dir_clear_c4_scanin), |
| 670 | .scan_out(ff_dc_dir_clear_c4_scanout), |
| 671 | .din (reset_dir_cams_c3), |
| 672 | .l1clk (l1clk), |
| 673 | .siclk(siclk), |
| 674 | .soclk(soclk) |
| 675 | ) ; |
| 676 | |
| 677 | assign fnl_csr_oneshot_dir_clear_c3 = l2t_mb0_run_r1 ? 1'b0 : csr_oneshot_dir_clear_c3; |
| 678 | |
| 679 | assign reset_dir_cams_c3 = fnl_csr_oneshot_dir_clear_c3 | ~por_l; |
| 680 | |
| 681 | |
| 682 | l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_l2t_mb0_run |
| 683 | (.dout (l2t_mb0_run_r1), |
| 684 | .scan_in(ff_l2t_mb0_run_scanin), |
| 685 | .scan_out(ff_l2t_mb0_run_scanout), |
| 686 | .din (l2t_mb0_run), |
| 687 | .l1clk (l1clk), |
| 688 | .siclk(siclk), |
| 689 | .soclk(soclk) |
| 690 | ) ; |
| 691 | |
| 692 | |
| 693 | |
| 694 | |
| 695 | |
| 696 | |
| 697 | |
| 698 | // fixscan start: |
| 699 | assign spares_scanin = scan_in ; |
| 700 | assign ff_dir_error_c8_scanin = spares_scanout ; |
| 701 | assign ff_wr_par_c4_scanin = ff_dir_error_c8_scanout ; |
| 702 | assign ff_dir_vld_dcd_c4_l_scanin = ff_wr_par_c4_scanout ; |
| 703 | assign ff_dc_rd_en_c4_scanin = ff_dir_vld_dcd_c4_l_scanout; |
| 704 | assign ff_ic_rd_en_c4_scanin = ff_dc_rd_en_c4_scanout ; |
| 705 | assign ff_dc_wr_en_c4_scanin = ff_ic_rd_en_c4_scanout ; |
| 706 | assign ff_ic_wr_en_c4_scanin = ff_dc_wr_en_c4_scanout ; |
| 707 | assign ff_inval_mask_dcd_c4_scanin = ff_ic_wr_en_c4_scanout ; |
| 708 | assign ff_inval_mask_icd_c4_scanin = ff_inval_mask_dcd_c4_scanout; |
| 709 | assign ff_dir_panel_dcd_c4_scanin = ff_inval_mask_icd_c4_scanout; |
| 710 | assign ff_inval_addrbit4_c4_scanin = ff_dir_panel_dcd_c4_scanout; |
| 711 | assign ff_dir_panel_icd_c4_scanin = ff_inval_addrbit4_c4_scanout; |
| 712 | assign ff_inval_vld_c78910_scanin = ff_dir_panel_icd_c4_scanout; |
| 713 | assign ff_lkup_row_addr_dcd_c4_scanin = ff_inval_vld_c78910_scanout; |
| 714 | assign ff_lkup_bank_ena_dcd_c4_scanin = ff_lkup_row_addr_dcd_c4_scanout; |
| 715 | assign ff_lkup_row_addr_icd_c4_scanin = ff_lkup_bank_ena_dcd_c4_scanout; |
| 716 | assign ff_lkup_bank_ena_icd_c4_scanin = ff_lkup_row_addr_icd_c4_scanout; |
| 717 | assign ff_wr_dc_dir_entry_c4_scanin = ff_lkup_bank_ena_icd_c4_scanout; |
| 718 | assign ff_wr_ic_dir_entry_c4_scanin = ff_wr_dc_dir_entry_c4_scanout; |
| 719 | assign ff_ic_dir_clear_c4_scanin = ff_wr_ic_dir_entry_c4_scanout; |
| 720 | assign ff_dc_dir_clear_c4_scanin = ff_ic_dir_clear_c4_scanout; |
| 721 | assign ff_l2t_mb0_run_scanin = ff_dc_dir_clear_c4_scanout; |
| 722 | assign scan_out = ff_l2t_mb0_run_scanout ; |
| 723 | // fixscan end: |
| 724 | endmodule |
| 725 | |
| 726 | |
| 727 | |
| 728 | |
| 729 | |
| 730 | |
| 731 | |
| 732 | // any PARAMS parms go into naming of macro |
| 733 | |
| 734 | module l2t_dirrep_ctl_l1clkhdr_ctl_macro ( |
| 735 | l2clk, |
| 736 | l1en, |
| 737 | pce_ov, |
| 738 | stop, |
| 739 | se, |
| 740 | l1clk); |
| 741 | |
| 742 | |
| 743 | input l2clk; |
| 744 | input l1en; |
| 745 | input pce_ov; |
| 746 | input stop; |
| 747 | input se; |
| 748 | output l1clk; |
| 749 | |
| 750 | |
| 751 | |
| 752 | |
| 753 | |
| 754 | cl_sc1_l1hdr_8x c_0 ( |
| 755 | |
| 756 | |
| 757 | .l2clk(l2clk), |
| 758 | .pce(l1en), |
| 759 | .l1clk(l1clk), |
| 760 | .se(se), |
| 761 | .pce_ov(pce_ov), |
| 762 | .stop(stop) |
| 763 | ); |
| 764 | |
| 765 | |
| 766 | |
| 767 | endmodule |
| 768 | |
| 769 | |
| 770 | |
| 771 | |
| 772 | |
| 773 | |
| 774 | |
| 775 | |
| 776 | |
| 777 | // Description: Spare gate macro for control blocks |
| 778 | // |
| 779 | // Param num controls the number of times the macro is added |
| 780 | // flops=0 can be used to use only combination spare logic |
| 781 | |
| 782 | |
| 783 | module l2t_dirrep_ctl_spare_ctl_macro__num_5 ( |
| 784 | l1clk, |
| 785 | scan_in, |
| 786 | siclk, |
| 787 | soclk, |
| 788 | scan_out); |
| 789 | wire si_0; |
| 790 | wire so_0; |
| 791 | wire spare0_flop_unused; |
| 792 | wire spare0_buf_32x_unused; |
| 793 | wire spare0_nand3_8x_unused; |
| 794 | wire spare0_inv_8x_unused; |
| 795 | wire spare0_aoi22_4x_unused; |
| 796 | wire spare0_buf_8x_unused; |
| 797 | wire spare0_oai22_4x_unused; |
| 798 | wire spare0_inv_16x_unused; |
| 799 | wire spare0_nand2_16x_unused; |
| 800 | wire spare0_nor3_4x_unused; |
| 801 | wire spare0_nand2_8x_unused; |
| 802 | wire spare0_buf_16x_unused; |
| 803 | wire spare0_nor2_16x_unused; |
| 804 | wire spare0_inv_32x_unused; |
| 805 | wire si_1; |
| 806 | wire so_1; |
| 807 | wire spare1_flop_unused; |
| 808 | wire spare1_buf_32x_unused; |
| 809 | wire spare1_nand3_8x_unused; |
| 810 | wire spare1_inv_8x_unused; |
| 811 | wire spare1_aoi22_4x_unused; |
| 812 | wire spare1_buf_8x_unused; |
| 813 | wire spare1_oai22_4x_unused; |
| 814 | wire spare1_inv_16x_unused; |
| 815 | wire spare1_nand2_16x_unused; |
| 816 | wire spare1_nor3_4x_unused; |
| 817 | wire spare1_nand2_8x_unused; |
| 818 | wire spare1_buf_16x_unused; |
| 819 | wire spare1_nor2_16x_unused; |
| 820 | wire spare1_inv_32x_unused; |
| 821 | wire si_2; |
| 822 | wire so_2; |
| 823 | wire spare2_flop_unused; |
| 824 | wire spare2_buf_32x_unused; |
| 825 | wire spare2_nand3_8x_unused; |
| 826 | wire spare2_inv_8x_unused; |
| 827 | wire spare2_aoi22_4x_unused; |
| 828 | wire spare2_buf_8x_unused; |
| 829 | wire spare2_oai22_4x_unused; |
| 830 | wire spare2_inv_16x_unused; |
| 831 | wire spare2_nand2_16x_unused; |
| 832 | wire spare2_nor3_4x_unused; |
| 833 | wire spare2_nand2_8x_unused; |
| 834 | wire spare2_buf_16x_unused; |
| 835 | wire spare2_nor2_16x_unused; |
| 836 | wire spare2_inv_32x_unused; |
| 837 | wire si_3; |
| 838 | wire so_3; |
| 839 | wire spare3_flop_unused; |
| 840 | wire spare3_buf_32x_unused; |
| 841 | wire spare3_nand3_8x_unused; |
| 842 | wire spare3_inv_8x_unused; |
| 843 | wire spare3_aoi22_4x_unused; |
| 844 | wire spare3_buf_8x_unused; |
| 845 | wire spare3_oai22_4x_unused; |
| 846 | wire spare3_inv_16x_unused; |
| 847 | wire spare3_nand2_16x_unused; |
| 848 | wire spare3_nor3_4x_unused; |
| 849 | wire spare3_nand2_8x_unused; |
| 850 | wire spare3_buf_16x_unused; |
| 851 | wire spare3_nor2_16x_unused; |
| 852 | wire spare3_inv_32x_unused; |
| 853 | wire si_4; |
| 854 | wire so_4; |
| 855 | wire spare4_flop_unused; |
| 856 | wire spare4_buf_32x_unused; |
| 857 | wire spare4_nand3_8x_unused; |
| 858 | wire spare4_inv_8x_unused; |
| 859 | wire spare4_aoi22_4x_unused; |
| 860 | wire spare4_buf_8x_unused; |
| 861 | wire spare4_oai22_4x_unused; |
| 862 | wire spare4_inv_16x_unused; |
| 863 | wire spare4_nand2_16x_unused; |
| 864 | wire spare4_nor3_4x_unused; |
| 865 | wire spare4_nand2_8x_unused; |
| 866 | wire spare4_buf_16x_unused; |
| 867 | wire spare4_nor2_16x_unused; |
| 868 | wire spare4_inv_32x_unused; |
| 869 | |
| 870 | |
| 871 | input l1clk; |
| 872 | input scan_in; |
| 873 | input siclk; |
| 874 | input soclk; |
| 875 | output scan_out; |
| 876 | |
| 877 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), |
| 878 | .siclk(siclk), |
| 879 | .soclk(soclk), |
| 880 | .si(si_0), |
| 881 | .so(so_0), |
| 882 | .d(1'b0), |
| 883 | .q(spare0_flop_unused)); |
| 884 | assign si_0 = scan_in; |
| 885 | |
| 886 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), |
| 887 | .out(spare0_buf_32x_unused)); |
| 888 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), |
| 889 | .in1(1'b1), |
| 890 | .in2(1'b1), |
| 891 | .out(spare0_nand3_8x_unused)); |
| 892 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), |
| 893 | .out(spare0_inv_8x_unused)); |
| 894 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), |
| 895 | .in01(1'b1), |
| 896 | .in10(1'b1), |
| 897 | .in11(1'b1), |
| 898 | .out(spare0_aoi22_4x_unused)); |
| 899 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), |
| 900 | .out(spare0_buf_8x_unused)); |
| 901 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), |
| 902 | .in01(1'b1), |
| 903 | .in10(1'b1), |
| 904 | .in11(1'b1), |
| 905 | .out(spare0_oai22_4x_unused)); |
| 906 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), |
| 907 | .out(spare0_inv_16x_unused)); |
| 908 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), |
| 909 | .in1(1'b1), |
| 910 | .out(spare0_nand2_16x_unused)); |
| 911 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), |
| 912 | .in1(1'b0), |
| 913 | .in2(1'b0), |
| 914 | .out(spare0_nor3_4x_unused)); |
| 915 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), |
| 916 | .in1(1'b1), |
| 917 | .out(spare0_nand2_8x_unused)); |
| 918 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), |
| 919 | .out(spare0_buf_16x_unused)); |
| 920 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), |
| 921 | .in1(1'b0), |
| 922 | .out(spare0_nor2_16x_unused)); |
| 923 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), |
| 924 | .out(spare0_inv_32x_unused)); |
| 925 | |
| 926 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), |
| 927 | .siclk(siclk), |
| 928 | .soclk(soclk), |
| 929 | .si(si_1), |
| 930 | .so(so_1), |
| 931 | .d(1'b0), |
| 932 | .q(spare1_flop_unused)); |
| 933 | assign si_1 = so_0; |
| 934 | |
| 935 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), |
| 936 | .out(spare1_buf_32x_unused)); |
| 937 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), |
| 938 | .in1(1'b1), |
| 939 | .in2(1'b1), |
| 940 | .out(spare1_nand3_8x_unused)); |
| 941 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), |
| 942 | .out(spare1_inv_8x_unused)); |
| 943 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), |
| 944 | .in01(1'b1), |
| 945 | .in10(1'b1), |
| 946 | .in11(1'b1), |
| 947 | .out(spare1_aoi22_4x_unused)); |
| 948 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), |
| 949 | .out(spare1_buf_8x_unused)); |
| 950 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), |
| 951 | .in01(1'b1), |
| 952 | .in10(1'b1), |
| 953 | .in11(1'b1), |
| 954 | .out(spare1_oai22_4x_unused)); |
| 955 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), |
| 956 | .out(spare1_inv_16x_unused)); |
| 957 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), |
| 958 | .in1(1'b1), |
| 959 | .out(spare1_nand2_16x_unused)); |
| 960 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), |
| 961 | .in1(1'b0), |
| 962 | .in2(1'b0), |
| 963 | .out(spare1_nor3_4x_unused)); |
| 964 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), |
| 965 | .in1(1'b1), |
| 966 | .out(spare1_nand2_8x_unused)); |
| 967 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), |
| 968 | .out(spare1_buf_16x_unused)); |
| 969 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), |
| 970 | .in1(1'b0), |
| 971 | .out(spare1_nor2_16x_unused)); |
| 972 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), |
| 973 | .out(spare1_inv_32x_unused)); |
| 974 | |
| 975 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), |
| 976 | .siclk(siclk), |
| 977 | .soclk(soclk), |
| 978 | .si(si_2), |
| 979 | .so(so_2), |
| 980 | .d(1'b0), |
| 981 | .q(spare2_flop_unused)); |
| 982 | assign si_2 = so_1; |
| 983 | |
| 984 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), |
| 985 | .out(spare2_buf_32x_unused)); |
| 986 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), |
| 987 | .in1(1'b1), |
| 988 | .in2(1'b1), |
| 989 | .out(spare2_nand3_8x_unused)); |
| 990 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), |
| 991 | .out(spare2_inv_8x_unused)); |
| 992 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), |
| 993 | .in01(1'b1), |
| 994 | .in10(1'b1), |
| 995 | .in11(1'b1), |
| 996 | .out(spare2_aoi22_4x_unused)); |
| 997 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), |
| 998 | .out(spare2_buf_8x_unused)); |
| 999 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), |
| 1000 | .in01(1'b1), |
| 1001 | .in10(1'b1), |
| 1002 | .in11(1'b1), |
| 1003 | .out(spare2_oai22_4x_unused)); |
| 1004 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), |
| 1005 | .out(spare2_inv_16x_unused)); |
| 1006 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), |
| 1007 | .in1(1'b1), |
| 1008 | .out(spare2_nand2_16x_unused)); |
| 1009 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), |
| 1010 | .in1(1'b0), |
| 1011 | .in2(1'b0), |
| 1012 | .out(spare2_nor3_4x_unused)); |
| 1013 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), |
| 1014 | .in1(1'b1), |
| 1015 | .out(spare2_nand2_8x_unused)); |
| 1016 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), |
| 1017 | .out(spare2_buf_16x_unused)); |
| 1018 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), |
| 1019 | .in1(1'b0), |
| 1020 | .out(spare2_nor2_16x_unused)); |
| 1021 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), |
| 1022 | .out(spare2_inv_32x_unused)); |
| 1023 | |
| 1024 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), |
| 1025 | .siclk(siclk), |
| 1026 | .soclk(soclk), |
| 1027 | .si(si_3), |
| 1028 | .so(so_3), |
| 1029 | .d(1'b0), |
| 1030 | .q(spare3_flop_unused)); |
| 1031 | assign si_3 = so_2; |
| 1032 | |
| 1033 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), |
| 1034 | .out(spare3_buf_32x_unused)); |
| 1035 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), |
| 1036 | .in1(1'b1), |
| 1037 | .in2(1'b1), |
| 1038 | .out(spare3_nand3_8x_unused)); |
| 1039 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), |
| 1040 | .out(spare3_inv_8x_unused)); |
| 1041 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), |
| 1042 | .in01(1'b1), |
| 1043 | .in10(1'b1), |
| 1044 | .in11(1'b1), |
| 1045 | .out(spare3_aoi22_4x_unused)); |
| 1046 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), |
| 1047 | .out(spare3_buf_8x_unused)); |
| 1048 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), |
| 1049 | .in01(1'b1), |
| 1050 | .in10(1'b1), |
| 1051 | .in11(1'b1), |
| 1052 | .out(spare3_oai22_4x_unused)); |
| 1053 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), |
| 1054 | .out(spare3_inv_16x_unused)); |
| 1055 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), |
| 1056 | .in1(1'b1), |
| 1057 | .out(spare3_nand2_16x_unused)); |
| 1058 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), |
| 1059 | .in1(1'b0), |
| 1060 | .in2(1'b0), |
| 1061 | .out(spare3_nor3_4x_unused)); |
| 1062 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), |
| 1063 | .in1(1'b1), |
| 1064 | .out(spare3_nand2_8x_unused)); |
| 1065 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), |
| 1066 | .out(spare3_buf_16x_unused)); |
| 1067 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), |
| 1068 | .in1(1'b0), |
| 1069 | .out(spare3_nor2_16x_unused)); |
| 1070 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), |
| 1071 | .out(spare3_inv_32x_unused)); |
| 1072 | |
| 1073 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), |
| 1074 | .siclk(siclk), |
| 1075 | .soclk(soclk), |
| 1076 | .si(si_4), |
| 1077 | .so(so_4), |
| 1078 | .d(1'b0), |
| 1079 | .q(spare4_flop_unused)); |
| 1080 | assign si_4 = so_3; |
| 1081 | |
| 1082 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), |
| 1083 | .out(spare4_buf_32x_unused)); |
| 1084 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), |
| 1085 | .in1(1'b1), |
| 1086 | .in2(1'b1), |
| 1087 | .out(spare4_nand3_8x_unused)); |
| 1088 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), |
| 1089 | .out(spare4_inv_8x_unused)); |
| 1090 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), |
| 1091 | .in01(1'b1), |
| 1092 | .in10(1'b1), |
| 1093 | .in11(1'b1), |
| 1094 | .out(spare4_aoi22_4x_unused)); |
| 1095 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), |
| 1096 | .out(spare4_buf_8x_unused)); |
| 1097 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), |
| 1098 | .in01(1'b1), |
| 1099 | .in10(1'b1), |
| 1100 | .in11(1'b1), |
| 1101 | .out(spare4_oai22_4x_unused)); |
| 1102 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), |
| 1103 | .out(spare4_inv_16x_unused)); |
| 1104 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), |
| 1105 | .in1(1'b1), |
| 1106 | .out(spare4_nand2_16x_unused)); |
| 1107 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), |
| 1108 | .in1(1'b0), |
| 1109 | .in2(1'b0), |
| 1110 | .out(spare4_nor3_4x_unused)); |
| 1111 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), |
| 1112 | .in1(1'b1), |
| 1113 | .out(spare4_nand2_8x_unused)); |
| 1114 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), |
| 1115 | .out(spare4_buf_16x_unused)); |
| 1116 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), |
| 1117 | .in1(1'b0), |
| 1118 | .out(spare4_nor2_16x_unused)); |
| 1119 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), |
| 1120 | .out(spare4_inv_32x_unused)); |
| 1121 | assign scan_out = so_4; |
| 1122 | |
| 1123 | |
| 1124 | |
| 1125 | endmodule |
| 1126 | |
| 1127 | |
| 1128 | |
| 1129 | |
| 1130 | |
| 1131 | |
| 1132 | // any PARAMS parms go into naming of macro |
| 1133 | |
| 1134 | module l2t_dirrep_ctl_msff_ctl_macro__width_1 ( |
| 1135 | din, |
| 1136 | l1clk, |
| 1137 | scan_in, |
| 1138 | siclk, |
| 1139 | soclk, |
| 1140 | dout, |
| 1141 | scan_out); |
| 1142 | wire [0:0] fdin; |
| 1143 | |
| 1144 | input [0:0] din; |
| 1145 | input l1clk; |
| 1146 | input scan_in; |
| 1147 | |
| 1148 | |
| 1149 | input siclk; |
| 1150 | input soclk; |
| 1151 | |
| 1152 | output [0:0] dout; |
| 1153 | output scan_out; |
| 1154 | assign fdin[0:0] = din[0:0]; |
| 1155 | |
| 1156 | |
| 1157 | |
| 1158 | |
| 1159 | |
| 1160 | |
| 1161 | dff #(1) d0_0 ( |
| 1162 | .l1clk(l1clk), |
| 1163 | .siclk(siclk), |
| 1164 | .soclk(soclk), |
| 1165 | .d(fdin[0:0]), |
| 1166 | .si(scan_in), |
| 1167 | .so(scan_out), |
| 1168 | .q(dout[0:0]) |
| 1169 | ); |
| 1170 | |
| 1171 | |
| 1172 | |
| 1173 | |
| 1174 | |
| 1175 | |
| 1176 | |
| 1177 | |
| 1178 | |
| 1179 | |
| 1180 | |
| 1181 | |
| 1182 | endmodule |
| 1183 | |
| 1184 | |
| 1185 | |
| 1186 | |
| 1187 | |
| 1188 | |
| 1189 | |
| 1190 | |
| 1191 | |
| 1192 | |
| 1193 | |
| 1194 | |
| 1195 | |
| 1196 | // any PARAMS parms go into naming of macro |
| 1197 | |
| 1198 | module l2t_dirrep_ctl_msff_ctl_macro__width_8 ( |
| 1199 | din, |
| 1200 | l1clk, |
| 1201 | scan_in, |
| 1202 | siclk, |
| 1203 | soclk, |
| 1204 | dout, |
| 1205 | scan_out); |
| 1206 | wire [7:0] fdin; |
| 1207 | wire [6:0] so; |
| 1208 | |
| 1209 | input [7:0] din; |
| 1210 | input l1clk; |
| 1211 | input scan_in; |
| 1212 | |
| 1213 | |
| 1214 | input siclk; |
| 1215 | input soclk; |
| 1216 | |
| 1217 | output [7:0] dout; |
| 1218 | output scan_out; |
| 1219 | assign fdin[7:0] = din[7:0]; |
| 1220 | |
| 1221 | |
| 1222 | |
| 1223 | |
| 1224 | |
| 1225 | |
| 1226 | dff #(8) d0_0 ( |
| 1227 | .l1clk(l1clk), |
| 1228 | .siclk(siclk), |
| 1229 | .soclk(soclk), |
| 1230 | .d(fdin[7:0]), |
| 1231 | .si({scan_in,so[6:0]}), |
| 1232 | .so({so[6:0],scan_out}), |
| 1233 | .q(dout[7:0]) |
| 1234 | ); |
| 1235 | |
| 1236 | |
| 1237 | |
| 1238 | |
| 1239 | |
| 1240 | |
| 1241 | |
| 1242 | |
| 1243 | |
| 1244 | |
| 1245 | |
| 1246 | |
| 1247 | endmodule |
| 1248 | |
| 1249 | |
| 1250 | |
| 1251 | |
| 1252 | |
| 1253 | |
| 1254 | |
| 1255 | |
| 1256 | |
| 1257 | |
| 1258 | |
| 1259 | |
| 1260 | |
| 1261 | // any PARAMS parms go into naming of macro |
| 1262 | |
| 1263 | module l2t_dirrep_ctl_msff_ctl_macro__width_6 ( |
| 1264 | din, |
| 1265 | l1clk, |
| 1266 | scan_in, |
| 1267 | siclk, |
| 1268 | soclk, |
| 1269 | dout, |
| 1270 | scan_out); |
| 1271 | wire [5:0] fdin; |
| 1272 | wire [4:0] so; |
| 1273 | |
| 1274 | input [5:0] din; |
| 1275 | input l1clk; |
| 1276 | input scan_in; |
| 1277 | |
| 1278 | |
| 1279 | input siclk; |
| 1280 | input soclk; |
| 1281 | |
| 1282 | output [5:0] dout; |
| 1283 | output scan_out; |
| 1284 | assign fdin[5:0] = din[5:0]; |
| 1285 | |
| 1286 | |
| 1287 | |
| 1288 | |
| 1289 | |
| 1290 | |
| 1291 | dff #(6) d0_0 ( |
| 1292 | .l1clk(l1clk), |
| 1293 | .siclk(siclk), |
| 1294 | .soclk(soclk), |
| 1295 | .d(fdin[5:0]), |
| 1296 | .si({scan_in,so[4:0]}), |
| 1297 | .so({so[4:0],scan_out}), |
| 1298 | .q(dout[5:0]) |
| 1299 | ); |
| 1300 | |
| 1301 | |
| 1302 | |
| 1303 | |
| 1304 | |
| 1305 | |
| 1306 | |
| 1307 | |
| 1308 | |
| 1309 | |
| 1310 | |
| 1311 | |
| 1312 | endmodule |
| 1313 | |
| 1314 | |
| 1315 | |
| 1316 | |
| 1317 | |
| 1318 | |
| 1319 | |
| 1320 | |
| 1321 | |
| 1322 | |
| 1323 | |
| 1324 | |
| 1325 | |
| 1326 | // any PARAMS parms go into naming of macro |
| 1327 | |
| 1328 | module l2t_dirrep_ctl_msff_ctl_macro__width_11 ( |
| 1329 | din, |
| 1330 | l1clk, |
| 1331 | scan_in, |
| 1332 | siclk, |
| 1333 | soclk, |
| 1334 | dout, |
| 1335 | scan_out); |
| 1336 | wire [10:0] fdin; |
| 1337 | wire [9:0] so; |
| 1338 | |
| 1339 | input [10:0] din; |
| 1340 | input l1clk; |
| 1341 | input scan_in; |
| 1342 | |
| 1343 | |
| 1344 | input siclk; |
| 1345 | input soclk; |
| 1346 | |
| 1347 | output [10:0] dout; |
| 1348 | output scan_out; |
| 1349 | assign fdin[10:0] = din[10:0]; |
| 1350 | |
| 1351 | |
| 1352 | |
| 1353 | |
| 1354 | |
| 1355 | |
| 1356 | dff #(11) d0_0 ( |
| 1357 | .l1clk(l1clk), |
| 1358 | .siclk(siclk), |
| 1359 | .soclk(soclk), |
| 1360 | .d(fdin[10:0]), |
| 1361 | .si({scan_in,so[9:0]}), |
| 1362 | .so({so[9:0],scan_out}), |
| 1363 | .q(dout[10:0]) |
| 1364 | ); |
| 1365 | |
| 1366 | |
| 1367 | |
| 1368 | |
| 1369 | |
| 1370 | |
| 1371 | |
| 1372 | |
| 1373 | |
| 1374 | |
| 1375 | |
| 1376 | |
| 1377 | endmodule |
| 1378 | |
| 1379 | |
| 1380 | |
| 1381 | |
| 1382 | |
| 1383 | |
| 1384 | |
| 1385 | |
| 1386 | |
| 1387 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders |
| 1388 | // also for pass-gate with decoder |
| 1389 | |
| 1390 | |
| 1391 | |
| 1392 | |
| 1393 | |
| 1394 | // any PARAMS parms go into naming of macro |
| 1395 | |
| 1396 | module l2t_dirrep_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_1 ( |
| 1397 | din0, |
| 1398 | sel0, |
| 1399 | din1, |
| 1400 | sel1, |
| 1401 | din2, |
| 1402 | sel2, |
| 1403 | din3, |
| 1404 | sel3, |
| 1405 | dout); |
| 1406 | input [0:0] din0; |
| 1407 | input sel0; |
| 1408 | input [0:0] din1; |
| 1409 | input sel1; |
| 1410 | input [0:0] din2; |
| 1411 | input sel2; |
| 1412 | input [0:0] din3; |
| 1413 | input sel3; |
| 1414 | output [0:0] dout; |
| 1415 | |
| 1416 | |
| 1417 | |
| 1418 | |
| 1419 | |
| 1420 | assign dout[0:0] = ( {1{sel0}} & din0[0:0] ) | |
| 1421 | ( {1{sel1}} & din1[0:0]) | |
| 1422 | ( {1{sel2}} & din2[0:0]) | |
| 1423 | ( {1{sel3}} & din3[0:0]); |
| 1424 | |
| 1425 | |
| 1426 | |
| 1427 | |
| 1428 | |
| 1429 | endmodule |
| 1430 | |
| 1431 | |
| 1432 | |
| 1433 | |
| 1434 | |
| 1435 | |
| 1436 | // any PARAMS parms go into naming of macro |
| 1437 | |
| 1438 | module l2t_dirrep_ctl_msff_ctl_macro__width_4 ( |
| 1439 | din, |
| 1440 | l1clk, |
| 1441 | scan_in, |
| 1442 | siclk, |
| 1443 | soclk, |
| 1444 | dout, |
| 1445 | scan_out); |
| 1446 | wire [3:0] fdin; |
| 1447 | wire [2:0] so; |
| 1448 | |
| 1449 | input [3:0] din; |
| 1450 | input l1clk; |
| 1451 | input scan_in; |
| 1452 | |
| 1453 | |
| 1454 | input siclk; |
| 1455 | input soclk; |
| 1456 | |
| 1457 | output [3:0] dout; |
| 1458 | output scan_out; |
| 1459 | assign fdin[3:0] = din[3:0]; |
| 1460 | |
| 1461 | |
| 1462 | |
| 1463 | |
| 1464 | |
| 1465 | |
| 1466 | dff #(4) d0_0 ( |
| 1467 | .l1clk(l1clk), |
| 1468 | .siclk(siclk), |
| 1469 | .soclk(soclk), |
| 1470 | .d(fdin[3:0]), |
| 1471 | .si({scan_in,so[2:0]}), |
| 1472 | .so({so[2:0],scan_out}), |
| 1473 | .q(dout[3:0]) |
| 1474 | ); |
| 1475 | |
| 1476 | |
| 1477 | |
| 1478 | |
| 1479 | |
| 1480 | |
| 1481 | |
| 1482 | |
| 1483 | |
| 1484 | |
| 1485 | |
| 1486 | |
| 1487 | endmodule |
| 1488 | |
| 1489 | |
| 1490 | |
| 1491 | |
| 1492 | |
| 1493 | |
| 1494 | |
| 1495 | |
| 1496 | |
| 1497 | |
| 1498 | |
| 1499 | |
| 1500 | |
| 1501 | // any PARAMS parms go into naming of macro |
| 1502 | |
| 1503 | module l2t_dirrep_ctl_msff_ctl_macro__width_3 ( |
| 1504 | din, |
| 1505 | l1clk, |
| 1506 | scan_in, |
| 1507 | siclk, |
| 1508 | soclk, |
| 1509 | dout, |
| 1510 | scan_out); |
| 1511 | wire [2:0] fdin; |
| 1512 | wire [1:0] so; |
| 1513 | |
| 1514 | input [2:0] din; |
| 1515 | input l1clk; |
| 1516 | input scan_in; |
| 1517 | |
| 1518 | |
| 1519 | input siclk; |
| 1520 | input soclk; |
| 1521 | |
| 1522 | output [2:0] dout; |
| 1523 | output scan_out; |
| 1524 | assign fdin[2:0] = din[2:0]; |
| 1525 | |
| 1526 | |
| 1527 | |
| 1528 | |
| 1529 | |
| 1530 | |
| 1531 | dff #(3) d0_0 ( |
| 1532 | .l1clk(l1clk), |
| 1533 | .siclk(siclk), |
| 1534 | .soclk(soclk), |
| 1535 | .d(fdin[2:0]), |
| 1536 | .si({scan_in,so[1:0]}), |
| 1537 | .so({so[1:0],scan_out}), |
| 1538 | .q(dout[2:0]) |
| 1539 | ); |
| 1540 | |
| 1541 | |
| 1542 | |
| 1543 | |
| 1544 | |
| 1545 | |
| 1546 | |
| 1547 | |
| 1548 | |
| 1549 | |
| 1550 | |
| 1551 | |
| 1552 | endmodule |
| 1553 | |
| 1554 | |
| 1555 | |
| 1556 | |
| 1557 | |
| 1558 | |
| 1559 | |
| 1560 | |
| 1561 | |
| 1562 | |
| 1563 | |
| 1564 | |
| 1565 | |
| 1566 | // any PARAMS parms go into naming of macro |
| 1567 | |
| 1568 | module l2t_dirrep_ctl_msff_ctl_macro__width_5 ( |
| 1569 | din, |
| 1570 | l1clk, |
| 1571 | scan_in, |
| 1572 | siclk, |
| 1573 | soclk, |
| 1574 | dout, |
| 1575 | scan_out); |
| 1576 | wire [4:0] fdin; |
| 1577 | wire [3:0] so; |
| 1578 | |
| 1579 | input [4:0] din; |
| 1580 | input l1clk; |
| 1581 | input scan_in; |
| 1582 | |
| 1583 | |
| 1584 | input siclk; |
| 1585 | input soclk; |
| 1586 | |
| 1587 | output [4:0] dout; |
| 1588 | output scan_out; |
| 1589 | assign fdin[4:0] = din[4:0]; |
| 1590 | |
| 1591 | |
| 1592 | |
| 1593 | |
| 1594 | |
| 1595 | |
| 1596 | dff #(5) d0_0 ( |
| 1597 | .l1clk(l1clk), |
| 1598 | .siclk(siclk), |
| 1599 | .soclk(soclk), |
| 1600 | .d(fdin[4:0]), |
| 1601 | .si({scan_in,so[3:0]}), |
| 1602 | .so({so[3:0],scan_out}), |
| 1603 | .q(dout[4:0]) |
| 1604 | ); |
| 1605 | |
| 1606 | |
| 1607 | |
| 1608 | |
| 1609 | |
| 1610 | |
| 1611 | |
| 1612 | |
| 1613 | |
| 1614 | |
| 1615 | |
| 1616 | |
| 1617 | endmodule |
| 1618 | |
| 1619 | |
| 1620 | |
| 1621 | |
| 1622 | |
| 1623 | |
| 1624 | |
| 1625 | |