// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: l2t_dirrep_ctl.v
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
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// ========== Copyright Header End ============================================
dirrep_inval_mask_dcd_c4,
dirrep_dc_rdwr_row_en_c4,
dirrep_dc_rdwr_panel_dec_c4,
dirrep_dc_lkup_row_dec_c4,
dirrep_dc_lkup_panel_dec_c4,
dirrep_wr_dc_dir_entry_c4,
dirrep_inval_mask_icd_c4,
dirrep_ic_rdwr_row_en_c4,
dirrep_ic_rdwr_panel_dec_c4,
dirrep_ic_lkup_row_dec_c4,
dirrep_ic_lkup_panel_dec_c4,
dirrep_wr_ic_dir_entry_c4,
arbadr_arbdp_addr5to4_c3,
arbadr_arbdp_dc_addr4_c4,
arbadr_arbdp_ic_addr4_c4,
arbadr_arbdp_index_ic_addr4_c4,
arbadr_arbdp_index_dc_addr4_c4,
arbadr_arbdp_dir_wr_par_c3,
arb_lkup_bank_ena_dcd_c3,
arb_lkup_bank_ena_icd_c3,
tagd_lkup_row_addr_dcd_c3,
tagd_lkup_row_addr_icd_c3,
csr_oneshot_dir_clear_c3,
wire ff_dir_error_c8_scanin;
wire ff_dir_error_c8_scanout;
wire ff_wr_par_c4_scanin;
wire ff_wr_par_c4_scanout;
wire ff_dir_vld_dcd_c4_l_scanin;
wire ff_dir_vld_dcd_c4_l_scanout;
wire ff_dc_rd_en_c4_scanin;
wire ff_dc_rd_en_c4_scanout;
wire ff_ic_rd_en_c4_scanin;
wire ff_ic_rd_en_c4_scanout;
wire ff_dc_wr_en_c4_scanin;
wire ff_dc_wr_en_c4_scanout;
wire ff_ic_wr_en_c4_scanin;
wire ff_ic_wr_en_c4_scanout;
wire ff_inval_mask_dcd_c4_scanin;
wire ff_inval_mask_dcd_c4_scanout;
wire ff_inval_mask_icd_c4_scanin;
wire ff_inval_mask_icd_c4_scanout;
wire [1:0] arbadr_arbdp_addr5to4_c4;
wire ff_dir_panel_dcd_c4_scanin;
wire ff_dir_panel_dcd_c4_scanout;
wire ff_inval_addrbit4_c4_scanin;
wire ff_inval_addrbit4_c4_scanout;
wire [1:0] arbadr_arbdp_addr5to4_c5;
wire [1:0] arbadr_arbdp_addr5to4_c52;
wire [1:0] arbadr_arbdp_addr5to4_c6;
wire arb_dc_ic_rd_bit_4_c4;
wire arbadr_arbdp_dc_addr4_c4_fnl;
wire ff_dir_panel_icd_c4_scanin;
wire ff_dir_panel_icd_c4_scanout;
wire ff_inval_vld_c78910_scanin;
wire ff_inval_vld_c78910_scanout;
wire ic_invalidation_bit4_flip;
wire arbadr_arbdp_ic_addr4_c4_fnl;
wire ff_lkup_row_addr_dcd_c4_scanin;
wire ff_lkup_row_addr_dcd_c4_scanout;
wire ff_lkup_bank_ena_dcd_c4_scanin;
wire ff_lkup_bank_ena_dcd_c4_scanout;
wire ff_lkup_row_addr_icd_c4_scanin;
wire ff_lkup_row_addr_icd_c4_scanout;
wire ff_lkup_bank_ena_icd_c4_scanin;
wire ff_lkup_bank_ena_icd_c4_scanout;
wire ff_wr_dc_dir_entry_c4_scanin;
wire ff_wr_dc_dir_entry_c4_scanout;
wire ff_wr_ic_dir_entry_c4_scanin;
wire ff_wr_ic_dir_entry_c4_scanout;
wire ff_ic_dir_clear_c4_scanin;
wire ff_ic_dir_clear_c4_scanout;
wire ff_dc_dir_clear_c4_scanin;
wire ff_dc_dir_clear_c4_scanout;
wire fnl_csr_oneshot_dir_clear_c3;
wire ff_l2t_mb0_run_scanin;
wire ff_l2t_mb0_run_scanout;
output dirrep_dir_wr_par_c4;
output dirrep_dir_vld_c4_l;
// D$ directory ( Left Bottom )
output dirrep_dc_rd_en_c4;
output dirrep_dc_wr_en_c4;
output [7:0] dirrep_inval_mask_dcd_c4;
// Read and write addresses require a rd_en/wr_en qualification
output [3:0] dirrep_dc_rdwr_row_en_c4; // bits 4,3 of panel decode (i.e. address 10:9 )
output [3:0] dirrep_dc_rdwr_panel_dec_c4; // dec bits 1:0 of the panel address (i.e. address 5,4 );
// Lkup addresses do not require a qualification as the
// _lkup_row_dec_c4 is actually a qualified vector.
output [3:0] dirrep_dc_lkup_row_dec_c4 ;
output [3:0] dirrep_dc_lkup_panel_dec_c4 ;// use lkup_row_addr_dcd[2:1] dec
output [4:0] dirrep_wr_dc_dir_entry_c4 ; // lsb is arb_dir_panel_dcd[2] , BS and SR 11/18/03 Reverse Directory change
output dirrep_dc_dir_clear_c4; // Bottom left
// ie bit 8 of the address.
// I$ directory ( Left TOp )
output dirrep_ic_rd_en_c4;
output dirrep_ic_wr_en_c4;
output [7:0] dirrep_inval_mask_icd_c4;
// Read and write addresses require a rd_en/wr_en qualification
output [3:0] dirrep_ic_rdwr_row_en_c4; // bits 4,3 of panel decode (i.e. address 10:9 )
output [3:0] dirrep_ic_rdwr_panel_dec_c4; // dec bits 1:0 of the panel address (i.e. address 5,4 );
// Lkup addresses do not require a qualification as the
// _lkup_row_dec_c4 is actually a qualified vector.
output [3:0] dirrep_ic_lkup_row_dec_c4 ; // use lkup_row_addr_dcd[2:1] dec
output [3:0] dirrep_ic_lkup_panel_dec_c4 ;
output [4:0] dirrep_wr_ic_dir_entry_c4 ; // lsb is arb_dir_panel_icd[2], BS and SR 11/18/03 Reverse Directory change
// ie bit 8 of the address.
output dirrep_ic_dir_clear_c4; // Top left
output dirrep_dir_error_c8; // Right
input [3:0] ic_parity_out; // LeftTop ( C7 signal.)
input [3:0] dc_parity_out; // LeftBottom ( C7 signal.)
input [1:0] arbadr_arbdp_addr5to4_c3;
output arbadr_arbdp_addr4_c4;
output arbadr_arbdp_dc_addr4_c4;
output arbadr_arbdp_ic_addr4_c4;
output arbadr_arbdp_index_ic_addr4_c4;
output arbadr_arbdp_index_dc_addr4_c4;
input arb_inval_inst_vld_c3;
input arb_dc_ic_rd_bit_4;
// Use same pin positions as before.
input arbadr_arbdp_dir_wr_par_c3;
input [4:0] arb_dir_panel_dcd_c3;
input [4:0] arb_dir_panel_icd_c3;
input [3:0] arb_lkup_bank_ena_dcd_c3; // translates to a row_en
input [3:0] arb_lkup_bank_ena_icd_c3;
input [7:0] arb_inval_mask_dcd_c3;
input [7:0] arb_inval_mask_icd_c3;
input [4:0] arb_wr_dc_dir_entry_c3;
input [4:0] arb_wr_ic_dir_entry_c3;
input [2:0] tagd_lkup_row_addr_dcd_c3; // translates to a panel enable.
input [2:0] tagd_lkup_row_addr_icd_c3 ;
input arb_ic_inval_vld_c7;
input csr_oneshot_dir_clear_c3;
// BS 2/1/04 : Brought out IC inval signal to separate from IC fill
// because IC fill will load only one panel in 1 row (only one 1 cache waY) while IC inval will write
// to two panels in two rows (2 icache ways) every cycle. This IC dir write enable logic is in
// input arb_ic_inval_wr_en_c3; // from l2t_arb_ctl
// output dirrep_ic_inval_wr_en_c4; // to l2t_dir_ctl modules
//////////////////////////////////////////////////
//////////////////////////////////////////////////
assign pce_ov = tcu_pce_ov;
l2t_dirrep_ctl_l1clkhdr_ctl_macro clkgen (
//////////////////////////////////////////////////
//////////////////////////////////////////
//////////////////////////////////////////
l2t_dirrep_ctl_spare_ctl_macro__num_5 spares (
.scan_out(spares_scanout),
//////////////////////////////////////////
wire [4:0] dir_panel_dcd_c4, dir_panel_icd_c4 ;
wire [2:0] lkup_row_addr_dcd_c4, lkup_row_addr_icd_c4;
assign dir_error_c7 = (|(ic_parity_out)) | (|(dc_parity_out)) ;
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dir_error_c8
(.dout (dirrep_dir_error_c8),
.scan_in(ff_dir_error_c8_scanin),
.scan_out(ff_dir_error_c8_scanout),
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_wr_par_c4
(.dout (dirrep_dir_wr_par_c4),
.scan_in(ff_wr_par_c4_scanin),
.scan_out(ff_wr_par_c4_scanout),
.din (arbadr_arbdp_dir_wr_par_c3),
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dir_vld_dcd_c4_l
(.dout (dirrep_dir_vld_c4_l),
.scan_in(ff_dir_vld_dcd_c4_l_scanin),
.scan_out(ff_dir_vld_dcd_c4_l_scanout),
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dc_rd_en_c4
(.dout (dirrep_dc_rd_en_c4),
.scan_in(ff_dc_rd_en_c4_scanin),
.scan_out(ff_dc_rd_en_c4_scanout),
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_ic_rd_en_c4
(.dout (dirrep_ic_rd_en_c4),
.scan_in(ff_ic_rd_en_c4_scanin),
.scan_out(ff_ic_rd_en_c4_scanout),
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dc_wr_en_c4
(.dout (dirrep_dc_wr_en_c4),
.scan_in(ff_dc_wr_en_c4_scanin),
.scan_out(ff_dc_wr_en_c4_scanout),
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_ic_wr_en_c4
(.dout (dirrep_ic_wr_en_c4),
.scan_in(ff_ic_wr_en_c4_scanin),
.scan_out(ff_ic_wr_en_c4_scanout),
//// BS 2/1/04 : Flop arb_ic_inval_wr_en_c3 to generate a C4 signal
//msff_ctl_macro ff_ic_inval_wr_en_c4 (width=1)
// (.dout (dirrep_ic_inval_wr_en_c4),
// .scan_in(ff_ic_inval_wr_en_c4_scanin),
// .scan_out(ff_ic_inval_wr_en_c4_scanout),
// .din (arb_ic_inval_wr_en_c3),
l2t_dirrep_ctl_msff_ctl_macro__width_8 ff_inval_mask_dcd_c4
(.dout (dirrep_inval_mask_dcd_c4[7:0]),
.scan_in(ff_inval_mask_dcd_c4_scanin),
.scan_out(ff_inval_mask_dcd_c4_scanout),
.din (arb_inval_mask_dcd_c3[7:0]),
l2t_dirrep_ctl_msff_ctl_macro__width_8 ff_inval_mask_icd_c4
(.dout (dirrep_inval_mask_icd_c4[7:0]),
.scan_in(ff_inval_mask_icd_c4_scanin),
.scan_out(ff_inval_mask_icd_c4_scanout),
.din (arb_inval_mask_icd_c3[7:0]),
///////////////////////////////////////////////////////////
// RD Write row and panel enables.
// Row is dtermined by the lower order bits of the
// ie bits 5,4 for the I$
// ie bits 5,11 for the D$.
// Panel is determined by address bits 10,9
///////////////////////////////////////////////////////////
l2t_dirrep_ctl_msff_ctl_macro__width_6 ff_dir_panel_dcd_c4
(.dout ({arbadr_arbdp_addr5to4_c4[1:0],dir_panel_dcd_c4[4:3], dir_panel_dcd_c4[1:0]}),
.scan_in(ff_dir_panel_dcd_c4_scanin),
.scan_out(ff_dir_panel_dcd_c4_scanout),
.din ({arbadr_arbdp_addr5to4_c3[1:0],arb_dir_panel_dcd_c3[4:3],arb_dir_panel_dcd_c3[1:0]}),
// Directory restructuring
l2t_dirrep_ctl_msff_ctl_macro__width_11 ff_inval_addrbit4_c4
.scan_in(ff_inval_addrbit4_c4_scanin),
.scan_out(ff_inval_addrbit4_c4_scanout),
.dout ({inval_inst_vld_c4,inval_inst_vld_c5,inval_inst_vld_c52,inval_inst_vld_c6,
arbadr_arbdp_addr5to4_c5[1:0],arbadr_arbdp_addr5to4_c52[1:0],
arbadr_arbdp_addr5to4_c6[1:0],arb_dc_ic_rd_bit_4_c4}),
.din ({arb_inval_inst_vld_c3,inval_inst_vld_c4,inval_inst_vld_c5,inval_inst_vld_c52,
arbadr_arbdp_addr5to4_c4[1:0],arbadr_arbdp_addr5to4_c5[1:0],
arbadr_arbdp_addr5to4_c52[1:0],arb_dc_ic_rd_bit_4}),
assign def_inval_entry = ~( inval_inst_vld_c5 | inval_inst_vld_c52 | inval_inst_vld_c6 ) ;
l2t_dirrep_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_1 mux_inval_dc_panel_c3
.dout (arbadr_arbdp_dc_addr4_c4_fnl),
.din0(arbadr_arbdp_addr5to4_c4[0]), .din1(arbadr_arbdp_addr5to4_c5[0]),
.din2(arbadr_arbdp_addr5to4_c52[0]), .din3(arbadr_arbdp_addr5to4_c6[0]),
.sel0(def_inval_entry), .sel1(inval_inst_vld_c5),
.sel2(inval_inst_vld_c52), .sel3(inval_inst_vld_c6));
//assign arbadr_arbdp_dc_addr4_c4 = dirrep_dc_rd_en_c4 ? arb_dc_ic_rd_bit_4 : arbadr_arbdp_dc_addr4_c4_fnl ;
assign arbadr_arbdp_dc_addr4_c4 = arbadr_arbdp_dc_addr4_c4_fnl ;
assign arbadr_arbdp_index_dc_addr4_c4 = arb_dc_ic_rd_bit_4_c4;
assign arbadr_arbdp_addr4_c4 = arbadr_arbdp_addr5to4_c4[0];
//assign dirrep_dc_rdwr_panel_dec_c4[0] = ( dir_panel_dcd_c4[4:3] == 2'd0 );
//assign dirrep_dc_rdwr_panel_dec_c4[1] = ( dir_panel_dcd_c4[4:3] == 2'd1 );
//assign dirrep_dc_rdwr_panel_dec_c4[2] = ( dir_panel_dcd_c4[4:3] == 2'd2 );
//assign dirrep_dc_rdwr_panel_dec_c4[3] = ( dir_panel_dcd_c4[4:3] == 2'd3 );
assign dirrep_dc_rdwr_panel_dec_c4[0] = ~dir_panel_dcd_c4[4] & ~dir_panel_dcd_c4[3] ;
assign dirrep_dc_rdwr_panel_dec_c4[1] = ~dir_panel_dcd_c4[4] & dir_panel_dcd_c4[3] ;
assign dirrep_dc_rdwr_panel_dec_c4[2] = dir_panel_dcd_c4[4] & ~dir_panel_dcd_c4[3] ;
assign dirrep_dc_rdwr_panel_dec_c4[3] = dir_panel_dcd_c4[4] & dir_panel_dcd_c4[3] ;
assign dirrep_dc_rdwr_row_en_c4[0] = (dir_panel_dcd_c4[1:0] == 2'd0 );
assign dirrep_dc_rdwr_row_en_c4[1] = (dir_panel_dcd_c4[1:0] == 2'd1 );
assign dirrep_dc_rdwr_row_en_c4[2] = (dir_panel_dcd_c4[1:0] == 2'd2 );
assign dirrep_dc_rdwr_row_en_c4[3] = (dir_panel_dcd_c4[1:0] == 2'd3 );
l2t_dirrep_ctl_msff_ctl_macro__width_4 ff_dir_panel_icd_c4
(.dout ({dir_panel_icd_c4[4:3],dir_panel_icd_c4[1:0]}),
.scan_in(ff_dir_panel_icd_c4_scanin),
.scan_out(ff_dir_panel_icd_c4_scanout),
.din ({arb_dir_panel_icd_c3[4:3],arb_dir_panel_icd_c3[1:0]}),
assign dirrep_ic_rdwr_panel_dec_c4[0] = ( dir_panel_icd_c4[4:3] == 2'd0 );
assign dirrep_ic_rdwr_panel_dec_c4[1] = ( dir_panel_icd_c4[4:3] == 2'd1 );
assign dirrep_ic_rdwr_panel_dec_c4[2] = ( dir_panel_icd_c4[4:3] == 2'd2 );
assign dirrep_ic_rdwr_panel_dec_c4[3] = ( dir_panel_icd_c4[4:3] == 2'd3 );
assign dirrep_ic_rdwr_row_en_c4[0] = (dir_panel_icd_c4[1:0] == 2'd0 );
assign dirrep_ic_rdwr_row_en_c4[1] = (dir_panel_icd_c4[1:0] == 2'd1 );
assign dirrep_ic_rdwr_row_en_c4[2] = (dir_panel_icd_c4[1:0] == 2'd2 );
assign dirrep_ic_rdwr_row_en_c4[3] = (dir_panel_icd_c4[1:0] == 2'd3 );
// Dir changes Bit 4 computation for inval case is different
l2t_dirrep_ctl_msff_ctl_macro__width_3 ff_inval_vld_c78910
.scan_in(ff_inval_vld_c78910_scanin),
.scan_out(ff_inval_vld_c78910_scanout),
.din ({arb_ic_inval_vld_c7,ic_inval_vld_c8,ic_inval_vld_c9}),
.dout ({ic_inval_vld_c8,ic_inval_vld_c9,ic_inval_vld_c10}),
assign ic_invalidation_bit4_flip = arb_ic_inval_vld_c7 | ic_inval_vld_c8 | ic_inval_vld_c9 | ic_inval_vld_c10;
// OLD :: assign arbadr_arbdp_ic_addr4_c4 = dir_panel_icd_c4[0];
assign arbadr_arbdp_ic_addr4_c4_fnl = ic_invalidation_bit4_flip ? ~dir_panel_icd_c4[0] : dir_panel_icd_c4[0] ;
//assign arbadr_arbdp_ic_addr4_c4 = dirrep_ic_rd_en_c4 ? arb_dc_ic_rd_bit_4 : arbadr_arbdp_ic_addr4_c4_fnl ;
assign arbadr_arbdp_ic_addr4_c4 = arbadr_arbdp_ic_addr4_c4_fnl ;
assign arbadr_arbdp_index_ic_addr4_c4 = arb_dc_ic_rd_bit_4_c4 ;
///////////////////////////////////////////////////////////
// lkup row and panel enables.
// Lkup row coming from tagd corresponds to
// address bits <10:8> of the lkup address.
// The bits <10:9> actually go into determining
// the panel id within the directory.
///////////////////////////////////////////////////////////
l2t_dirrep_ctl_msff_ctl_macro__width_3 ff_lkup_row_addr_dcd_c4
(.dout (lkup_row_addr_dcd_c4[2:0]),
.scan_in(ff_lkup_row_addr_dcd_c4_scanin),
.scan_out(ff_lkup_row_addr_dcd_c4_scanout),
.din (tagd_lkup_row_addr_dcd_c3[2:0]),
assign dirrep_dc_lkup_panel_dec_c4[0] = ( lkup_row_addr_dcd_c4[1:0] == 2'd0 );
assign dirrep_dc_lkup_panel_dec_c4[1] = ( lkup_row_addr_dcd_c4[1:0] == 2'd1 );
assign dirrep_dc_lkup_panel_dec_c4[2] = ( lkup_row_addr_dcd_c4[1:0] == 2'd2 );
assign dirrep_dc_lkup_panel_dec_c4[3] = ( lkup_row_addr_dcd_c4[1:0] == 2'd3 );
l2t_dirrep_ctl_msff_ctl_macro__width_4 ff_lkup_bank_ena_dcd_c4
(.dout (dirrep_dc_lkup_row_dec_c4[3:0]),
.scan_in(ff_lkup_bank_ena_dcd_c4_scanin),
.scan_out(ff_lkup_bank_ena_dcd_c4_scanout),
.din (arb_lkup_bank_ena_dcd_c3[3:0]),
l2t_dirrep_ctl_msff_ctl_macro__width_3 ff_lkup_row_addr_icd_c4
(.dout (lkup_row_addr_icd_c4[2:0]),
.scan_in(ff_lkup_row_addr_icd_c4_scanin),
.scan_out(ff_lkup_row_addr_icd_c4_scanout),
.din (tagd_lkup_row_addr_icd_c3[2:0]),
assign dirrep_ic_lkup_panel_dec_c4[0] = ( lkup_row_addr_icd_c4[1:0] == 2'd0 );
assign dirrep_ic_lkup_panel_dec_c4[1] = ( lkup_row_addr_icd_c4[1:0] == 2'd1 );
assign dirrep_ic_lkup_panel_dec_c4[2] = ( lkup_row_addr_icd_c4[1:0] == 2'd2 );
assign dirrep_ic_lkup_panel_dec_c4[3] = ( lkup_row_addr_icd_c4[1:0] == 2'd3 );
l2t_dirrep_ctl_msff_ctl_macro__width_4 ff_lkup_bank_ena_icd_c4
(.dout (dirrep_ic_lkup_row_dec_c4[3:0]),
.scan_in(ff_lkup_bank_ena_icd_c4_scanin),
.scan_out(ff_lkup_bank_ena_icd_c4_scanout),
.din (arb_lkup_bank_ena_icd_c3[3:0]),
l2t_dirrep_ctl_msff_ctl_macro__width_5 ff_wr_dc_dir_entry_c4 // BS and SR 11/18/03 Reverse Directory change
(.dout (dirrep_wr_dc_dir_entry_c4[4:0]),
.scan_in(ff_wr_dc_dir_entry_c4_scanin),
.scan_out(ff_wr_dc_dir_entry_c4_scanout),
.din (arb_wr_dc_dir_entry_c3[4:0]), // BS and SR 11/18/03 Reverse Directory change
l2t_dirrep_ctl_msff_ctl_macro__width_5 ff_wr_ic_dir_entry_c4 // BS and SR 11/18/03 Reverse Directory change
(.dout (dirrep_wr_ic_dir_entry_c4[4:0]),
.scan_in(ff_wr_ic_dir_entry_c4_scanin),
.scan_out(ff_wr_ic_dir_entry_c4_scanout),
.din (arb_wr_ic_dir_entry_c3[4:0]), // BS and SR 11/18/03 Reverse Directory change
///////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_ic_dir_clear_c4
(.dout (dirrep_ic_dir_clear_c4),
.scan_in(ff_ic_dir_clear_c4_scanin),
.scan_out(ff_ic_dir_clear_c4_scanout),
.din (reset_dir_cams_c3),
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_dc_dir_clear_c4
(.dout (dirrep_dc_dir_clear_c4),
.scan_in(ff_dc_dir_clear_c4_scanin),
.scan_out(ff_dc_dir_clear_c4_scanout),
.din (reset_dir_cams_c3),
assign fnl_csr_oneshot_dir_clear_c3 = l2t_mb0_run_r1 ? 1'b0 : csr_oneshot_dir_clear_c3;
assign reset_dir_cams_c3 = fnl_csr_oneshot_dir_clear_c3 | ~por_l;
l2t_dirrep_ctl_msff_ctl_macro__width_1 ff_l2t_mb0_run
.scan_in(ff_l2t_mb0_run_scanin),
.scan_out(ff_l2t_mb0_run_scanout),
assign spares_scanin = scan_in ;
assign ff_dir_error_c8_scanin = spares_scanout ;
assign ff_wr_par_c4_scanin = ff_dir_error_c8_scanout ;
assign ff_dir_vld_dcd_c4_l_scanin = ff_wr_par_c4_scanout ;
assign ff_dc_rd_en_c4_scanin = ff_dir_vld_dcd_c4_l_scanout;
assign ff_ic_rd_en_c4_scanin = ff_dc_rd_en_c4_scanout ;
assign ff_dc_wr_en_c4_scanin = ff_ic_rd_en_c4_scanout ;
assign ff_ic_wr_en_c4_scanin = ff_dc_wr_en_c4_scanout ;
assign ff_inval_mask_dcd_c4_scanin = ff_ic_wr_en_c4_scanout ;
assign ff_inval_mask_icd_c4_scanin = ff_inval_mask_dcd_c4_scanout;
assign ff_dir_panel_dcd_c4_scanin = ff_inval_mask_icd_c4_scanout;
assign ff_inval_addrbit4_c4_scanin = ff_dir_panel_dcd_c4_scanout;
assign ff_dir_panel_icd_c4_scanin = ff_inval_addrbit4_c4_scanout;
assign ff_inval_vld_c78910_scanin = ff_dir_panel_icd_c4_scanout;
assign ff_lkup_row_addr_dcd_c4_scanin = ff_inval_vld_c78910_scanout;
assign ff_lkup_bank_ena_dcd_c4_scanin = ff_lkup_row_addr_dcd_c4_scanout;
assign ff_lkup_row_addr_icd_c4_scanin = ff_lkup_bank_ena_dcd_c4_scanout;
assign ff_lkup_bank_ena_icd_c4_scanin = ff_lkup_row_addr_icd_c4_scanout;
assign ff_wr_dc_dir_entry_c4_scanin = ff_lkup_bank_ena_icd_c4_scanout;
assign ff_wr_ic_dir_entry_c4_scanin = ff_wr_dc_dir_entry_c4_scanout;
assign ff_ic_dir_clear_c4_scanin = ff_wr_ic_dir_entry_c4_scanout;
assign ff_dc_dir_clear_c4_scanin = ff_ic_dir_clear_c4_scanout;
assign ff_l2t_mb0_run_scanin = ff_dc_dir_clear_c4_scanout;
assign scan_out = ff_l2t_mb0_run_scanout ;
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_l1clkhdr_ctl_macro (
// Description: Spare gate macro for control blocks
// Param num controls the number of times the macro is added
// flops=0 can be used to use only combination spare logic
module l2t_dirrep_ctl_spare_ctl_macro__num_5 (
wire spare0_buf_32x_unused;
wire spare0_nand3_8x_unused;
wire spare0_inv_8x_unused;
wire spare0_aoi22_4x_unused;
wire spare0_buf_8x_unused;
wire spare0_oai22_4x_unused;
wire spare0_inv_16x_unused;
wire spare0_nand2_16x_unused;
wire spare0_nor3_4x_unused;
wire spare0_nand2_8x_unused;
wire spare0_buf_16x_unused;
wire spare0_nor2_16x_unused;
wire spare0_inv_32x_unused;
wire spare1_buf_32x_unused;
wire spare1_nand3_8x_unused;
wire spare1_inv_8x_unused;
wire spare1_aoi22_4x_unused;
wire spare1_buf_8x_unused;
wire spare1_oai22_4x_unused;
wire spare1_inv_16x_unused;
wire spare1_nand2_16x_unused;
wire spare1_nor3_4x_unused;
wire spare1_nand2_8x_unused;
wire spare1_buf_16x_unused;
wire spare1_nor2_16x_unused;
wire spare1_inv_32x_unused;
wire spare2_buf_32x_unused;
wire spare2_nand3_8x_unused;
wire spare2_inv_8x_unused;
wire spare2_aoi22_4x_unused;
wire spare2_buf_8x_unused;
wire spare2_oai22_4x_unused;
wire spare2_inv_16x_unused;
wire spare2_nand2_16x_unused;
wire spare2_nor3_4x_unused;
wire spare2_nand2_8x_unused;
wire spare2_buf_16x_unused;
wire spare2_nor2_16x_unused;
wire spare2_inv_32x_unused;
wire spare3_buf_32x_unused;
wire spare3_nand3_8x_unused;
wire spare3_inv_8x_unused;
wire spare3_aoi22_4x_unused;
wire spare3_buf_8x_unused;
wire spare3_oai22_4x_unused;
wire spare3_inv_16x_unused;
wire spare3_nand2_16x_unused;
wire spare3_nor3_4x_unused;
wire spare3_nand2_8x_unused;
wire spare3_buf_16x_unused;
wire spare3_nor2_16x_unused;
wire spare3_inv_32x_unused;
wire spare4_buf_32x_unused;
wire spare4_nand3_8x_unused;
wire spare4_inv_8x_unused;
wire spare4_aoi22_4x_unused;
wire spare4_buf_8x_unused;
wire spare4_oai22_4x_unused;
wire spare4_inv_16x_unused;
wire spare4_nand2_16x_unused;
wire spare4_nor3_4x_unused;
wire spare4_nand2_8x_unused;
wire spare4_buf_16x_unused;
wire spare4_nor2_16x_unused;
wire spare4_inv_32x_unused;
cl_sc1_msff_8x spare0_flop (.l1clk(l1clk),
cl_u1_buf_32x spare0_buf_32x (.in(1'b1),
.out(spare0_buf_32x_unused));
cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1),
.out(spare0_nand3_8x_unused));
cl_u1_inv_8x spare0_inv_8x (.in(1'b1),
.out(spare0_inv_8x_unused));
cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1),
.out(spare0_aoi22_4x_unused));
cl_u1_buf_8x spare0_buf_8x (.in(1'b1),
.out(spare0_buf_8x_unused));
cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1),
.out(spare0_oai22_4x_unused));
cl_u1_inv_16x spare0_inv_16x (.in(1'b1),
.out(spare0_inv_16x_unused));
cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1),
.out(spare0_nand2_16x_unused));
cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0),
.out(spare0_nor3_4x_unused));
cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1),
.out(spare0_nand2_8x_unused));
cl_u1_buf_16x spare0_buf_16x (.in(1'b1),
.out(spare0_buf_16x_unused));
cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0),
.out(spare0_nor2_16x_unused));
cl_u1_inv_32x spare0_inv_32x (.in(1'b1),
.out(spare0_inv_32x_unused));
cl_sc1_msff_8x spare1_flop (.l1clk(l1clk),
cl_u1_buf_32x spare1_buf_32x (.in(1'b1),
.out(spare1_buf_32x_unused));
cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1),
.out(spare1_nand3_8x_unused));
cl_u1_inv_8x spare1_inv_8x (.in(1'b1),
.out(spare1_inv_8x_unused));
cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1),
.out(spare1_aoi22_4x_unused));
cl_u1_buf_8x spare1_buf_8x (.in(1'b1),
.out(spare1_buf_8x_unused));
cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1),
.out(spare1_oai22_4x_unused));
cl_u1_inv_16x spare1_inv_16x (.in(1'b1),
.out(spare1_inv_16x_unused));
cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1),
.out(spare1_nand2_16x_unused));
cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0),
.out(spare1_nor3_4x_unused));
cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1),
.out(spare1_nand2_8x_unused));
cl_u1_buf_16x spare1_buf_16x (.in(1'b1),
.out(spare1_buf_16x_unused));
cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0),
.out(spare1_nor2_16x_unused));
cl_u1_inv_32x spare1_inv_32x (.in(1'b1),
.out(spare1_inv_32x_unused));
cl_sc1_msff_8x spare2_flop (.l1clk(l1clk),
cl_u1_buf_32x spare2_buf_32x (.in(1'b1),
.out(spare2_buf_32x_unused));
cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1),
.out(spare2_nand3_8x_unused));
cl_u1_inv_8x spare2_inv_8x (.in(1'b1),
.out(spare2_inv_8x_unused));
cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1),
.out(spare2_aoi22_4x_unused));
cl_u1_buf_8x spare2_buf_8x (.in(1'b1),
.out(spare2_buf_8x_unused));
cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1),
.out(spare2_oai22_4x_unused));
cl_u1_inv_16x spare2_inv_16x (.in(1'b1),
.out(spare2_inv_16x_unused));
cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1),
.out(spare2_nand2_16x_unused));
cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0),
.out(spare2_nor3_4x_unused));
cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1),
.out(spare2_nand2_8x_unused));
cl_u1_buf_16x spare2_buf_16x (.in(1'b1),
.out(spare2_buf_16x_unused));
cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0),
.out(spare2_nor2_16x_unused));
cl_u1_inv_32x spare2_inv_32x (.in(1'b1),
.out(spare2_inv_32x_unused));
cl_sc1_msff_8x spare3_flop (.l1clk(l1clk),
cl_u1_buf_32x spare3_buf_32x (.in(1'b1),
.out(spare3_buf_32x_unused));
cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1),
.out(spare3_nand3_8x_unused));
cl_u1_inv_8x spare3_inv_8x (.in(1'b1),
.out(spare3_inv_8x_unused));
cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1),
.out(spare3_aoi22_4x_unused));
cl_u1_buf_8x spare3_buf_8x (.in(1'b1),
.out(spare3_buf_8x_unused));
cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1),
.out(spare3_oai22_4x_unused));
cl_u1_inv_16x spare3_inv_16x (.in(1'b1),
.out(spare3_inv_16x_unused));
cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1),
.out(spare3_nand2_16x_unused));
cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0),
.out(spare3_nor3_4x_unused));
cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1),
.out(spare3_nand2_8x_unused));
cl_u1_buf_16x spare3_buf_16x (.in(1'b1),
.out(spare3_buf_16x_unused));
cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0),
.out(spare3_nor2_16x_unused));
cl_u1_inv_32x spare3_inv_32x (.in(1'b1),
.out(spare3_inv_32x_unused));
cl_sc1_msff_8x spare4_flop (.l1clk(l1clk),
cl_u1_buf_32x spare4_buf_32x (.in(1'b1),
.out(spare4_buf_32x_unused));
cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1),
.out(spare4_nand3_8x_unused));
cl_u1_inv_8x spare4_inv_8x (.in(1'b1),
.out(spare4_inv_8x_unused));
cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1),
.out(spare4_aoi22_4x_unused));
cl_u1_buf_8x spare4_buf_8x (.in(1'b1),
.out(spare4_buf_8x_unused));
cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1),
.out(spare4_oai22_4x_unused));
cl_u1_inv_16x spare4_inv_16x (.in(1'b1),
.out(spare4_inv_16x_unused));
cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1),
.out(spare4_nand2_16x_unused));
cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0),
.out(spare4_nor3_4x_unused));
cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1),
.out(spare4_nand2_8x_unused));
cl_u1_buf_16x spare4_buf_16x (.in(1'b1),
.out(spare4_buf_16x_unused));
cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0),
.out(spare4_nor2_16x_unused));
cl_u1_inv_32x spare4_inv_32x (.in(1'b1),
.out(spare4_inv_32x_unused));
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_msff_ctl_macro__width_1 (
assign fdin[0:0] = din[0:0];
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_msff_ctl_macro__width_8 (
assign fdin[7:0] = din[7:0];
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_msff_ctl_macro__width_6 (
assign fdin[5:0] = din[5:0];
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_msff_ctl_macro__width_11 (
assign fdin[10:0] = din[10:0];
// general mux macro for pass-gate and and-or muxes with/wout priority encoders
// also for pass-gate with decoder
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_mux_ctl_macro__mux_aonpe__ports_4__width_1 (
assign dout[0:0] = ( {1{sel0}} & din0[0:0] ) |
( {1{sel1}} & din1[0:0]) |
( {1{sel2}} & din2[0:0]) |
( {1{sel3}} & din3[0:0]);
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_msff_ctl_macro__width_4 (
assign fdin[3:0] = din[3:0];
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_msff_ctl_macro__width_3 (
assign fdin[2:0] = din[2:0];
// any PARAMS parms go into naming of macro
module l2t_dirrep_ctl_msff_ctl_macro__width_5 (
assign fdin[4:0] = din[4:0];
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