| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: fc_jtpor.if.vrh |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #ifndef INC_FC_JTPOR_IF_VRH |
| 36 | #define INC_FC_JTPOR_IF_VRH |
| 37 | |
| 38 | #include <vera_defines.vrh> |
| 39 | #include "fc_top_defines.vri" |
| 40 | //#include "dbg_dq_pins_defines.vri" |
| 41 | //#include "pkg.port.vri" |
| 42 | //#include "pkg.if.vri" |
| 43 | |
| 44 | //#include "tcu_top_defines.vri" |
| 45 | #define INPUT_EDGE PSAMPLE |
| 46 | #define INPUT_SKEW #-3 |
| 47 | #define OUTPUT_EDGE_N NHOLD |
| 48 | // #include <tcu_top_defines.vri> |
| 49 | |
| 50 | |
| 51 | // interface rst_iol2clk { |
| 52 | // input clk_iol2clk CLOCK verilog_node "`RST.iol2clk"; |
| 53 | // input rst_ncu_unpark_thread INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_ncu_unpark_thread"; |
| 54 | // } |
| 55 | // |
| 56 | // interface rst_l2clk { |
| 57 | // input clk_l2clk CLOCK verilog_node "`RST.l2clk"; |
| 58 | // input ccu_rst_sync_stable INPUT_EDGE INPUT_SKEW verilog_node "`RST.ccu_rst_sync_stable"; |
| 59 | // input tcu_rst_asicflush_stop_ack INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_asicflush_stop_ack"; |
| 60 | // input rst_tcu_asicflush_stop_req INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_tcu_asicflush_stop_req"; |
| 61 | // input rst_tcu_flush_stop_req INPUT_EDGE INPUT_SKEW verilog_node "`RST.rst_tcu_flush_stop_req"; |
| 62 | // input tcu_rst_efu_done INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_efu_done"; |
| 63 | // input tcu_bisx_done INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_bisx_done"; |
| 64 | // input tcu_rst_flush_init_ack INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_flush_init_ack"; |
| 65 | // input tcu_rst_flush_stop_ack INPUT_EDGE INPUT_SKEW verilog_node "`RST.tcu_rst_flush_stop_ack"; |
| 66 | // |
| 67 | // } |
| 68 | // |
| 69 | // |
| 70 | // |
| 71 | // |
| 72 | // port RST_port { |
| 73 | // clk_l2clk; |
| 74 | // ccu_rst_sync_stable; |
| 75 | // tcu_rst_asicflush_stop_ack; |
| 76 | // rst_tcu_asicflush_stop_req; |
| 77 | // rst_tcu_flush_stop_req; |
| 78 | // tcu_rst_efu_done; |
| 79 | // tcu_bisx_done; |
| 80 | // tcu_rst_flush_init_ack; |
| 81 | // rst_ncu_unpark_thread; |
| 82 | // tcu_rst_flush_stop_ack; |
| 83 | // } |
| 84 | // |
| 85 | // bind RST_port rst_bind { |
| 86 | // clk_l2clk rst_l2clk.clk_l2clk; |
| 87 | // ccu_rst_sync_stable rst_l2clk.ccu_rst_sync_stable; |
| 88 | // tcu_rst_asicflush_stop_ack rst_l2clk.tcu_rst_asicflush_stop_ack; |
| 89 | // rst_tcu_asicflush_stop_req rst_l2clk.rst_tcu_asicflush_stop_req; |
| 90 | // rst_tcu_flush_stop_req rst_l2clk.rst_tcu_flush_stop_req; |
| 91 | // tcu_rst_efu_done rst_l2clk.tcu_rst_efu_done; |
| 92 | // tcu_bisx_done rst_l2clk.tcu_bisx_done; |
| 93 | // tcu_rst_flush_init_ack rst_l2clk.tcu_rst_flush_init_ack; |
| 94 | // rst_ncu_unpark_thread rst_iol2clk.rst_ncu_unpark_thread; |
| 95 | // tcu_rst_flush_stop_ack rst_l2clk.tcu_rst_flush_stop_ack; |
| 96 | // } |
| 97 | |
| 98 | interface bscann { |
| 99 | input TCK CLOCK verilog_node "`TOP.tck" ; |
| 100 | } |
| 101 | |
| 102 | port BSCAN_port { |
| 103 | tck; |
| 104 | } |
| 105 | |
| 106 | bind BSCAN_port bscann_bind { |
| 107 | tck bscann.TCK; |
| 108 | } |
| 109 | |
| 110 | |
| 111 | interface ccu_pll_sys_clk_p_ifn { |
| 112 | input pll_sys_clk_p PSAMPLE #-1 verilog_node "`CCU.pll_sys_clk_p"; |
| 113 | } |
| 114 | |
| 115 | port CCU_clk_portn { |
| 116 | sys_clk; |
| 117 | } |
| 118 | |
| 119 | bind CCU_clk_portn ccu_clk_bindn { |
| 120 | sys_clk ccu_pll_sys_clk_p_ifn.pll_sys_clk_p; |
| 121 | } |
| 122 | |
| 123 | |
| 124 | interface efusen { |
| 125 | input [6:0] sbc_efa_word_addr INPUT_EDGE INPUT_SKEW verilog_node "`EFU.sbc_efa_word_addr"; |
| 126 | } |
| 127 | |
| 128 | port EFUSE_port { |
| 129 | efusen_sbc_efa_word_addr; |
| 130 | } |
| 131 | |
| 132 | bind EFUSE_port efusen_bind { |
| 133 | efusen_sbc_efa_word_addr efusen.sbc_efa_word_addr; |
| 134 | } |
| 135 | |
| 136 | interface pkgn_if { |
| 137 | input clk CLOCK verilog_node "`CPU.PLL_CMP_CLK_P"; // review: need to use an always running IO2X clk |
| 138 | input TRIGOUT PSAMPLE #-1 verilog_node "`CPU.TRIGOUT"; |
| 139 | output [165:0] DBG_DQ_out NHOLD verilog_node "`CPU.DBG_DQ"; |
| 140 | } |
| 141 | |
| 142 | port PKGn_port { |
| 143 | TRIGOUTn; |
| 144 | DBG_DQ_outn; |
| 145 | } |
| 146 | |
| 147 | bind PKGn_port pkgn_bind { |
| 148 | TRIGOUTn pkgn_if.TRIGOUT; |
| 149 | DBG_DQ_outn pkgn_if.DBG_DQ_out; |
| 150 | } |
| 151 | //[136] |
| 152 | |
| 153 | // interface sc { |
| 154 | // input clk CLOCK verilog_node "`CPU.PLL_CMP_CLK_P"; |
| 155 | // output POR_L OUTPUT_EDGE_N verilog_node "`CPU.PWRON_RST_L"; |
| 156 | // output PB_XIR_L OUTPUT_EDGE_N verilog_node "`CPU.BUTTON_XIR_L"; |
| 157 | // output PB_RST_L OUTPUT_EDGE_N verilog_node "`CPU.PB_RST_L"; |
| 158 | // output TRST_L OUTPUT_EDGE_N verilog_node "`CPU.TRST_L"; |
| 159 | // } |
| 160 | // |
| 161 | // port SC_port { |
| 162 | // clk; |
| 163 | // por_; |
| 164 | // pb_xir_; |
| 165 | // pb_rst_; |
| 166 | // trst_l; |
| 167 | // } |
| 168 | // |
| 169 | // bind SC_port sc_bind { |
| 170 | // clk sc.clk; |
| 171 | // por_ sc.POR_L; |
| 172 | // pb_xir_ sc.PB_XIR_L; |
| 173 | // pb_rst_ sc.PB_RST_L; |
| 174 | // trst_l sc.TRST_L; |
| 175 | // } |
| 176 | |
| 177 | interface mbistn { |
| 178 | // input TCK CLOCK verilog_node "`TCU.gclk"; |
| 179 | input mbist_l2tag_read_l2t0 INPUT_EDGE INPUT_SKEW verilog_node "`CPU.l2t0.mbist.mbist_l2tag_read"; |
| 180 | } |
| 181 | |
| 182 | port MBIST_port { |
| 183 | mbistn_l2tag_read_l2t0; |
| 184 | } |
| 185 | |
| 186 | bind MBIST_port mbistn_bind { |
| 187 | mbistn_l2tag_read_l2t0 mbistn.mbist_l2tag_read_l2t0; |
| 188 | } |
| 189 | |
| 190 | |
| 191 | |
| 192 | |
| 193 | #endif |
| 194 | |