verif/env/fc/vera/interfaces/fc_jtpor.if.vrh

// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T2 Processor File: fc_jtpor.if.vrh
// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
//
// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; version 2 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
//
// For the avoidance of doubt, and except that if any non-GPL license
// choice is available it will apply instead, Sun elects to use only
// the General Public License version 2 (GPLv2) at this time for any
// software where a choice of GPL license versions is made
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// ========== Copyright Header End ============================================
#ifndef INC_FC_JTPOR_IF_VRH
#define INC_FC_JTPOR_IF_VRH

#include <vera_defines.vrh>
#include "fc_top_defines.vri"
//#include "dbg_dq_pins_defines.vri"
//#include "pkg.port.vri"
//#include "pkg.if.vri"

//#include "tcu_top_defines.vri"
#define INPUT_EDGE   PSAMPLE
#define INPUT_SKEW   #-3
#define OUTPUT_EDGE_N  NHOLD
//      #include <tcu_top_defines.vri>


// interface rst_iol2clk {
//   input       clk_iol2clk                    CLOCK                           verilog_node "`RST.iol2clk";
//   input       rst_ncu_unpark_thread          INPUT_EDGE INPUT_SKEW       verilog_node "`RST.rst_ncu_unpark_thread";
// }
//
// interface rst_l2clk {
//   input       clk_l2clk                      CLOCK                          verilog_node "`RST.l2clk";
//   input       ccu_rst_sync_stable            INPUT_EDGE INPUT_SKEW       verilog_node "`RST.ccu_rst_sync_stable";
//   input       tcu_rst_asicflush_stop_ack  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.tcu_rst_asicflush_stop_ack";
//   input       rst_tcu_asicflush_stop_req  INPUT_EDGE INPUT_SKEW          verilog_node "`RST.rst_tcu_asicflush_stop_req";
//   input       rst_tcu_flush_stop_req         INPUT_EDGE INPUT_SKEW       verilog_node "`RST.rst_tcu_flush_stop_req";
//   input       tcu_rst_efu_done               INPUT_EDGE INPUT_SKEW       verilog_node "`RST.tcu_rst_efu_done";
//   input       tcu_bisx_done                  INPUT_EDGE INPUT_SKEW       verilog_node "`RST.tcu_bisx_done";
//   input       tcu_rst_flush_init_ack         INPUT_EDGE INPUT_SKEW       verilog_node "`RST.tcu_rst_flush_init_ack";
//   input       tcu_rst_flush_stop_ack         INPUT_EDGE INPUT_SKEW       verilog_node "`RST.tcu_rst_flush_stop_ack";
//
// }
//
//
//
//
// port RST_port {
//   clk_l2clk;
//   ccu_rst_sync_stable;
//   tcu_rst_asicflush_stop_ack;
//   rst_tcu_asicflush_stop_req;
//   rst_tcu_flush_stop_req;
//   tcu_rst_efu_done;
//   tcu_bisx_done;
//   tcu_rst_flush_init_ack;
//   rst_ncu_unpark_thread;
//   tcu_rst_flush_stop_ack;
// }
//
// bind RST_port rst_bind {
//   clk_l2clk                  rst_l2clk.clk_l2clk;
//   ccu_rst_sync_stable                rst_l2clk.ccu_rst_sync_stable;
//   tcu_rst_asicflush_stop_ack rst_l2clk.tcu_rst_asicflush_stop_ack;
//   rst_tcu_asicflush_stop_req rst_l2clk.rst_tcu_asicflush_stop_req;
//   rst_tcu_flush_stop_req     rst_l2clk.rst_tcu_flush_stop_req;
//   tcu_rst_efu_done           rst_l2clk.tcu_rst_efu_done;
//   tcu_bisx_done                      rst_l2clk.tcu_bisx_done;
//   tcu_rst_flush_init_ack     rst_l2clk.tcu_rst_flush_init_ack;
//   rst_ncu_unpark_thread              rst_iol2clk.rst_ncu_unpark_thread;
//   tcu_rst_flush_stop_ack     rst_l2clk.tcu_rst_flush_stop_ack;
// }

interface bscann {
  input  TCK                    CLOCK                    verilog_node "`TOP.tck" ;
}

port BSCAN_port {
  tck;
}

bind BSCAN_port bscann_bind {
  tck                             bscann.TCK;
}


interface ccu_pll_sys_clk_p_ifn {
  input pll_sys_clk_p                 PSAMPLE #-1  verilog_node "`CCU.pll_sys_clk_p";
}

port CCU_clk_portn {
   sys_clk;
}

bind CCU_clk_portn ccu_clk_bindn {
  sys_clk               ccu_pll_sys_clk_p_ifn.pll_sys_clk_p;
}


interface efusen {
  input [6:0] sbc_efa_word_addr INPUT_EDGE INPUT_SKEW  verilog_node "`EFU.sbc_efa_word_addr";
}

port EFUSE_port {
  efusen_sbc_efa_word_addr;
}

bind EFUSE_port efusen_bind {
  efusen_sbc_efa_word_addr      efusen.sbc_efa_word_addr;
}

interface pkgn_if {
  input   clk              CLOCK        verilog_node "`CPU.PLL_CMP_CLK_P";       // review: need to use an always running IO2X clk
  input        TRIGOUT            PSAMPLE #-1  verilog_node "`CPU.TRIGOUT";
  output [165:0] DBG_DQ_out NHOLD        verilog_node "`CPU.DBG_DQ";
}

port PKGn_port {
 TRIGOUTn;
 DBG_DQ_outn;
}

bind  PKGn_port pkgn_bind {
  TRIGOUTn              pkgn_if.TRIGOUT;
  DBG_DQ_outn           pkgn_if.DBG_DQ_out;
}
 //[136]

// interface sc {
//   input  clk                   CLOCK                          verilog_node "`CPU.PLL_CMP_CLK_P";
//   output POR_L                 OUTPUT_EDGE_N         verilog_node "`CPU.PWRON_RST_L";
//   output PB_XIR_L              OUTPUT_EDGE_N         verilog_node "`CPU.BUTTON_XIR_L";
//   output PB_RST_L              OUTPUT_EDGE_N         verilog_node "`CPU.PB_RST_L";
//   output TRST_L              OUTPUT_EDGE_N           verilog_node "`CPU.TRST_L";
// }
//
// port SC_port {
//   clk;
//   por_;
//   pb_xir_;
//   pb_rst_;
//   trst_l;
// }
//
// bind SC_port sc_bind {
//   clk                 sc.clk;
//   por_                sc.POR_L;
//   pb_xir_             sc.PB_XIR_L;
//   pb_rst_             sc.PB_RST_L;
//   trst_l              sc.TRST_L;
// }

interface mbistn {
 //  input       TCK                      CLOCK                   verilog_node "`TCU.gclk";
  input  mbist_l2tag_read_l2t0  INPUT_EDGE INPUT_SKEW   verilog_node "`CPU.l2t0.mbist.mbist_l2tag_read";
}

port MBIST_port {
    mbistn_l2tag_read_l2t0;
}

bind MBIST_port mbistn_bind {
  mbistn_l2tag_read_l2t0            mbistn.mbist_l2tag_read_l2t0;
}


#endif