| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2jbi.vr |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | #include <vera_defines.vrh> |
| 36 | // #include "defines.vri" |
| 37 | #include<ccxDevicesDefines.vri> |
| 38 | #include<defines.vri> |
| 39 | #include<l2jbi_ports_binds.vrh> |
| 40 | //#include<iop_rtl.h> |
| 41 | //#include<ccm_top.if.vrh> |
| 42 | #include<std_display_class.vrh> |
| 43 | #include<std_display_defines.vri> |
| 44 | #include "globals.vri" |
| 45 | |
| 46 | #define JBI 38 |
| 47 | //#define JBI_REQTYPE 17:15 |
| 48 | #define RDD 21 |
| 49 | #define CTAG_UPPER 19:18 |
| 50 | //#define CTAG_LOWER 12:3 |
| 51 | #define JBI_RDD 2'b00 |
| 52 | #define JBI_WRI 2'b01 |
| 53 | #define JBI_WR8 2'b10 |
| 54 | |
| 55 | |
| 56 | #define myname "CheckJbiInvBeforeAck" |
| 57 | |
| 58 | |
| 59 | |
| 60 | class JbiClass { |
| 61 | bit isWRI; |
| 62 | bit [39:0] address; |
| 63 | bit [15:0] ctag; |
| 64 | bit [31:0] ack; |
| 65 | bit inv_before_ack; |
| 66 | bit [7:0] sctag_cpx_req; |
| 67 | bit [CPX_WIDTH-1:0] sctag_cpx_data; |
| 68 | |
| 69 | task new() { |
| 70 | inv_before_ack = 1'b0; |
| 71 | isWRI = 1'b0; |
| 72 | } |
| 73 | } |
| 74 | |
| 75 | |
| 76 | task CheckJbiInvBeforeAck() { |
| 77 | |
| 78 | //local StandardDisplay dbg; |
| 79 | // string myname; |
| 80 | shadow integer i; |
| 81 | l2jbi_port l2jbi_bind[8]; |
| 82 | shadow l2jbi_port lp; |
| 83 | |
| 84 | integer monitor_on = 1; |
| 85 | if (get_plus_arg(CHECK, "l2jbi_chk_off")) |
| 86 | { |
| 87 | monitor_on = 0; |
| 88 | } |
| 89 | |
| 90 | // dbg = new; |
| 91 | |
| 92 | // assign l2jbi_bind_N (defined in l2jbi_ports_binds.vrh) to the array of l2jbi_ports |
| 93 | l2jbi_bind[0] = l2jbi_bind_0; |
| 94 | l2jbi_bind[1] = l2jbi_bind_1; |
| 95 | l2jbi_bind[2] = l2jbi_bind_2; |
| 96 | l2jbi_bind[3] = l2jbi_bind_3; |
| 97 | l2jbi_bind[4] = l2jbi_bind_4; |
| 98 | l2jbi_bind[5] = l2jbi_bind_5; |
| 99 | l2jbi_bind[6] = l2jbi_bind_6; |
| 100 | l2jbi_bind[7] = l2jbi_bind_7; |
| 101 | |
| 102 | // dbg.dispmon(myname, MON_NORMAL, psprintf("%0d: L2JBI (inv before ack) Monitor started\n", get_time(LO))); |
| 103 | PR_NORMAL(myname, MON_NORMAL, psprintf("%0d: L2JBI (inv before ack) Monitor started\n", get_time(LO))); |
| 104 | //printf("%0d: L2JBI (inv before ack) Monitor started\n", get_time(LO)); |
| 105 | |
| 106 | for(i=0; i<8; i++) { |
| 107 | fork |
| 108 | /// Ensure that the L2 sends requests to the CPX for WR8/WRI invalidations before sending the WR8/WRI ack |
| 109 | { |
| 110 | integer l2_semph_id = alloc(SEMAPHORE, 0, 1,1); |
| 111 | lp = l2jbi_bind[i]; |
| 112 | |
| 113 | while(monitor_on) { |
| 114 | // Wait for WR8/WRI hit or dependent (i.e. not miss) to hit the cache. |
| 115 | if(lp.$arb_inst_vld_c2 && !lp.$arbdec_arbdp_inst_fb_c2 && |
| 116 | lp.$arbdp_inst_c2[JBI] && !lp.$arbdp_inst_c2[RDD] && |
| 117 | lp.$tag_hit_l2orfb_c2 && (lp.$arbdec_arbdp_inst_dep_c2 || !lp.$arbdec_arbdp_inst_mb_c2)) { |
| 118 | fork |
| 119 | { |
| 120 | WaitForInvAndAck(lp, l2_semph_id); |
| 121 | } |
| 122 | join none |
| 123 | } |
| 124 | |
| 125 | @(posedge l2jbi.ccx_rclk); |
| 126 | } // while(1) |
| 127 | } |
| 128 | join none |
| 129 | } // for(i=0; i<8; i++) |
| 130 | |
| 131 | } |
| 132 | |
| 133 | |
| 134 | task WaitForInvAndAck(l2jbi_port lp, integer l2_semph_id) { |
| 135 | integer maxWait = 2500; // was 500 |
| 136 | integer j; |
| 137 | bit [7:0] sctag_cpx_req_cq, sctag_cpx_req_cq_d1; |
| 138 | JbiClass jbi; |
| 139 | |
| 140 | jbi = new(); |
| 141 | |
| 142 | // C2 at this point |
| 143 | //jbi.reqtype = lp.$arbdp_inst_c2[JBI_REQTYPE]; |
| 144 | if(lp.$arbdp_inst_c2[22]){ |
| 145 | jbi.isWRI = 1'b0; |
| 146 | } |
| 147 | else if(lp.$arbdp_inst_c2[23]){ |
| 148 | jbi.isWRI = 1'b1; |
| 149 | } |
| 150 | else{ |
| 151 | error("%0d: L2JBI: Unexpected JBI request type\n\n", get_time(LO)); |
| 152 | } |
| 153 | |
| 154 | jbi.address = lp.$arbdp_addr_c2; |
| 155 | //jbi.ctag = {lp.$arbdp_inst_c2[CTAG_UPPER], lp.$arbdp_inst_c2[CTAG_LOWER]}; |
| 156 | jbi.ctag = lp.$arbdp_inst_c2[15:0]; |
| 157 | jbi.ack = {8'bXXXXXXXX, 8'bXXXXXXXX, jbi.ctag}; |
| 158 | //jbi.ack = {17'b0, jbi.address[1:0], jbi.reqtype[0], jbi.ctag}; |
| 159 | |
| 160 | PR_NORMAL(myname, MON_NORMAL, psprintf("%0d: WaitForInvAndAck started for %s (ctag = %x, addr = %x)\n", get_time(LO), jbi.isWRI ? "WRI" : "WR8", jbi.ctag, jbi.address)); |
| 161 | |
| 162 | fork |
| 163 | { |
| 164 | // wait till C6 (req_out_c6 is asserted 4 cycles after tagctl_hit_l2orfb_c2 for WR8s/WRIs) |
| 165 | repeat(4 + 1) @(posedge l2jbi.ccx_rclk); |
| 166 | jbi.sctag_cpx_req = lp.$req_out_c6; |
| 167 | |
| 168 | // WR8/WRI causes L1 invalidations |
| 169 | if(jbi.sctag_cpx_req != 8'b0) { |
| 170 | // wait till C7 |
| 171 | @(posedge l2jbi.ccx_rclk); |
| 172 | jbi.sctag_cpx_data = {1'b1, CPX_EVICT, 3'b0, 9'bx, 1'b0, lp.$ext_inval_data_c7}; //<MOD> |
| 173 | |
| 174 | j = 0; |
| 175 | while(j++ < maxWait) { |
| 176 | sctag_cpx_req_cq_d1 = sctag_cpx_req_cq; |
| 177 | sctag_cpx_req_cq = lp.$sctag_cpx_req_cq; |
| 178 | |
| 179 | // match both sctag_cpx_req_cq and sctag_cpx_data_ca |
| 180 | if(sctag_cpx_req_cq_d1 == jbi.sctag_cpx_req && lp.$sctag_cpx_data_ca =?= jbi.sctag_cpx_data) { |
| 181 | jbi.inv_before_ack = 1'b1; |
| 182 | break; |
| 183 | } |
| 184 | @(posedge l2jbi.ccx_rclk); |
| 185 | } |
| 186 | if(j > maxWait) |
| 187 | error("%0d: L2JBI: Timeout waiting for CPX requests for WR8/WRI invalidations\n\n", get_time(LO)); |
| 188 | } |
| 189 | // no L1 invalidations |
| 190 | else |
| 191 | jbi.inv_before_ack = 1'b1; |
| 192 | } |
| 193 | { |
| 194 | // only one monitor can be waiting for lp.$oqu_st_complete_c6 == 1'b1 |
| 195 | semaphore_get (WAIT, l2_semph_id, 1); |
| 196 | |
| 197 | // Wait for oqctl_st_complete_c6 to be asserted, because scbuf_jbi_ctag_vld is always asserted |
| 198 | // exactly 7 cycles after oqctl_st_complete_c6. |
| 199 | // Only 1 WR8/WRI will be issued out of the MB and waiting for store completion at any time. |
| 200 | @1,maxWait lp.$oqu_st_complete_c6 == 1'b1; |
| 201 | |
| 202 | semaphore_put (l2_semph_id, 1); // let other monitors get started |
| 203 | |
| 204 | // ack arrives exactly 7 cycles after oqctl_st_complete_c6 |
| 205 | // Expecting the ack in the exact cycle is necessary because the diags issue different WR8s/WRIs with |
| 206 | // the same ctag, which results in non-unique acks. |
| 207 | @7 lp.$l2b_sio_ctag_vld == 1'b1, lp.$l2b_sio_data == jbi.ack; |
| 208 | |
| 209 | // check that CPX request for INV was sent before JBI ack |
| 210 | if(!jbi.inv_before_ack) { |
| 211 | error("%0d: L2JBI: %s ack sent to JBI before invalidations were sent to cores (ctag = %x, addr = %x)\n\n", |
| 212 | get_time(LO), jbi.isWRI ? "WRI" : "WR8", jbi.ctag, jbi.address); |
| 213 | } |
| 214 | |
| 215 | // optional: print out message when inv-before-ack condition is satisfied |
| 216 | if(jbi.sctag_cpx_req != 8'b0) { |
| 217 | PR_NORMAL(myname, MON_NORMAL, psprintf("%0d: L2JBI: inv-before-ack condition satisfied for %s (ctag = %x, addr = %x)\n", get_time(LO), jbi.isWRI ? "WRI" : "WR8", jbi.ctag, jbi.address)); |
| 218 | } |
| 219 | } |
| 220 | join all |
| 221 | |
| 222 | } |