| 1 | // ========== Copyright Header Begin ========================================== |
| 2 | // |
| 3 | // OpenSPARC T2 Processor File: l2_offmode_directmap_insts_sample.vrhpal |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. |
| 6 | // |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. |
| 8 | // |
| 9 | // This program is free software; you can redistribute it and/or modify |
| 10 | // it under the terms of the GNU General Public License as published by |
| 11 | // the Free Software Foundation; version 2 of the License. |
| 12 | // |
| 13 | // This program is distributed in the hope that it will be useful, |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 16 | // GNU General Public License for more details. |
| 17 | // |
| 18 | // You should have received a copy of the GNU General Public License |
| 19 | // along with this program; if not, write to the Free Software |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 21 | // |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license |
| 23 | // choice is available it will apply instead, Sun elects to use only |
| 24 | // the General Public License version 2 (GPLv2) at this time for any |
| 25 | // software where a choice of GPL license versions is made |
| 26 | // available with the language indicating that GPLv2 or any later version |
| 27 | // may be used, or where a choice of which version of the GPL is applied is |
| 28 | // otherwise unspecified. |
| 29 | // |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or |
| 32 | // have any questions. |
| 33 | // |
| 34 | // ========== Copyright Header End ============================================ |
| 35 | wildcard state LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 36 | wildcard state LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 37 | //wildcard state LOAD_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 38 | |
| 39 | // PREFETCH off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 40 | wildcard state PREFETCH_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); |
| 41 | wildcard state PREFETCH_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); |
| 42 | //wildcard state PREFETCH_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b1, 1'b0} ); |
| 43 | |
| 44 | // DIAG_LOAD off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 45 | wildcard state DIAG_LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b1, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 46 | wildcard state DIAG_LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b1, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 47 | //wildcard state DIAG_LOAD_both( {1'b1, 1'b1, 1'b1, 1'b1, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 48 | |
| 49 | // DCACHE_INV off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 50 | wildcard state DCACHE_INV_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); |
| 51 | wildcard state DCACHE_INV_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); |
| 52 | //wildcard state DCACHE_INV_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); |
| 53 | |
| 54 | // IMISS off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 55 | wildcard state IMISS_off ( {1'b1, 1'b0, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 56 | wildcard state IMISS_dmap( {1'b0, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 57 | //wildcard state IMISS_both( {1'b1, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 58 | |
| 59 | // ICACHE_INV off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 60 | wildcard state ICACHE_INV_off ( {1'b1, 1'b0, 1'b1, 1'b0, IMISS_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); |
| 61 | wildcard state ICACHE_INV_dmap( {1'b0, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); |
| 62 | //wildcard state ICACHE_INV_both( {1'b1, 1'b1, 1'b1, 1'b0, IMISS_RQ, 1'b0, 1'b0, 6'bx, 1'b1, 1'b0, 1'b0} ); |
| 63 | |
| 64 | // STORE off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 65 | wildcard state STORE_off ( {1'b1, 1'b0, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 66 | wildcard state STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 67 | //wildcard state STORE_both( {1'b1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 68 | |
| 69 | // BLKSTORE off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 70 | wildcard state BLKSTORE_off ( {1'b1, 1'b0, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); |
| 71 | wildcard state BLKSTORE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); |
| 72 | //wildcard state BLKSTORE_both( {1'b1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b1, 1'b1} ); |
| 73 | |
| 74 | // BLKINITST off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 75 | wildcard state BLKINITST_off ( {1'b1, 1'b0, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); |
| 76 | wildcard state BLKINITST_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); |
| 77 | //wildcard state BLKINITST_both( {1'b1, 1'b1, 1'b1, 1'b0, STORE_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b1} ); |
| 78 | |
| 79 | // DIAG_STORE off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 80 | wildcard state DIAG_STORE_off ( {1'b1, 1'b0, 1'b1, 1'b1, STORE_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 81 | wildcard state DIAG_STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b1, STORE_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 82 | //wildcard state DIAG_STORE_both( {1'b1, 1'b1, 1'b1, 1'b1, STORE_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 83 | |
| 84 | // CAS1 off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 85 | wildcard state CAS1_off ( {1'b1, 1'b0, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 86 | wildcard state CAS1_dmap( {1'b0, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 87 | //wildcard state CAS1_both( {1'b1, 1'b1, 1'b1, 1'b0, CAS1_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 88 | |
| 89 | // CAS2 off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 90 | wildcard state CAS2_off ( {1'b1, 1'b0, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 91 | wildcard state CAS2_dmap( {1'b0, 1'b1, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 92 | //wildcard state CAS2_both( {1'b1, 1'b1, 1'b1, 1'b0, CAS2_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 93 | |
| 94 | // SWAP off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 95 | wildcard state SWAP_off ( {1'b1, 1'b0, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 96 | wildcard state SWAP_dmap( {1'b0, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 97 | //wildcard state SWAP_both( {1'b1, 1'b1, 1'b1, 1'b0, SWAP_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 98 | |
| 99 | // STRLOAD off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 100 | wildcard state STRLOAD_off ( {1'b1, 1'b0, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 101 | wildcard state STRLOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 102 | //wildcard state STRLOAD_both( {1'b1, 1'b1, 1'b1, 1'b0, STRLOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 103 | |
| 104 | // STRST off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 105 | wildcard state STRST_off ( {1'b1, 1'b0, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 106 | wildcard state STRST_dmap( {1'b0, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 107 | //wildcard state STRST_both( {1'b1, 1'b1, 1'b1, 1'b0, STRST_RQ, 1'bx, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 108 | |
| 109 | /* |
| 110 | // FWDRQ_LOAD off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 111 | wildcard state FWDRQ_LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 112 | wildcard state FWDRQ_LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 113 | //wildcard state FWDRQ_LOAD_both( {1'b1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 114 | |
| 115 | // FWDRQ_STORE off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 116 | wildcard state FWDRQ_STORE_off ( {1'b1, 1'b0, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 117 | wildcard state FWDRQ_STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 118 | //wildcard state FWDRQ_STORE_both( {1'b1, 1'b1, 1'b1, 1'b0, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 119 | |
| 120 | // FWDRQ_DIAG_LOAD off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 121 | wildcard state FWDRQ_DIAG_LOAD_off ( {1'b1, 1'b0, 1'b1, 1'b1, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 122 | wildcard state FWDRQ_DIAG_LOAD_dmap( {1'b0, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 123 | //wildcard state FWDRQ_DIAG_LOAD_both( {1'b1, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b1, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 124 | |
| 125 | // FWDRQ_DIAG_STORE off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 126 | wildcard state FWDRQ_DIAG_STORE_off ( {1'b1, 1'b0, 1'b1, 1'b1, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 127 | wildcard state FWDRQ_DIAG_STORE_dmap( {1'b0, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 128 | //wildcard state FWDRQ_DIAG_STORE_both( {1'b1, 1'b1, 1'b1, 1'b1, FWD_RQ, 1'b0, 1'b0, 6'bx, 1'b0, 1'b0, 1'b0} ); |
| 129 | */ |
| 130 | |
| 131 | // PREFETCH_ICE off dmap vld diag reqtype nc jbi cputh inv pf bis |
| 132 | wildcard state PFICE_off ( {1'b1, 1'b0, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); |
| 133 | wildcard state PFICE_dmap( {1'b0, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); |
| 134 | //wildcard state PFICE_both( {1'b1, 1'b1, 1'b1, 1'b0, LOAD_RQ, 1'b1, 1'b0, 6'bx, 1'b1, 1'b1, 1'b0} ); |
| 135 | |
| 136 | // RDD off dmap vld diag reqtype nc jbi |
| 137 | wildcard state RDD_off ( {1'b1, 1'b0, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); |
| 138 | wildcard state RDD_dmap( {1'b0, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); |
| 139 | //wildcard state RDD_both( {1'b1, 1'b1, 1'b1, 1'b0, 5'bxx001, 1'b0, 1'b1, 9'bx} ); |
| 140 | |
| 141 | // WR8 off dmap vld diag reqtype nc jbi |
| 142 | wildcard state WR8_off ( {1'b1, 1'b0, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); |
| 143 | wildcard state WR8_dmap( {1'b0, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); |
| 144 | //wildcard state WR8_both( {1'b1, 1'b1, 1'b1, 1'b0, 5'bxx010, 1'b0, 1'b1, 9'bx} ); |
| 145 | |
| 146 | // WRI off dmap vld diag reqtype nc jbi |
| 147 | wildcard state WRI_off ( {1'b1, 1'b0, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); |
| 148 | wildcard state WRI_dmap( {1'b0, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); |
| 149 | //wildcard state WRI_both( {1'b1, 1'b1, 1'b1, 1'b0, 5'bxx100, 1'b0, 1'b1, 9'bx} ); |