// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_cmu_ctx_aloc.v
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module dmu_cmu_ctx_aloc (
//************************************************
//************************************************
parameter WIDTH = 5; // max width supported
parameter DEPTH = 32; // max depth supported
//************************************************
//************************************************
input clk; // The input clock
input rst_l; // synopsys sync_set_reset "rst_l"
input enq; // enqueue into fifo
input [WIDTH - 1:0] data_in; // data to put in
input deq; // dequeue outof fifo
output [WIDTH - 1:0] data_out; // data taken out
output valid; // full flag
//************************************************
//************************************************
reg [DEPTH - 1:0] vld; // current location has valid data
reg [WIDTH - 1:0] count; // # valid contents in fifo
//*********************************************
// list counter, updates on deq asserted
//*********************************************
1'b1: count <= count + 1'b1;
//*********************************************
// valid contents, updates when enq asserted
//*********************************************
for ( n = 0; n < DEPTH ; n = n+1)
case ({enq, deq}) // synopsys parallel_case
2'b01 : vld[count] <= 1'b0;
2'b10 : vld[data_in] <= 1'b1;
for ( n = 0; n < DEPTH ; n = n+1)
endcase // case({enq, deq})
end // always @ (posedge clk)
//************************************************
//************************************************
assign data_out = count[WIDTH -1 :0];
assign valid = vld[count];