// ========== Copyright Header Begin ==========================================
// OpenSPARC T2 Processor File: dmu_cru_csr_dmc_dbg_sel_b_reg.v
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module dmu_cru_csr_dmc_dbg_sel_b_reg
dmc_dbg_sel_b_reg_csrbus_read_data,
dmc_dbg_sel_b_reg_block_sel_hw_read,
dmc_dbg_sel_b_reg_sub_sel_hw_read,
dmc_dbg_sel_b_reg_signal_sel_hw_read
//====================================================================
//====================================================================
input rst_l; // Reset signal
input dmc_dbg_sel_b_reg_w_ld; // SW load bus
input [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH-1:0] dmc_dbg_sel_b_reg_csrbus_read_data;
output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_INT_SLC] dmc_dbg_sel_b_reg_block_sel_hw_read;
// This signal provides the current value of dmc_dbg_sel_b_reg_block_sel.
output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_INT_SLC] dmc_dbg_sel_b_reg_sub_sel_hw_read;
// This signal provides the current value of dmc_dbg_sel_b_reg_sub_sel.
output [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_INT_SLC] dmc_dbg_sel_b_reg_signal_sel_hw_read;
// This signal provides the current value of dmc_dbg_sel_b_reg_signal_sel.
//====================================================================
//====================================================================
wire rst_l; // Reset signal
wire dmc_dbg_sel_b_reg_w_ld; // SW load bus
wire [`FIRE_CSRBUS_DATA_WIDTH-1:0] csrbus_wr_data; // SW write data
wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH-1:0] dmc_dbg_sel_b_reg_csrbus_read_data;
wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_INT_SLC] dmc_dbg_sel_b_reg_block_sel_hw_read;
// This signal provides the current value of dmc_dbg_sel_b_reg_block_sel.
wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_INT_SLC] dmc_dbg_sel_b_reg_sub_sel_hw_read;
// This signal provides the current value of dmc_dbg_sel_b_reg_sub_sel.
wire [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_INT_SLC] dmc_dbg_sel_b_reg_signal_sel_hw_read;
// This signal provides the current value of dmc_dbg_sel_b_reg_signal_sel.
//====================================================================
//====================================================================
// synopsys translate_off
reg [`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH-1:0] omni_data;
// vlint flag_unsynthesizable_initial off
omni_data = `FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_WIDTH'b0;
end// vlint flag_unsynthesizable_initial on
//----- Hardware Data Out Mux Assignments
assign dmc_dbg_sel_b_reg_block_sel_hw_read=
dmc_dbg_sel_b_reg_csrbus_read_data
[`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_BLOCK_SEL_SLC];
assign dmc_dbg_sel_b_reg_sub_sel_hw_read=
dmc_dbg_sel_b_reg_csrbus_read_data
[`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SUB_SEL_SLC];
assign dmc_dbg_sel_b_reg_signal_sel_hw_read=
dmc_dbg_sel_b_reg_csrbus_read_data
[`FIRE_DLC_CRU_CSR_DMC_DBG_SEL_B_REG_SIGNAL_SEL_SLC];
//====================================================================
// Instantiation of entries
//====================================================================
dmu_cru_csr_dmc_dbg_sel_b_reg_entry dmc_dbg_sel_b_reg_0
// synopsys translate_off
.w_ld (dmc_dbg_sel_b_reg_w_ld),
.csrbus_wr_data (csrbus_wr_data),
.dmc_dbg_sel_b_reg_csrbus_read_data (dmc_dbg_sel_b_reg_csrbus_read_data)
endmodule // dmu_cru_csr_dmc_dbg_sel_b_reg