* ========== Copyright Header Begin ==========================================
* OpenSPARC T2 Processor File: dmu_imu_eqs_defines.h
* Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
* 4150 Network Circle, Santa Clara, California 95054, U.S.A.
* DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
* For the avoidance of doubt, and except that if any non-GPL license
* choice is available it will apply instead, Sun elects to use only
* the General Public License version 2 (GPLv2) at this time for any
* software where a choice of GPL license versions is made
* available with the language indicating that GPLv2 or any later version
* may be used, or where a choice of which version of the GPL is applied is
* Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
* CA 95054 USA or visit www.sun.com if you need additional information or
* ========== Copyright Header End ============================================
`ifdef FIRE_DLC_IMU_EQS_DEFINES
`define FIRE_DLC_IMU_EQS_DEFINES
`define FIRE_DLC_IMU_EQS_INSTANCE_ID_VALUE_A
1'h0
`define FIRE_DLC_IMU_EQS_INSTANCE_ID_VALUE_B
1'h1
//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_base_address
//-------------------------------------------------------
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_HW_ADDR
27'b000000011000010000000000000
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_BASE_ADDRESS_ADDR
30'b000000011000010000000000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_BASE_ADDRESS_HW_ADDR
27'b000000011100010000000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_BASE_ADDRESS_ADDR
30'b000000011100010000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WIDTH
64
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_DEPTH
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_INT_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_LOW_ADDR_WIDTH
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDR_RANGE
26:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_READ_MASK
64'b1111111111111111111111111111111111111111111110000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_READ_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WRITE_MASK
64'b1111111111111111111111111111111111111111111110000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_WRITE_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_SET_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_CLEAR_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_TOGGLE_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_RMASK
64'b1111111111111111111111111111111111111111111110000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_RESERVED_BIT_MASK
64'b0000000000000000000000000000000000000000000001111111111111111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_POR_VALUE
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_INTERNAL_REG
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ZERO_TIME_OMNI
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_NUM_FIELDS
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_FID
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_SLC
63:19
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_WIDTH
45
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_INT_SLC
44:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_POSITION
19
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_FMASK
64'b1111111111111111111111111111111111111111111110000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_BASE_ADDRESS_ADDRESS_POR_VALUE
45'b000000000000000000000000000000000000000000000
//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_ctrl_set
//-------------------------------------------------------
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_HW_ADDR
27'b000000011000010001000000000
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_SET_ADDR
30'b000000011000010001000000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_SET_HW_ADDR
27'b000000011100010001000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_SET_ADDR
30'b000000011100010001000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_WIDTH
64
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_DEPTH
36
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_INT_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_LOW_ADDR_WIDTH
6
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_SEL_RANGE
5:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ADDR_RANGE
26:6
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_READ_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_READ_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_WRITE_MASK
64'b0000001000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_WRITE_ONLY_MASK
64'b0000001000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_SET_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_CLEAR_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_TOGGLE_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_RMASK
64'b0000001000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_RESERVED_BIT_MASK
64'b1111110111111111111011111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_POR_VALUE
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_INTERNAL_REG
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EXTERNAL_DECODE_REG
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ZERO_TIME_OMNI
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_NUM_FIELDS
2
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_FID
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_SLC
57:57
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_WIDTH
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_INT_SLC
0:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_POSITION
57
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_FMASK
64'b0000001000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_ENOVERR_POR_VALUE
1'b0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_FID
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_SLC
44:44
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_WIDTH
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_INT_SLC
0:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_POSITION
44
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_FMASK
64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_SET_EN_POR_VALUE
1'b0
//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_ctrl_clr
//-------------------------------------------------------
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_HW_ADDR
27'b000000011000010001001000000
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_CTRL_CLR_ADDR
30'b000000011000010001001000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_CLR_HW_ADDR
27'b000000011100010001001000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_CTRL_CLR_ADDR
30'b000000011100010001001000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_WIDTH
64
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DEPTH
36
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_INT_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_LOW_ADDR_WIDTH
6
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_SEL_RANGE
5:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_ADDR_RANGE
26:6
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_READ_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_READ_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_WRITE_MASK
64'b0000001000000000100100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_WRITE_ONLY_MASK
64'b0000001000000000100100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_SET_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_CLEAR_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_TOGGLE_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_RMASK
64'b0000001000000000100100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_RESERVED_BIT_MASK
64'b1111110111111111011011111111111111111111111111111111111111111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_POR_VALUE
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_INTERNAL_REG
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_EXTERNAL_DECODE_REG
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_ZERO_TIME_OMNI
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_NUM_FIELDS
3
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_FID
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_SLC
57:57
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_WIDTH
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_INT_SLC
0:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_POSITION
57
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_FMASK
64'b0000001000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_COVERR_POR_VALUE
1'b0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_FID
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_SLC
47:47
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_WIDTH
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_INT_SLC
0:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_POSITION
47
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_FMASK
64'b0000000000000000100000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_E2I_POR_VALUE
1'b0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_FID
2
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_SLC
44:44
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_WIDTH
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_INT_SLC
0:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_POSITION
44
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_FMASK
64'b0000000000000000000100000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_CTRL_CLR_DIS_POR_VALUE
1'b0
//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_state
//-------------------------------------------------------
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_HW_ADDR
27'b000000011000010001010000000
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_STATE_ADDR
30'b000000011000010001010000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_STATE_HW_ADDR
27'b000000011100010001010000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_STATE_ADDR
30'b000000011100010001010000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_WIDTH
64
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_DEPTH
36
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_INT_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_LOW_ADDR_WIDTH
6
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_SEL_RANGE
5:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_ADDR_RANGE
26:6
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_READ_MASK
64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_READ_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_WRITE_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_WRITE_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_SET_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_CLEAR_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_TOGGLE_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_RMASK
64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_RESERVED_BIT_MASK
64'b1111111111111111111111111111111111111111111111111111111111111000
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_POR_VALUE
64'b0000000000000000000000000000000000000000000000000000000000000001
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_INTERNAL_REG
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_EXTERNAL_DECODE_REG
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_ZERO_TIME_OMNI
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_NUM_FIELDS
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_FID
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_SLC
2:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_WIDTH
3
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_INT_SLC
2:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_FMASK
64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000111
`define FIRE_DLC_IMU_EQS_CSR_EQ_STATE_STATE_POR_VALUE
3'b001
//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_tail
//-------------------------------------------------------
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_HW_ADDR
27'b000000011000010001011000000
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_TAIL_ADDR
30'b000000011000010001011000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_TAIL_HW_ADDR
27'b000000011100010001011000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_TAIL_ADDR
30'b000000011100010001011000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WIDTH
64
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_DEPTH
36
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_INT_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_LOW_ADDR_WIDTH
6
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_SEL_RANGE
5:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_ADDR_RANGE
26:6
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_READ_MASK
64'b0000001000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_READ_ONLY_MASK
64'b0000001000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WRITE_MASK
64'b0000000000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_WRITE_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_SET_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_CLEAR_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TOGGLE_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_RMASK
64'b0000001000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_RESERVED_BIT_MASK
64'b1111110111111111111111111111111111111111111111111111111110000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_HW_LD_MASK
64'b0000001000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_POR_VALUE
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_INTERNAL_REG
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_ZERO_TIME_OMNI
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_NUM_FIELDS
2
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_FID
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_SLC
57:57
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_WIDTH
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_INT_SLC
0:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_POSITION
57
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_FMASK
64'b0000001000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_HW_LD_MASK
64'b0000001000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_OVERR_POR_VALUE
1'b0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_FID
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_SLC
6:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_WIDTH
7
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_INT_SLC
6:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_FMASK
64'b0000000000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_TAIL_TAIL_POR_VALUE
7'b0000000
//-------------------------------------------------------
//----- Variable definitions for register fire_dlc_imu_eqs_csr_eq_head
//-------------------------------------------------------
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_HW_ADDR
27'b000000011000010001100000000
`define FIRE_DLC_IMU_EQS_CSR_A_EQ_HEAD_ADDR
30'b000000011000010001100000000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_HEAD_HW_ADDR
27'b000000011100010001100000000
`define FIRE_DLC_IMU_EQS_CSR_B_EQ_HEAD_ADDR
30'b000000011100010001100000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WIDTH
64
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_DEPTH
36
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_INT_SLC
63:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_LOW_ADDR_WIDTH
6
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_SEL_RANGE
5:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_ADDR_RANGE
26:6
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_READ_MASK
64'b0000000000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_READ_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WRITE_MASK
64'b0000000000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_WRITE_ONLY_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_SET_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_CLEAR_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_TOGGLE_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_RMASK
64'b0000000000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_RESERVED_BIT_MASK
64'b1111111111111111111111111111111111111111111111111111111110000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_POR_VALUE
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_INTERNAL_REG
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_ZERO_TIME_OMNI
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_NUM_FIELDS
1
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_FID
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_SLC
6:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_WIDTH
7
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_INT_SLC
6:0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_POSITION
0
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_FMASK
64'b0000000000000000000000000000000000000000000000000000000001111111
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_HW_LD_MASK
64'b0000000000000000000000000000000000000000000000000000000000000000
`define FIRE_DLC_IMU_EQS_CSR_EQ_HEAD_HEAD_POR_VALUE
7'b0000000